Abstract: A power detector with wide dynamic range. The power detector includes a linear detector, followed by a voltage-to-current-to-voltage converter, which is then followed by an amplification stage. The current-to-voltage conversion in the converter is performed logarithmically. The power detector generates a desired linear-in-dB response at the output. In this power detector, the distribution of gain along the signal path is optimized in order to preserve linearity, and to minimize the impact of offset voltage inherently present in electronic blocks, which would corrupt the output voltage. Further, the topologies in the sub-blocks are designed to provide wide dynamic range, and to mitigate error sources. Moreover, the temperature sensitivity is designed out by either minimizing temperature variation of an individual block such as the v-i-v detector, or using two sub-blocks in tandem to provide overall temperature compensation.

Abstract: An angle sensor generates an angle detection value based on a first and a second detection signal. A correction apparatus performs correction processing for generating a first corrected detection signal by adding a first correction value to the first detection signal and generating a second corrected detection signal by adding a second correction value to the second detection signal. When an angle to be detected varies with a period T and if no correction processing is performed, the angle detection value contains an Nth-order angle error component varying with a period of T/N. Each of the first and second detection signals contains an (N?1)th-order signal error component and an (N+1)th-order signal error component. The order of the first and second correction values is N?1 or N+1.

Abstract: A bias current generator circuit includes a current path and a leakage control circuit. The current path is connected between a supply voltage and a ground level. The current path includes a transistor and a resistor. The transistor has a current channel connected in the current path. The resistor has an upper terminal and a lower terminal connected in the current path, and a well contact to allow a reverse leakage current of the resistor to flow through. The leakage control circuit is connected to the supply voltage. The leakage control circuit includes a driving transistor to provide a driving voltage to the well contact of the resistor, and to allow the reverse leakage current of the resistor to flow into the leakage control circuit.

Abstract: Inductive wireless power transfer systems are provided for medical devices, such as implantable medical devices (IMDs). The systems may comprise a transmitter unit and a receiver unit and may be configured for transferring power and/or signals from the transmitter unit to the receiver unit and/or vice versa. The transmitter unit may comprise an energy source, a transmitter antenna, and a supply line connected in between the energy source and the antenna. The receiver unit may comprise a receiver antenna and a rectifier output. The transmitter antenna and the receiver antenna may be configured to provide a wireless power transfer link. The supply line may comprise a virtual resistance unit, which may be configured to provide a virtual resistance, which may be determined such that the rectifier output provides a substantially constant or less varying charge current over a predetermined distance range, for a large range of implant depths.

Abstract: A sample and hold circuit configured to sample a current includes an input node to receive the current, a capacitor coupled with a sampling node and a reference voltage node, switch between the input node and the sampling node, a controlled current source coupled to the input node, a current mirror circuit having connections each providing a mirrored current, wherein at least one of said connections provides an output node, and a transistor arrangement. The transistor arrangement includes a control MOSFET in series with a series connected chain of cascaded cells. The control MOSFET and each of said cascaded cells are coupled to the current mirror circuit and each of the cascaded cells includes a pair of MOSFETs arranged to provide a voltage difference including a difference between a gate-source voltage of a first of the pair and a gate-source voltage of a second of the pair.

Abstract: Pre-charging two or more sets of nodes to set a differential output of a multi-input summation latch connected to the two or more sets of nodes in a pre-charged state, the two or more sets of nodes comprising a set of data signal nodes and a set of DFE correction nodes, in response to a sampling clock, generating a differential data voltage and an aggregate differential DFE correction signal, and generating a data decision by driving the differential output of the multi-input summation latch into one of two possible output states according to a summation of the differential data voltage signal and the aggregate differential DFE correction signal and subsequently holding the data decision by holding the differential output of the multi-input summation latch in a latched state for a duration determined by the sampling clock.

Abstract: Disclosed herein is a voltage comparator including a first capacitor, a first inverter and a first switch connected in series and provided between both ends of the first capacitor, a second inverter connected in parallel with the first inverter, a second switch provided between an input and an output of the first inverter, a third switch provided between an input and an output of the second inverter, a second capacitor provided between the output of the first inverter and the input of the second inverter, a third capacitor provided between the output of the second inverter and the input of the first inverter, and a fourth switch provided in one of a position between an upper electrode of the first capacitor and a power supply line and a position between a lower electrode of the first capacitor and a ground line.

Abstract: A system and method for sensing drive current in a pixel. In some embodiments, the system includes: a first pixel, a second pixel, a differential sensing circuit, a reference current source, and a control circuit. The differential sensing circuit may have a first input, a second input, and an output, the first input being connected to a node at which a reference current generated by the reference current source is subtracted from a first pixel current, the first pixel current including a current generated by the first pixel. The second input may be configured to receive a second pixel current, the second pixel current including a current generated by the second pixel. The output may be configured to produce an output signal based on a difference between a current received at the first input and a current received at the second input.

Abstract: Aspects of the disclosure are directed to generating a reference voltage with trim adjustment. Accordingly, a reference voltage with trim adjustment is generating which involves generating a trim current using at least one of a plurality of selectable parallel elements; inputting the trim current to parallel resistor branches to generate a first scaled voltage; and combining a first voltage with the first scaled voltage to generate the reference voltage.

Abstract: A system includes multiple capacitive sensors, a multiplexer, a programmable gain amplifier, an oscillator, a switch, and a controller. The sensors are coupled to the multiplexer, the multiplexer is coupled to the switch, and the switch is coupled to the amplifier and the oscillator. The controller may control the multiplexer to select each of the sensors. The controller may control the switch to activate the amplifier or the oscillator. The controller may measure voltage output by the amplifier or frequency output by the oscillator. The system may be included in an occupant support such as a vehicle seat.

Abstract: Various embodiments relate to a method and apparatus for maintaining constant gain in an open loop gain stage amplifier, the circuit including a reference signal generator configured to generate a plurality of reference voltages, a gain compensation circuit, including a reference selector configured to select one of the plurality of reference voltages for each of a plurality of gain stages, an error amplifier configured to output a control voltage signal to a selector, a selector configured to select which of a plurality of degeneration resistors in the open loop gain stage amplifier to apply the control voltage signal wherein the voltage signal is applied to the gate of at least one of the plurality of degeneration resistors in the open loop gain stage amplifier.

Abstract: Disclosed are apparatuses and methods for controlling gate-induced drain leakage current in a transistor device. An apparatus may include a first biasing circuit stage configured to provide a biasing voltage on a biasing signal line, the biasing voltage based on a current through a first resistor associated with the first biasing circuit stage, a voltage generation circuit stage coupled to the first biasing circuit stage, the voltage generation circuit stage having an output transistor that is coupled to the biasing signal line through a gate terminal of the output transistor, and an output line coupled to the voltage generation circuit stage and configured to provide an output voltage signal having a steady-state voltage that is less than a power supply voltage by an amount that corresponds to a voltage drop across the first resistor associated with the first biasing circuit stage.

Abstract: An image sensor may contain an array of imaging pixels arranged in rows and columns. Each column of imaging pixels may be coupled to a column line which is used to read out imaging signals from the pixels. The column line may be coupled to an analog-to-digital converter for converting analog imaging signals from the pixels to digital signals. The analog-to-digital converter may be implemented as a charge sharing successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC may include a comparator coupled to a feedback digital-to-analog converter (DAC). The comparator may have a non-zero comparator offset. The feedback DAC may include capacitors that are scaled using a sub-radix-2 sizing scheme to help improve tolerance to the comparator offset while enabling resolutions of up to 10-bits or more.

Abstract: An example current limiting apparatus comprises a first transistor to carry a first current; a sense transistor coupled to the first transistor, the sense transistor to carry a sense current that is a function of the first current; a first amplifier coupled to the first transistor and the sense transistor, the amplifier to achieve a common voltage potential on terminals of the first and the sense transistors; a second amplifier coupled to the first amplifier and the sense transistor, the second amplifier to control the first and sense transistors based on the sense current; and a circuit coupled to the first and second amplifiers, the circuit to control an input to the second amplifier based on an input to the first amplifier such that a current limit of the first transistor remains below a programmed current limit of the first transistor.

Abstract: Adjustment of drive control based on a detection voltage of a transformer requires a loop time, and therefore high-speed processing of the adjustment is difficult. A semiconductor integrated circuit device includes a driving circuit that drives a power semiconductor device and a driving capability control circuit that controls a driving capability of the driving circuit. The driving circuit stops driving of the power semiconductor device based on an abnormal current detected from a sense current of the power semiconductor device. The driving capability control circuit controls the driving capability of the driving circuit based on a normal current detected from the sense current of the power semiconductor device.

Abstract: A voltage divider circuit assembly includes resistors, an external electrostatic shield, and internal electrostatic shield(s). The resistors are in series with each other between input terminals that receive an input voltage. An external resistor is disposed between sensing terminals that conduct an output voltage that is the input voltage divided by the resistors in the series. The external shield is conductively coupled with the series of the resistors with the external resistor disposed outside of the external shield and the other resistor(s) inside the external shield. The internal shield(s) are conductively coupled with the resistors and disposed inside the external shield. A first internal resistor is disposed inside the external shield and outside of the internal shield(s). One or more remaining resistors are inside the internal shield(s). The shields divide parasitic capacitances to enable the measurement of dynamically changing high voltage input signals.

Abstract: The invention relates to a circuit arrangement having a switching device (1) which is designed to provide a first voltage (UE) and a first electrical current (IE) in a power path and to provide a second voltage (US) and a second electrical current (IS) in a measuring path for the duration of a switching period, wherein the first electrical current corresponds to the second electrical current; having a current measuring apparatus (2) which is arranged in the measuring path and is designed to provide an output signal (UM) which corresponds to the first electrical current; and having a control circuit (3, 4) which is designed to activate the current measuring apparatus for the duration of a measuring period and to deactivate the current measuring apparatus again after the measuring period expires.

Abstract: The invention relates to the evaluation of a variable of an electric current in a power path by evaluating another electric current in a measuring path. To avoid excessively large electric currents in the measuring path, the current in said path is limited to a predetermined maximum limit value.

Abstract: A diode structure includes a rectangular first doping region, and a second doping region surrounds the first doping region wherein the first doping region and the second doping region are separated by a first isolation structure. A third doping region surrounds the second doping region wherein the second doping region and the third doping region are separated by a second isolation structure. The first isolation structure, the second doping region, the second isolation structure and the third doping region are arranged in a quadruple concentric rectangular ring surrounding the first doping region.

Abstract: A serial data transfer apparatus includes a decoder, a counter, and a calculation circuit. The decoder is configured to decode serial data to obtain written data, a base address, and transfer type information for specifying a storage unit for storing the written data. The counter is configured to count a frame synchronization pulse. The calculation circuit is configured to generate a chip select signal based on the transfer type information and the base address, as decoded by the decoder, and a count value of the frame synchronization pulse output by the counter.

Abstract: A method of making a temperature-compensated resonator is presented. The method comprises the steps of: (a) providing a substrate including a device layer; (b) replacing material from the device layer with material having an opposite temperature coefficient of elasticity (TCE) along a pre-determined region of high strain energy density for the resonator; (c) depositing a capping layer over the replacement material; and (d) etch-releasing the resonator from the substrate. The resonator may be a part of a micro electromechanical system (MEMS).

Abstract: A switched equalizer for equalizing the frequency response of a channel with high-frequency attenuation. In one embodiment the differential input of the equalizer is fed to a switch that interchanges the complementary signals at the differential input, changing the sign of the received signal, at each transition of a clock at the Nyquist frequency. The switched signal is filtered by a low-pass filter with positive feedback enhancement at DC gain and digitized by a sense amplifier, and the digital output of the sense amplifier is inverted during every half-cycle of clock at the Nyquist frequency, restoring the sign of the input signal.

Abstract: A scan driver includes a plurality of stages arranged sequentially and configured to respectively output a scan signal; and a switching unit configured to receive a plurality of clock signals, to select clock signals of the plurality of clock signals according to a selection control signal, and to input the selected clock signals to the plurality of stages.

Abstract: In some converter architectures, unary digital-to-analog (DAC) converter elements generate an analog output which represents the digital input signal. Thermometer codes trigger an appropriate number of DAC elements to generate the analog output. The DAC elements are not all perfectly weighted, and mismatch shaping is often used to dynamically equalize the usage of each DAC element during data conversion to average out the mismatches. Unfortunately, mismatch shaping adds additional switching and can worsen the effect of switching errors. Switching errors which are non-linearly dependent on the input causes a second order distortion if the sum of the switching errors corresponding to a set of DAC elements is not zero. Prior to data conversion, calibration can select a subset of DAC elements having a lesser sum of switching errors for data conversion. Other (redundant) DAC elements are not used at all or shut off permanently.

Abstract: A first P-channel transistor to a gate of which a first input signal is inputted and a second P-channel transistor to a gate of which a selection signal is inputted are provided in series between a power supply line and an output node. A first N-channel transistor to a gate of which a second input signal is inputted and a second N-channel transistor to a gate of which the selection signal is inputted are provided in series between a ground line and the output node. A third P-channel transistor to a gate of which the second input signal is inputted is provided between the gate of the second P-channel transistor and the output node, and a third N-channel transistor to a gate of which the first input signal is inputted is provided between the gate of the second N-channel transistor and the output node.

Abstract: The present invention is directed to data communication systems and methods. In various embodiments, the present invention provides a CML device that changes output frequency response by varying resistance values of its load resistance and source resistance. A bias control voltage is used to adjust the tail current of the CML device, and the tail current adjusts the output gain of the CML device. There are other embodiments as well.

Abstract: A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off.

Abstract: Reducing signal dependence for a reference voltage of a CDAC includes: splitting a decoupling capacitor into a plurality of capacitors smaller in size than a size of the decoupling capacitor; isolating at least one of the plurality of capacitors from a sampling buffer coupled to the reference voltage during a conversion phase; and supplying an appropriate amount of charge needed to replenish charge drawn by capacitors in the CDAC at each conversion step using a charge pump to pump in a dummy charge to the CDAC so that resulting configurations of the CDAC draw substantially similar amount of charge for each code change of the each conversion step.

Abstract: A compensation capacitor can be added to an amplifier for stability. Disclosed are systems and methods for improving the power supply rejection ratio (PSRR) performance of an amplifier in the presence of one or more compensation capacitors.

Abstract: An amplifier circuit has a plurality of amplifiers configured to be connected in series, and each of the plurality of amplifiers has an amplifying element configured to non-inverting amplify a signal and a phase adjustment element configured to be connected to an output terminal of the amplifying element and to adjust a phase of the signal, wherein the amplifying element is subjected to negative feedback, and wherein a stability coefficient of a circuit in which the amplifying elements of the number the same as the number of the plurality of amplifiers are connected in series is less than 1.

Abstract: An electronic circuit apparatus for compensating for a process variation of a resistor in an electronic circuit is provided. The electronic circuit includes a detecting part for generating a tune voltage corresponding to a process variation value of the at least one resistor, and a compensating part for compensating for a process variation of the at least one resistor using the tune voltage.

Abstract: The present invention is directed to data communication systems and methods. In various embodiments, the present invention provides a CML device that changes output frequency response by varying resistance values of its load resistance and source resistance. A bias control voltage is used to adjust the tail current of the CML device, and the tail current adjusts the output gain of the CML device. There are other embodiments as well.

Abstract: A differential signal is amplified by passive amplification which does not a reference of a common-mode voltage. At this time, the voltage of the differential signal is passive-amplified twice before carrying out a successive approximation type analog-digital conversion operation. The passive amplification is attained by providing a plurality of capacitances which carry out a sampling operation, and switching these connection relation by using switches. Without being accompanied by the increase of the consumed power and the chip size, an influence by the noise of s comparator is reduced to a half so that the effective resolution can be increased for one bit.

Abstract: According to one embodiment, there is provided a semiconductor device including a first amplifier and a second amplifier. The first amplifier has an input terminal to receive a first signal and an output terminal to output a second signal. The second amplifier is configured to receive the first signal and a correction data, to generate a correction signal according to the first signal and the correction data, and to output the generated correction signal to the output terminal of the first amplifier so as to add the first signal and the generated correction signal.

Abstract: In one embodiment, a temperature compensating attenuator is disclosed having an attenuation circuit and a control circuit. The temperature compensating attenuator circuit may include a first series connected attenuation circuit segment and a shunt connected attenuation circuit segment, as well as additional attenuation circuit segments. Each attenuation circuit segment includes a stack of transistors that are coupled to provide the attenuation circuit segment with an impedance attenuation level having a continuous impedance range. The control circuit may be operably associated with the stack of transistors in each attenuation circuit segment to control the attenuation level of the attenuation circuit. The temperature compensating attenuator includes a temperature compensating circuit that compensates for variations in operation of the attenuation circuit due to a temperature change.

Abstract: A semiconductor device includes a reference current generator suitable for generating a reference current, a current-voltage converter suitable for generating a first reference voltage and a second reference voltage in response to the reference current, and an analog-digital converter suitable for generating a digital code value based on a voltage difference between the first and second reference voltages, wherein the reference current generator includes a current control unit for controlling the reference current in response to the digital code value.

Abstract: Low power low noise input bias current compensation for an amplifier input stage is provided by recycling the tail current of the differential pair transistors. A local amplifier regulates the tail current and buffers the base current of the tail current transistor, which is mirrored back to the input transistors to provide input bias current compensation.

Abstract: Disclosed is a noise current compensation circuit. The circuit is provided with two input and output terminals A and B, and two control terminals CON and CONF. The control terminals control a work mode (work state and pre-charge state) of the compensation circuit. The compensation circuit consists of 7 PMOS transistors and 8 NMOS transistors. In the normal work state, by detecting changes of potential change rate of two signal lines in an original circuit, the noise current compensation circuit automatically enables one end of the original circuit that discharges slowly to discharge a signal more slowly, and enables one end of the original circuit that discharges rapidly to discharge a signal more rapidly, thus eliminating the influence of the noise current on the circuit and providing assistance for correct identification of subsequent circuit signals.

Abstract: A switched capacitor circuit with switching loss compensation mechanism includes a resonant unit and a loss compensation unit. The resonant unit generates a resonant frequency and includes a capacitor switching unit for switching an output capacitor. The loss compensation unit is coupled to the resonant unit for providing loss compensation when the capacitor switching unit outputs different capacitance values.

Abstract: A measure initialization path for a delay line structure includes: a forward path, comprising a plurality of delay stages coupled in series; a first output path coupled to at least an output of a delay stage of the forward path, where at least an output of a delay stage is fed forward to the forward path; and a second output path coupled to at least an output of a delay stage of the forward path, where at least an output of a delay stage is fed forward to the forward path. When a signal is propagated through the measure initialization path, the signal successively propagates through a delay stage of the forward path, a delay stage of the first output path and a delay stage of the second output path for performing measure initialization.

Abstract: A system and a method of generating an external parameter value for a separately excited motor controller are disclosed, the system including: a digital signal processor to convert a received analog electrical signal into a digital signal and to scale the digital signal, so as to generate a parameter value in conformity with a data format of the system; an external parameter generating module to adjust the parameter value with a calibration coefficient to obtain the external parameter value; the calibration coefficient being generated by a calibration coefficient generating module and being pre-stored in a calibration coefficient storing module; and a calibration coefficient generating module to read the parameter value generated by the digital signal processor and obtain an actual measuring value as a reference parameter value, to calculate a difference value between the parameter value from the digital signal processor and the reference parameter value, and to generate the calibration coefficient from a rat

Abstract: An implementation relates to compensating DC offset in a signal path. The signal path may have a plurality of stages, where for each stage a fine DC compensation is performed by introducing a fine DC compensation signal into the signal path of the stage by way of a compensation analog to digital converter.

Abstract: Signal processing within an integrated circuit (IC) may be monitored by a silicon process monitor, where one or more inputs to the IC may be controlled. The controlled input may comprise a variable frequency signal, a variable voltage level, an analog signal and/or a known input with a corresponding expected output. The controlled input may drive a plurality of components on the IC. The IC output signal variations may be due to temperature and/or silicon manufacturing processes variations and may affect performance and/or power consumption. IC output signal variations may be detected based on the controlled inputs. Controlled inputs may be adjusted based on the detected output variations and may be adjusted to modify the output. The variations may be detected based on relative frequency between output and the controlled input. In addition, logical operations and/or counters may be utilized to detect variations.

Abstract: A device includes a sense circuit configured to detect a leakage current from a driver output pad. A current mirror responds to the sense circuit and compensates for the leakage current detected at the driver output pad. A scaled compensation circuit can supply compensation current to the current mirror.

Abstract: In one embodiment, a bandgap reference circuit is designed with three trimmable elements to generate a temperature-independent bandgap reference voltage VBG: a VBG adjustment resistance ?R1, a VBG slope adjustment resistance ?R2, and a curvature compensation adjustment voltage VCU. Instances of the bandgap reference circuit can be trimmed in two phases: a characterization phase during which a triple-trim process determines design-specific trim values for the VBG slope adjustment resistance ?R2 and the curvature compensation adjustment voltage VCU and a production phase during which a single-trim process determines instance-specific values for the VBG adjustment resistance ?R1. Since the characterization phase can be applied to a relatively small number of instances of the bandgap reference circuit, the two-phase trimming technique is suitable for efficient mass production and high production yield.

Abstract: Capacitive level-shifting circuits and methods are provided for adding DC offsets to the output of a current-integrating amplifier. For example, a current-integrating amplifier includes an input amplifier stage and an output offset circuit. The input amplifier stage includes an input node, a first output node, and a first switch connected between the first output node and a power supply node. The output offset circuit is connected to the first output node of the input amplifier stage and to a second output node of the current-integrating amplifier. The output offset circuit includes a first series capacitor coupled between the first output node of the input amplifier stage and the second output node of the current-integrating amplifier. The output offset circuit switchably connects a bias voltage to the second output node and charges the first series capacitor to add a DC offset to the second output node of the current-integrating amplifier.

Abstract: A non-linear correction current ICTAT2 (current complementary to the square of absolute temperature) is generated from a current IPTAT (current proportional to absolute temperature) and a current ICTAT (current complementary to absolute temperature), both modified in a circuit having a topology and components which capitalize on the logarithmic relationship between transistor collector current and base-emitter voltage. The resulting ICTAT2 current (current complementary to the square of absolute temperature) is injected into a node of a bandgap reference circuit to compensate for non-linear temperature effects on output voltage. A more general correction circuit generates both IPTAT2 and ICTAT2, and applies each to a respective multiplier which, in a preferred embodiment, is a current DAC configured as a multiplier.

Abstract: A DC-offset correction circuit for a target circuit with an output terminal and a feedback input terminal. The DC-offset correction circuit includes an obtaining module and a correction module. The obtaining module obtains a DC-offset voltage from the output terminal. The correction module includes a first charging switch, a first inductor connected to the first charging switch in order from the output terminal to the feedback input terminal, and a first charging capacitor connected between ground and the node of the feedback input terminal and the first charging switch. When the voltage of the feedback input terminal is less then the DC-offset voltage, the correction module closes the first charging switch. When the voltage of the feedback input terminal is equal to the DC-offset voltage, the correction module opens the first charging switch.

Abstract: A high-linearity testing stimulus signal generator comprises a signal collection unit receiving an input current signal, a waveform conversion unit connecting with the signal collection unit, a first voltage-to-current conversion unit connecting with the waveform conversion unit, a delay unit connecting with the waveform conversion unit, a second voltage-to-current conversion unit connecting with the delay unit, a current comparison unit connecting respectively with the first voltage-to-current conversion unit and the second voltage-to-current conversion unit, an error calculation unit connecting with the current comparison unit, and a compensation unit connecting with the error calculation unit. The above-mentioned structure forms a feedback mechanism to perform compensation adjustment to promote the linearity of the output signals. Thus, the present invention can generate high-accuracy testing stimulus signals.

Abstract: A charge domain filter (CDF) apparatus having a bandwidth compensation circuit is provided. The bandwidth compensation circuit includes a configurable power-reference cell (CPC) and/or a programmable-delay cell (PDC). The CPC receives and adjusts an output of the CDF to obtain a sensing power, and outputs the sensing power to the CDF. The PDC receives and delay an output of the CDF, and outputs a delay result to the CDF. The bandwidth compensation circuit having a flexible structure, so as to implement X-axis (frequency) compensation and/or Y-axis (power or gain) compensation of a frequency response diagram according to a design requirement.