Abstract: A semiconductor device includes an analog voltage regulator and an integrated circuit module. The analog voltage regulator generates a regulated output voltage. The integrated circuit module generates an analog sense voltage based on the regulated output voltage and includes integrated circuit dies, a first sensor, second sensors, and a digital voltage offset controller (DVOC). The first sensor generates a digital reference voltage based on an analog reference voltage. The second voltage sensors detect voltages at predetermined locations on the integrated circuit dies. The DVOC generates a digital offset voltage substantially equal to the difference between the digital reference voltage and the voltage detected by a selected one of the second voltage sensors. The regulated output voltage is based on an unregulated input voltage, the analog sense voltage, and the digital offset voltage.

Abstract: Methods, systems, and devices for voltage detection for managed memory systems are described. In some cases, a memory system may include circuitry to monitor one or more supply voltages to the memory system or voltages generated by the memory system to determine whether a voltage rises above an operational range. In some cases, an overvoltage detector may include an undervoltage detector that has been tuned or manufactured to have a higher threshold than an undervoltage detector used to determine whether a voltage has fallen below the operational range. Accordingly, the memory system may monitor a voltage using an undervoltage detector having a threshold corresponding to a lower bound or lower operation point of the operational range of the monitored voltage and an overvoltage detectors having a threshold corresponding to the upper bound or upper operational point of the operational range.

Abstract: Some embodiments provide a DC power distribution system that includes a plurality of DC sources coupled to a plurality of DC buses via respective protection devices that are configured to selectively cause an open-circuit between the DC source and the respective DC bus in the event of a fault or overload condition on the respective DC bus. The plurality of DC buses are coupled to a load combiner, and the system is configured to supply power in parallel from the DC sources via the plurality of DC buses to at least one DC/DC step-down converter via the load combiner, which combines the power supplied via the plurality of DC buses. The DC buses, load combiner, and the DC power sources are configured such that the total maximum load current is capable of being supplied via less than all of the plurality of DC buses in the event that any one of the DC buses is non-operational.

Abstract: A circuit for preventing false turn-on of a semiconductor switching device includes an active clamp circuit, a control circuit, a power amplifier circuit, and a suppression circuit. The control circuit is coupled to an input of the power amplifier circuit. An output of the power amplifier circuit is coupled to a gate of the semiconductor switching device. The active clamp circuit is configured to operate within a preset period when a voltage between the first end of the semiconductor switching device and a second end of the semiconductor switching device is greater than a preset voltage. The suppression circuit includes a controllable switch, which is configured to turn on after the operation of the active clamp circuit is completed, such that potential at the input of the power amplifier circuit is clamped to a fixed potential.

Abstract: Embodiments of input supply circuits and methods for operating an input supply circuit are described. In one embodiment, an input supply circuit includes a bias circuit configured to define a voltage threshold in response to an input signal, and an input buffer configured to generate an output signal in response to the voltage threshold. Other embodiments are also described.

Abstract: Described is an invention that adds capacitive sensing ability with a single magnetic field sensor location or distributed within an array of surfaces of the sensor. The capacitive sensing can be achieved by modifying a classic Hall effect sensor or putting separate capacitive sensor plates in close proximity to the hall effect sensor.

Abstract: The present disclosure is generally directed to a method for driving an ultrasonic transducer. The method includes coupling a driving electrode and a ground electrode of the ultrasonic transducer to a power supply and a ground, respectively, during a first time period based on a received drive signal. The method further includes decoupling the driving electrode and the ground electrode of the ultrasonic transducer from the power supply and the ground, respectively, to float the driving electrode and the ground electrode of the ultrasonic transducer during a second time period based on the received drive signal to store a charge between the driving electrode to the ground electrode.

Abstract: Disclosed herein is a MEMS ASIC. In some examples, the MEMS ASIC can include a MEMS, an analog front end (AFE) amplifier, an analog-to-digital converter (ADC), an overload detector, and a high-ohmic (HO) block. The HO block and the MEMS can form a high-pass filter (HPF). The impedance of the HO block can be related to the DC operating level of the AFE amplifier and the cutoff frequency of the HPF. In some examples, an overload event can occur, and the overload detector can be configured to adjust the impedance of the HO block to reduce the settling time of the MEMS ASIC. Methods of using the MEMS ASIC to reduce the settling time of the MEMS ASIC due to an overload event are disclosed herein.

Abstract: A memory package includes; a first memory chip including first memory pads, and a buffer chip including first buffer pads respectively connected with the first memory pads and second buffer pads connected with an external device. The buffer chip respectively communicates signals received via the second buffer pads to the first buffer pads in response to a swap enable signal having a disabled state, and the buffer chip swaps signals received via the second buffer pads to generate first swapped signals, and respectively communicates the first swapped signals to the first buffer pads in response to the swap enable signal having an enabled state.

Abstract: The present disclosure describes a power supply switch that includes a voltage generator, a switch circuit, and a confirmation circuit. The voltage generator is configured to compare a first power supply voltage to a second power supply voltage and to output the first power supply voltage or the second power supply voltage as a bulk voltage (Vbulk). The switch circuit includes one or more transistors and is configured to (i) bias bulk terminals of the one or more transistors with the Vbulk and (ii) output either the first power supply voltage or the second power supply voltage as a voltage output signal. The confirmation circuit is configured to output a confirmation signal that indicates whether the voltage output signal transitioned from the first power supply voltage to the second power supply voltage.

Abstract: Methods, systems, and devices for power-efficient generation of voltage are described. A driver circuit in a memory device may produce a voltage on an output node for other components in the memory device to use. To produce the voltage, the driver circuit may use a first voltage supply to charge the output node to a first threshold voltage level. The driver may then use a second voltage source to charge the output node to a second threshold voltage level that is different than (e.g., higher than) the first threshold voltage level.

Abstract: A method for selecting a power source for a load is provided. The method includes monitoring the primary power source, when the primary power source is providing power to the load, determining if a condition of the primary power source crosses a first threshold, when the condition crosses the first threshold, turning on a first power field effect transistor to couple a back-up power source to the load through a second power field effect transistor, when the primary power source is not providing power to the load, determining if a condition of the primary power source crosses a second threshold, and when the condition crosses the second threshold, switching off the first power field effect transistor to couple the primary power source to the load through a third power field effect transistor.

Abstract: The present invention of the embodiment provides a drive circuit, comprising a first group of drive circuits and a second group of drive circuits each having multiple stages of gate drive circuits connected in series, each stage of the gate drive circuits comprising a shift register outputting a first gate drive signal and a touch voltage stabilizing unit coupled to the shift register, the touch voltage stabilizing unit comprising a reference end electrically connected to a reference potential of the shift register, a first voltage stabilizing end electrically connected to the first gate drive signal, a second voltage stabilizing end outputting a second gate drive signal and a signal end electrically connected to a control signal, wherein the control signal disables the touch voltage stabilizing unit during a display period, and the control signal enables the touch voltage stabilizing unit during a touch period.

Abstract: A communication unit (300) is described that includes a plurality of cascaded devices that includes at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device comprises a modulator circuit (362) configured to: receive a system clock signal and a frame start signal; modulate the system clock signal with the frame start signal to produce a modulated master-slave clock signal (384); and transmit the modulated master-slave clock signal (384) to the at least one slave device. The at least one slave device comprises a demodulator circuit (364) configured to: receive and demodulate the modulated master-slave clock signal (384); and re-create therefrom the system clock signal (388, 385) and the frame start signal (390, 386).

Abstract: A method of signal detection includes receiving an input voltage signal; using AC (alternate current) coupling to couple the input voltage signal into a coupled voltage signal; establishing a DC (direct current) value of the coupled voltage signal using a resistor; generating a self-mixed voltage signal by performing a self-mixing of the coupled voltage signal using a pair of cross-coupling MOS (metal oxide semiconductor) transistors; generating an output voltage by applying low-pass filtering on the self-mixed voltage signal; generating a reference voltage using a reference current terminated with a reference load; and determining a logical signal by comparing the output voltage with the reference voltage.

Abstract: Disclosed herein is a MEMS ASIC. In some examples, the MEMS ASIC can include a MEMS, an analog front end (AFE) amplifier, an analog-to-digital converter (ADC), an overload detector, and a high-ohmic (HO) block. The HO block and the MEMS can form a high-pass filter (HPF). The impedance of the HO block can be related to the DC operating level of the AFE amplifier and the cutoff frequency of the HPF. In some examples, an overload event can occur, and the overload detector can be configured to adjust the impedance of the HO block to reduce the settling time of the MEMS ASIC. Methods of using the MEMS ASIC to reduce the settling time of the MEMS ASIC due to an overload event are disclosed herein.

Abstract: A method and apparatus capable of adjusting a signal level in a wireless communication system are provided. An electronic device includes an oscillator configured to output a local oscillator (LO) signal, a mixer configured to convert a frequency band of a first signal based on the LO signal and output a third signal, and a feedback circuit configured to output a feedback signal for adjusting a magnitude of the LO signal, wherein the mixer is further configured to adjust a magnitude of LO signal based on the feedback signal.

Abstract: To provide an ignition control device of an internal combustion engine capable of reducing the number of adjustment steps required for adjustment such as matching of a MOS gate voltage or the like without being affected by device variation. A detection voltage is generated on the basis of a primary current flowing through a current detection resistor having a positive temperature dependent characteristic. A reference voltage is generated by a potential difference between a base and an emitter of a first bipolar transistor circuit and a multiple type second bipolar transistor circuit in which a plurality of bipolar transistors are connected in parallel, and a resistance value of a first resistor connected to the emitter side of the plurality of the bipolar transistor circuit, on the basis of a current having a positive temperature dependent characteristic similar to the current detection resistor.

Abstract: A method is provided for initializing an electronic circuit in dependence on an externally applied voltage. The electronic circuit contains a first input circuit and further circuit elements. In a first step, a first enable signal for the operation of the input circuit and a further enable signal for the operation of the further circuit elements are deactivated if the voltage falls below a first threshold. In a second step, the first enable signal for the operation of an input circuit is activated and the further enable signal for the operation of the further circuit elements is deactivated if the voltage exceeds the first threshold. This is followed by the reception, with the first input circuit, of a chip select signal for the activation of the electronic circuit and of a code word at a terminal for the command bus. The activation of the further enable signal for the operation of the further circuit elements takes place if the received chip select signal and the received code word have predetermined values.

Abstract: The switch circuit includes a MOS transistor one end of which is coupled to a power supply line and to a control terminal of which voltage is input, a switch coupled between the power supply line and one end of the MOS transistor or one end of which is coupled to the other end of the MOS transistor, a MOS transistor coupled between an output terminal and ground potential, and a series-connected switch and constant current source coupled to a connection point between an opposite-side end of the whole series-connected MOS transistor and switch to the power supply line and the control terminal of the MOS transistor and performing adjustment to prevent current from flowing from the MOS transistor to ground potential after the switch turns on until the MOS transistor turns on.

Abstract: Various techniques are provided for implementing a segmented focal plane array (FPA) of infrared sensors. In one example, a system includes a segmented FPA. The segmented FPA includes a top die having an array of infrared sensors (e.g., bolometers). The top die may also include a portion of a read-out integrated circuit (ROIC). The segmented FPA also includes a bottom die having at least a portion of the ROIC. The top and the bottom dies are electrically coupled via inter-die connections. Advantageously, the segmented FPA may be fabricated with a higher yield and a smaller footprint compared with conventional FPA architectures. Moreover, the segmented FPA may be fabricated using different semiconductor processes for each die.

Abstract: A semiconductor storage device comprises a plurality of memory cells arranged in a matrix. Each of the memory cells includes: a semiconductor storage element including a silicon carbide substrate and a silicon carbide film on a first surface of the silicon carbide substrate; a lower electrode on a second surface facing away from the first surface of the silicon carbide substrate; and an upper electrode on at least part of a surface of the silicon carbide film, the surface facing away from another surface of the silicon carbide film in contact with the silicon carbide substrate. Each memory cell includes at least one basal plane dislocation formed at at least part of the semiconductor storage element.

Abstract: An operating method of an electronic device including a semiconductor memory, the operating method includes selecting one of a plurality of memory cells during a set operation, applying a write current having a slow quenching pattern to the selected memory cell, monitoring a cell current flowing through the selected memory cell, generating a discharge control signal corresponding to a result of the monitoring, and discharging the write current in response to the discharge control signal.

Abstract: Disclosed herein is an apparatus that includes a first external terminal supplied with a first power potential, a second external terminal supplied with a second power potential different from the first power potential, a first transistor connected between the first external terminal and an internal power line, a second transistor connected between the second external terminal and the internal power line, and a first circuit configured to bring the first transistor OFF during at least a first period until the second power potential is supplied after the first power potential is supplied.

Abstract: The disclosure relates to solid state relay circuit for switching an electrical load. The solid state relay circuit may include a relay transistor; and a driver circuit comprising a constant current source. The driver circuit is configured and arranged to switchably operate the relay transistor, and the relay transistor is configured and arranged to switchably operate the electrical load.

Abstract: Apparatuses and methods for mixed charge pumps with voltage regulator circuits is disclosed. An example apparatus comprises a first charge pump circuit configured to provide a first voltage, a second charge pump circuit configured to provide a second voltage, a plurality of coupling circuits configured to voltage couple and current couple the first voltage and the second voltage to a common node to provide a regulated voltage, and a feedback circuit configured to regulate the first voltage and the second voltage based on the regulated voltage.

Abstract: A method for switching a power supply for low current standby operation includes deactivating a first supply connected to a first supply node, in response to activating an enable signal. A second supply is changed to a low power mode in response to activating the enable signal, wherein the second supply is connected to a second supply node. The first supply node is connected to the second supply node in response to a first voltage of the first supply node being less than or equal to a positive offset above a second voltage of the second supply node. The first supply node is disconnected from the second supply node in response to deactivating the enable signal, wherein the first supply node is disconnected at a rate preventing the first supply node from discharging below a first supply minimum voltage.

Abstract: Methods, systems, and devices for a current monitor for a memory device are described. A memory device may monitor potential degradation of memory cells on the device by monitoring the amount of current drawn by one or more memory cells. As the memory cells degrade, the current supplied to the memory cells may change (e.g., increase due to additional leakage current. The memory device may indirectly monitor changes in the current supplied to the memory cells by monitoring a voltage of a node of a transistor that controls the amount of current supplied to the array of memory cells. The voltage at the control node may be compared to a reference voltage to determine whether the two voltages differ by a threshold amount, indicating that the memory cells are drawing more current. The memory device may output a status indicator when the voltages differ, for example, by the threshold amount.

Abstract: A computer system may include circuit blocks that may operate in different operating modes. When operating in a retention mode, a voltage level of a local power supply node for a particular circuit block may be less than a voltage level of the local power supply node when the particular circuit block is operating in an active mode. An output buffer circuit may be configured to generate, when the particular circuit block is operating in retention mode, an output signal using a circuit signal generated by the particular circuit block, and a voltage level corresponding to the active mode of operation.

Abstract: A charge pump circuit has load driven clock frequency management. The charge pump circuit includes a CCO generating a CCO output signal that has a frequency generally proportional to a feedback current, and a charge pump operated by the CCO output signal and boosting a supply voltage to produce a charge pump output voltage at an output coupled to a load. A current sensing circuit senses a load current drawn by the load and generates the feedback current as having a magnitude that varies as a function of the sensed load current if a magnitude of the load current is between a lower load current threshold and an upper load current threshold. The magnitude of the feedback current does not vary with the sensed load current if the magnitude of the sensed load current is not between the lower load current threshold and the upper load current threshold.

Abstract: A battery reverse polarity protection circuit is disclosed. The battery reverse polarity protection circuit includes a field effect transistor (FET) coupled to a control circuit. The FET is configured to transmit an input voltage from a normal-polarity-connected battery to an output terminal, and block the input voltage from a reverses polarity-connected battery to the output terminal. The control circuit is coupled to the input terminal, the output terminal, and a common terminal and is configured to detect, during transmission of the input voltage from the normal-polarity-connected battery to the output terminal, that the input voltage is less than an output voltage, indicating onset of an abnormal operating mode, and turn off the FET to prevent the output voltage from being affected by the input voltage during the abnormal operating mode.

Abstract: A level shifting circuit includes a level shifting portion configured to receive an input signal and generate an output signal, and a current adjustment circuit connected between the level shifting portion and a drive high voltage node at which a drive high voltage is applied. The current adjustment circuit is configured to adjust an amount of current provided from the drive high voltage node to the level shifting portion.

Abstract: An example device in accordance with an aspect of the present disclosure includes a first module, a second module, and a third module. The first module is coupled to an element whose status is to be determined, and the first module is to receive an input current that increases over time. The second module is to perform a temporal derivative of a voltage across the element. The third module is to provide an output signal based on a current behavior of the element, according to a change in voltage as a function of a change in current.

Abstract: A semiconductor device includes a die pad, and a first lead integrally connected to the die pad. A second lead and a third lead are arranged laterally away from the first lead. A semiconductor element including a first lateral surface and a second lateral surface adjacent to each other and a third lateral surface located opposite to the first lateral surface and adjacent to the second lateral surface, is mounted on the die pad. A plurality of first conductive members electrically connects the at least part of a main electrode pad to the end on the die pad side of the second lead. A second conductive member connects a control electrode pad to the end on the die pad side of the third lead.

Abstract: A negative charge pump without the need for a negative supply potential. The negative charge pump can be manufactured utilizing standard CMOS processes. The charge pump includes a first inverter, a second inverter, a charge storage and a coupling element.

Abstract: Voltage regulators for battery operated systems are provided. In certain implementations, a voltage regulator is operable in a regulating mode and a bypass mode. In the regulating mode, an input voltage greater than a selected value can be regulated so as to yield a desired output voltage. In the bypass mode, an input voltage at or less than the selected value can be regulated so as to yield an output voltage that substantially tracks the input voltage. Such a capability of switching between two modes can provide advantageous features such as reducing the likelihood of damage in a powered circuit due to high input voltage, and extending the operating duration of a power source such as a rechargeable battery. Also disclosed are examples of how the foregoing features can be implemented in different products and methods of operation and fabrication.

Abstract: An apparatus is provided which comprises: a first power supply rail to provide a first power supply voltage; a second power supply rail to provide a second power supply voltage, wherein the first power supply voltage is higher than the second power supply voltage; a first circuitry coupled to the first and second supply rails, wherein the first circuitry is to operate using the first supply voltage, and wherein the first circuitry is to inject charge on to the second power supply rail in response to a droop indication; and a second circuitry to detect voltage droop on the second power supply rail, wherein the second circuitry is to generate the droop indication for the first circuitry.

Abstract: A driver circuit includes two pull-up portions coupled respectively between VDD and first and second driver output nodes and two pull-down sections coupled respectively between ground and third and fourth driver output nodes. The driver circuit is configurable as an RS485 driver or a CAN driver. The active diodes in the pull-up sections are turned off when necessary to prevent unwanted reverse currents between the first and second output nodes and VDD. The active diodes in the pull-down sections are turned off when necessary to prevent unwanted reverse current between ground and the third and fourth output nodes.

Abstract: A power supply switching circuit that selects one power supply potential from among a plurality of power supply potentials. This power supply switching circuit is provided with a transistor QP1 that is connected between an input node N1 and node N2 and has a back gate connected to node N1, a transistor QP2 that is connected between node N2 and output node N3 and has a back gate connected to node N3, a transistor QP3 that is connected between input node N4 and node N5 and has a back gate connected to node N4, a transistor QP4 that is connected between the node N5 and N3 and has a back gate connected to node N3, and a control signal generation unit that sets a group of transistors QP1 and QP2 and a group of transistors QP3 and QP4 to a conduction state and sets the other to a non-conduction state.

Abstract: Provided is a condenser microphone circuit that can support variation in power supply voltage of a phantom power supply using a wiring system of two lines. A condenser microphone circuit includes a microphone unit, an FET, a constant current diode, a collector grounding first transistor that generates an operation power supply of the FET, a first resistor that sets base potential of the first transistor, a collector grounding second transistor that amplifies an output signal from the FET, a second resistor that sets base potential of the second transistor, and an output circuit. A base of the first transistor is connected to a source of the FET, an emitter of the first transistor is connected to a drain of the FET, a base of the second transistor is connected to the drain of the FET, an emitter of the second transistor is connected to the output circuit, and the second resistor divides voltage on a cathode side of the constant current diode.

Abstract: Apparatuses and methods for duty cycle distortion correction of clocks are disclosed. An example apparatus includes a clock circuit configured to receive complementary input clocks and a control signal and to provide multiphase clocks responsive to complementary input clocks. The clock circuit is further configured to be in a first mode or second mode controlled by the control signal and configured to provide the multiphase clocks having greater duty cycle distortion in a first mode than in a second mode.

Abstract: To provide a receiver, a communication device, and a communication method capable of restoring a signal transmitted via a non-contact transmission channel with high accuracy. A communication device has a transmission circuit that converts an input signal into a pulse, a non-contact transmission channel that has a primary side coil and a secondary side coil and transmits the pulse from the transmission circuit in a non-contact manner, a restoration circuit that restores the input signal on the basis of a reception signal corresponding to the pulse transmitted via the non-contact transmission channel, an initialization unit that initializes an output of the non-contact transmission channel, and an initialization control unit that outputs a control signal of controlling the initialization unit on the basis of the reception signal corresponding to the pulse received via the non-contact transmission channel.

Abstract: An integrated circuit includes a first stage configured to receive a bias current. A current regulation loop includes a transimpedance amplifier having a first transistor, and a second transistor having a gate coupled to a gate of the first transistor. The first transistor and the second transistor are configured to compare the bias current with a reference current, and to generate a regulation voltage on an output node of the transimpedance amplifier. A capacitor is coupled between the output node of the transimpedance amplifier and the gates of the first and second transistors.

Abstract: A semiconductor structure includes first and second source/drain region disposed in a semiconductor body and spaced from each other by a channel region. A gate electrode overlies the channel region and a capacitor electrode is disposed between the gate electrode and the channel region. A first gate dielectric is disposed between the gate electrode and the capacitor electrode and a second gate dielectric disposed between the capacitor electrode and the channel region. A first electrically conductive contact region is in electrical contact with the gate electrode and a second electrically conductive contact region in electrical contact with the capacitor electrode. The first and second contact regions are electrically isolated from one another.

Abstract: A circuit having an amplifier, comprising: a depletion mode transistor having a source electrode coupled to a reference potential; a drain electrode coupled to a potential more positive than the reference potential; and a gate electrode for coupling to an input signal. The circuit includes a bias circuit, comprising: a current source; and biasing circuitry coupled to the current source and between the potential more positive than the reference potential and a potential more negative than the reference potential. A control circuit is connected to the current source for controlling the amount of current produced by the current source to the biasing circuitry.

Abstract: A bandgap reference circuit includes a voltage generation circuit, a capacitor and a clamping control circuit. The voltage generation circuit is used to generate a current on an operation terminal. The capacitor includes a first terminal coupled to the operation terminal, and a second terminal coupled to a first reference voltage terminal. The clamping control circuit is coupled between the operation terminal and a second reference voltage terminal. The clamping control circuit includes a switch and a clamping unit, and is used to allow part of the current flowing through the clamping unit to the second reference voltage terminal when the switch is turned on.

Abstract: A processor system includes first and second regulators for regulating an adjusted supply voltage. The first and second regulators generate a plurality of control signals to regulate an adjusted power supply voltage and that generate a charge when a droop level falls below a droop threshold value by implementing first and second control loops. A supply adjustment block with the two regulators and control loops are provided for each processor core allowing different cores to have different regulated supply levels all based on one common supply. One regulator is a global regulator while another is a local regulator found in each of the processing tiles. Processing tiles are grouped into two groups wherein one group includes tiles that may powered down to save power. Voltage rails of the two groups are selectively connected to equalize voltage levels when both groups are powered on and operating.

Abstract: An acoustic energy detection circuit can include a microphone interface circuit configured for coupling to a microphone. The microphone interface circuit is configured to intermittently activate the microphone to detect acoustic energy and convert the acoustic energy to an electrical signal. The acoustic energy detection circuit also includes a comparator circuit for receiving the electrical signal and comparing the electrical signal with a threshold signal. The comparator circuit is configured to output an output signal to indicate detection of acoustic energy.

Abstract: A system for interfacing an LC sensor includes a starter configured to selectively start an oscillation of the LC sensor. The system also includes an analog peak detector configured to determine a signal (Vpeak) being indicative of a peak voltage of the oscillation of the LC sensor and a detector configured to determine a state of the LC sensor as a function of the signal (Vpeak) determined by the analog peak detector.

Abstract: Methods for fabricating an integrated circuit with a voltage regulator are provided. In some implementations, a method includes forming a primary regulator on a semiconductor substrate, including fabricating a switch, fabricating an amplifier for controlling the switch, and fabricating a voltage generator for biasing the amplifier to operate the primary regulator in a bypass mode or in a regulating mode. The method further includes forming an input terminal and an output terminal of the primary regulator on the semiconductor substrate, forming a secondary regulator on the substrate, forming an input terminal and an output terminal of the secondary regulator on the semiconductor substrate, and forming an electrical connection between the output terminal of the primary regulator and the input terminal of the secondary regulator.