Abstract: A high-frequency module (20) includes a reception-side filter (21) that uses a first frequency band as a pass band and a second frequency band as an attenuation band, an LNA (23), and a matching circuit (22) disposed between the reception-side filter (21) and the LNA (23). In a Smith chart, the matching circuit (22) makes an interval between impedance in the second frequency band of the reception-side filter (21) and a second gain circle center point indicating impedance at which gain in the second frequency band of the LNA (23) is maximized greater than an interval between impedance in the first frequency band of the reception-side filter (21) and a first gain circle center point indicating impedance at which gain in the first frequency band of the LNA (23) is maximized.

Abstract: A headphone driver includes a pre-main amplifier and a main amplifier. The pre-main amplifier receives an input signal from first and second node and outputs the input signal to a third node. The main amplifier is between the third node and a fourth node. A first switch is between the fourth node and a fifth node. A second switch is between the fourth node and a sixth node. A third switch is between the fourth node and a seventh node. A fourth switch is between the fifth and seventh nodes. A fifth switch is between the first and fifth nodes. A capacitor is between the third and fifth nodes. A first feedback resistor is between the first and seventh nodes. A second feedback resistor is between the second and sixth nodes, and the sixth and seventh nodes are connected to a speaker.

Abstract: A device, system, and method of a programmable circuit configured to operate in a buffered drive mode and blanking mode is disclosed. The programmable circuit includes a continuous-time digital-to-analog converter (CTDAC), a continuous-time block (CTB), coupled to the CTDAC, and a sample and hold (SH) circuit coupled to the CTDAC and the CTB. The programmable circuit is configured to operate in a buffered drive mode to buffer an output signal from the CTDAC. The programmable circuit, in buffered drive mode, is further configured to operate in a blanking mode to cause the SH circuit to perform a blanking operation on the CTDAC output signal.

Abstract: An amplifier may include a plurality of stages, wherein each stage may have an amplifier stage output configured to generate an amplifier output signal and a transistor coupled at its gate terminal to the amplifier input and to the gate terminals of the transistors of the other amplifier stages. Each stage may be configured to periodically and cyclically operate in an amplifier mode in which the amplifier stage generates at its corresponding amplifier stage output a power-amplified version of a signal received at the amplifier input and a in reset mode in which the transistor of the stage operating in the reset mode has an electrical property thereof reset. At any given time, at least one amplifier stage is operating in the amplifier mode. The amplifier may be configured to output as an output signal one of the amplifier output signals corresponding to an amplifier stage operating in the amplifier mode.

Abstract: A technique for a reconditioning equalizer filter for non-constant envelope signals is described. The input to a transmitter chain is modified by a reconditioning equalizer filter, prior to being applied to the transmitter. The reconditioning equalizer filter modifies and smoothens the amplitude of the signal. The modified and smoothened signal has its peaks reduced which results in lower Crest Factor. The input to the reconditioning equalizer filter could be a baseband, intermediate frequency (IF) or radio frequency (RF) signal. When the signal is an IF or RF signal, it needs to be down-converted to baseband before being applied to the reconditioning equalizer filter. The reconditioning equalizer filter could be performed in a digital or analog domain.

Abstract: An amplifier includes an amplifying stage configured to provide an amplifier output signal based on a combination of a received amplifying stage input signal and a received amplified version of the amplifying stage input signal.

Abstract: A signal level conversion circuit 1 includes a first differential amplifier circuit 10 and a second differential amplifier circuit 20. The first differential amplifier circuit 10 multiplies a potential difference between a first input signal and a second input signal by G1 thereby providing an output signal. The second differential amplifier circuit 20 multiplies a potential difference between the output signal of the first differential amplifier circuit 10 and the second input signal by G2 thereby providing an output, where the two gains satisfy the relation of G1×G2<0 and 0<?(G1+1)×G2<2.

Abstract: A technique for a reconditioning equalizer filter for non-constant envelope signals is described. The input to a transmitter chain is modified by a reconditioning equalizer filter, prior to being applied to the transmitter. The reconditioning equalizer filter modifies and smoothens the amplitude of the signal. The modified and smoothened signal has its peaks reduced which results in lower Crest Factor. The input to the reconditioning equalizer filter could be a baseband, intermediate frequency (IF) or radio frequency (RF) signal. When the signal is an IF or RF signal, it needs to be down-converted to baseband before being applied to the reconditioning equalizer filter. The reconditioning equalizer filter could be performed in a digital or analog domain.

Abstract: An amplifier includes an amplifying stage configured to provide an amplifier output signal based on a combination of a received amplifying stage input signal and a received amplified version of the amplifying stage input signal.

Abstract: Techniques for optimizing a cascade gain device comprising at least two gain stages are disclosed. A first noise figure associated with the first gain stage is incrementally increased by a plurality of noise figure increments determined based, at least in part, on a minimum noise figure and a maximum noise figure associated with the first gain stage. At each of the plurality of noise figure increments, at least a gain value that corresponds to the noise figure increment is calculated. One of the plurality of noise figure increments and the corresponding gain value is selected as an optimum noise figure of the first gain stage and an optimum gain value of the first gain stage respectively. Parameters of an inter-stage matching network associated with the first gain stage are configured based on the optimum noise figure and the optimum gain of the first gain stage.

Abstract: A technique for a reconditioning equalizer filter for non-constant envelope signals is described. The input to a transmitter chain is modified by a reconditioning equalizer filter, prior to being applied to the transmitter. The reconditioning equalizer filter modifies and smoothens the amplitude of the signal. The modified and smoothened signal has its peaks reduced which results in lower Crest Factor. The input to the reconditioning equalizer filter could be a baseband, intermediate frequency (IF) or radio frequency (RF) signal. When the signal is an IF or RF signal, it needs to be down-converted to baseband before being applied to the reconditioning equalizer filter. The reconditioning equalizer filter could be performed in a digital or analog domain.

Abstract: A channelized amplification system and method for mitigating non-linear amplification effects and controlling spectral re-growth is disclosed. A channelized amplifier system includes a frequency divider, a plurality of distributors coupled to the frequency divider, and a plurality of amplification modules coupled to the plurality of distributors. Each of the plurality of amplification modules includes a plurality of channelized non-linear amplifiers, a frequency combiner having a plurality of band-pass filters and coupled to the plurality of channelized non-linear amplifiers, and a band-pass filter coupled to the frequency combiner.

Abstract: Embodiments of the present disclosure may provide a charge redistribution DAC with an on-chip reservoir capacitor to provide charges to the DAC in lieu of traditional external reference voltages. The DAC may include the on-chip reservoir capacitor having a first plate and a second plate, an array of DAC capacitors to generate a DAC output, and an array of switches controlled by a DAC input word to couple the DAC capacitors to the reservoir capacitor. The charge redistribution DAC may further comprise a first switch connecting the first plate to an external terminal for a first external reference voltage, and a second switch connecting the second plate to an external terminal for a second external reference voltage. One embodiment may provide an ADC that includes the charge redistribution DAC.

Abstract: This document discusses among other things apparatus and methods for protecting circuit elements from harmful voltages. In an example, an apparatus can include an amplifier configured to receive an input signal and to provide an estimate of a first output signal, a peak detector to receive the estimate and to generate a comparison signal that is active when the amplified input signal exceeds a threshold value, and a timer configured to activate a second output signal if the comparison signal is active for at least a selected time period. The timer can include a first digital input and the selected time period can be set using a state of the first digital input.

Abstract: An apparatus and method for amplifying a transmission signals in multiple modes and multiple bands. The apparatus includes a tunable power amplifying module adapted to receive a plurality of signal types comprising multiple modes and multiple bands. The tunable power amplifying module includes a first and second power amplifier stages and a number of tunable matching networks configured to optimize an impedance value based on the mode and band of the signal to be amplified.

Abstract: An amplifier system providing improved Cartesian feedback is provided. A complex band pass error amplifier is provided. A quadrature up converter is connected to the complex band pass error amplifier so as to receive as input, output from the complex band pass error amplifier. An amplifier is connected to the quadrature up converter so as to receive as input, output from the quadrature up converter. A quadrature down converter is connected at or beyond the amplifier output so as to receive as input a signal proportional to that delivered by the amplifier as output to a load, wherein the complex band pass error amplifier is connected to the quadrature down converter so as to receive as a first input, output from the quadrature down converter and as a second input, a quadrature reference signal.

Abstract: A multistage amplifying circuit includes a first amplifying circuit that either samples a first analog voltage input or amplifies a difference between the first analog voltage and a first digital voltage converted from the first analog voltage, in response to a control signal. A second amplifying circuit either samples a second analog voltage input or amplifies a difference between the second analog voltage and a second digital voltage converted from the second analog voltage, in response to the control signal. A common amplifier receives output voltages of the first amplifying circuit and the second amplifying circuit and either resets the output voltage of the first amplifying circuit and determines an output voltage by using the second amplifying circuit, or resets the output voltage of the second amplifying circuit and determines an output voltage by using the first amplifying circuit, in response to the control signal.

Abstract: A multistage amplifier and design method are disclosed. The multistage amplifier has a plurality of amplifier stages, each stage having an amplifier designed and biased to operate at or near the amplifier's power added efficiency (PAE) peak. The PAE peak of each of the amplifier is at or near the amplifiers linear-compression transition region, providing a multistage power amplifier that is power efficient and has desirable amplitude to amplitude and amplitude to phase power transfer characteristics. The amplifier is designed by matching the output impedance of a final stage with a load. Amplifier stages are iteratively designed from the last stage to the first. At each stage, an amplifier and drive circuit are designed. The drive circuit and amplifier are designed to provide each stage with output impedance matched to the input impedance of the following stage and to operate at or near the PAE peak of the amplifier.

Abstract: A technique for enhanced reconditioning equalizer filter for non-constant envelope signals is described. The input to a transmitter chain is modified by an enhanced reconditioning equalizer filter, prior to being applied to the transmitter. The enhanced reconditioning equalizer filter modifies and smoothens the amplitude of the signal. The modified and smoothened signal has its peaks reduced which results in lower Crest Factor. The input to the enhanced reconditioning equalizer filter could be a baseband, an intermediate frequency (IF) or radio frequency (RF) signal. When the signal is an IF or RF signal it needs to be down converted to baseband before applied to enhanced reconditioning equalizer filter. The enhanced reconditioning equalizer filter could be implemented in digital or analog domain.

Abstract: An amplifier arrangement and a method for amplifying a signal, the arrangement including a transistor to amplify an input signal and to provide an intermediate signal. The intermediate signal is amplified to form an output signal which is fed back to the transistor.

Abstract: A method of settling an amplifier and a multistage amplifier are provided. To settle an amplifier, a plurality of clock signals are, respectively, applied to preset switches, each of which is placed between amplifiers connected in cascade, to open the preset switches sequentially, thereby settling the amplifiers in order.

Abstract: Systems and methods for performance improvements in digital switching amplifiers using low-pass filtering to reduce noise and distortion. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a low-pass filter configured to filter audio signals output by the plant. The filtered output of the plant is added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.

Abstract: There is provided a cable television network (10) comprising a first amplifier (12) and a plurality of successive amplifiers (14, 14?, 14?) all connected in series electrically, with the first amplifier (12) connected to a power source (16) and power for each amplifier routed through the preceding amplifier, wherein at least some of the plurality of successive amplifiers (14, 14?, 14?) further comprise a power delay device (34, 34?, 34?) in the form of a relay such that the successive amplifiers are connected to power at different times to reduce current load on each amplifier. Each relay (34, 34?, 34?) receives electrical power from the preceding amplifier and introduces a power delay of between 100 and 1500 ms and more preferably 220-1000 ms.

Abstract: According to an exemplary embodiment, a multimode power amplifier configured to receive an RF input signal and provide an RF output signal in linear and saturated operating modes includes an output stage configured to receive a fixed supply voltage and to provide the RF output signal. The multimode power amplifier further includes at least one driver stage coupled to the output stage, where the at least one driver stage is configured to receive the RF input signal and an adjustable supply voltage. The adjustable supply voltage controls an RF output power of the RF output signal when the multimode power amplifier is in the saturated operating mode. The at least one driver and the output stage are each biased by a low impedance voltage in the linear and saturated operating modes. The adjustable supply voltage can be controlled by a fixed control voltage in the linear operating mode.

Abstract: A high frequency signal detection circuit includes an input terminal for a high frequency signal to be detected, a switch transferring the high frequency signal as intermittent ringing signal to a first node in response to a pulse signal whose frequency is lower than that of the high frequency signal, a transistor amplifying the signal at the first node, and outputting to a second node, a bias generator generating a bias voltage by which the transistor is operated in its weak inversion region, a resonant circuit outputting the bias voltage to the first node, and resonating the high frequency signal, a capacitor removing a high frequency component of the signal at the second node; and a judgment circuit judging whether or not the high frequency signal is inputted by detecting the signal at the second node, which has the same frequency as the pulse signal.

Abstract: A multistage amplifier and design method are disclosed. The multistage amplifier has a plurality of amplifier stages, each stage having an amplifier designed and biased to operate at or near the amplifier's power added efficiency (PAE) peak. The PAE peak of each of the amplifier is at or near the amplifiers linear-compression transition region, providing a multistage power amplifier that is power efficient and has desirable amplitude to amplitude and amplitude to phase power transfer characteristics. The amplifier is designed by matching the output impedance of a final stage with a load. Amplifier stages are iteratively designed from the last stage to the first. At each stage, an amplifier and drive circuit are designed. The drive circuit and amplifier are designed to provide each stage with output impedance matched to the input impedance of the following stage and to operate at or near the PAE peak of the amplifier.

Abstract: A method of settling an amplifier and a multistage amplifier are provided. To settle an amplifier, a plurality of clock signals are, respectively, applied to preset switches, each of which is placed between amplifiers connected in cascade, to open the preset switches sequentially, thereby settling the amplifiers in order.

Abstract: A clipping circuit to limit amplitude of an orthogonal baseband signal includes a 16-gonal clipping circuit almost equivalent to a circular clipping circuit. The 16-gonal clipping circuit includes plural stages of series-connected units each including a rectangular clipping circuit and a phase rotating module. To compensate for variation in the signal amplitude due to the rectangular clipping circuits and the phase rotating modules, an amplitude adjuster conducts amplitude scaling for the signal.

Abstract: A non-linearity generator operates on a signal between a frequency converter and an amplifier and acts as a postdistorter for the component it follows and as a predistorter for the component it precedes, thus linearizing the overall input-output characteristic of the circuit. Cross-modulation components distorting an injected pilot signal provide a feed-back signal that is used to control the distortion applied by a non-linearity generator. The non-linearity generator can be adapted to cope with widely spaced input tones. The circuit may form part of a transmitter or a receiver.

Abstract: A driving circuit for driving a capacitive load promptly to a target voltage is to have a broad dynamic range and achieve a high accuracy output and saving in the surface area with low power dissipation. A first period and a second period are provided in one data driving period. During the first period, a transistor amplifier for driving the load for charging, with a setting drive voltage (V1), and a transistor amplifier for driving the load for discharging, with a setting drive voltage (V2), with V1<V2, are both enabled for actuation and, during the second period, the transistor amplifier performing either the driving for charging or the driving for discharging, and a constant current source, performing the reverse of the operation of the transistor amplifier, are actuated, for driving the load to the target voltage.

Abstract: A feed-forward operational amplifier including a dedicated summer circuit for summing a signal generated by a first amplifier stage of a feed-forward amplifier and a signal received from an external source to generate a sum signal and a second amplifier stage coupled to the summer circuit and receiving the sum signal. The second amplifier stage realizes a pole-zero doublet to decrease a unity gain frequency of the feed-forward operational amplifier.

Abstract: A multi-stage amplifier including a first amplifier stage including a first transistor, the first transistor selected to provide an optimum noise characteristic, and a second amplifier stage including a second transistor, the second transistor selected to provide an optimum gain characteristic.

Abstract: A gain-control method and device that enable high-speed gain switching of cascaded programmable gain amplifiers (PGA) without a high-resolution A/D converter is provided. In one example, the gain-control method for cascaded PGAs detects all the input levels of the PGAs, calculates the optimum gains of the PGAs each on the basis of the detection results, and sets the obtained optimum gains of each of the PGAs at one time, whereby high-speed gain switching becomes possible. The gain-control device for cascaded PGAs that implements this gain-control method includes peak hold circuits that retain the input levels of each of the PGAs, a switch group that sequentially switches outputs of the peak hold circuits, an A/D converter that sequentially detects the outputs from the switch group, and a control and operation device that calculates the optimum gains of the PGAs from the detection results by the A/D converter to set the calculated optimum gains simultaneously to each of the PGAs.

Abstract: A transmission channel for a subscriber line interface circuit comprises a front end, tip/ring current-sensing transimpedance stage, containing relatively low valued tip and ring sense resistors coupled in circuit with tip and ring paths of a telecommunication wireline pair. The front end transimpedance stage transforms differential tip and ring input currents sensed by the tip and ring sense resistors into a single ended voltage, which is coupled to a transconductance amplifier filter/gain stage. The filter/gain stage is configured to provide a programmable output impedance, and converts the voltage from the current-sensing transimpedance stage into an output transmission voltage for application to a selected one of a current-sense, voltage-feed, or voltage-sense, voltage-feed telecommunication circuit.

Abstract: An initial-stage amplifier 1 that deals with microsignals and other amplifiers 2 and 3 separate a power source line, and both separated power source lines 4 and 8 are commonly connected to a power source pad 6. This enables avoidance of the occurrence of a large potential difference between the initial-stage amplifier 1 and other amplifiers 2 and 3 due to differences in currents pulled to the amplifiers 1 to 3, and can prevent the occurrence of noise arising from such potential difference. Also, feedback loops are differentiated by the initial-stage amplifier 1 and other amplifiers 2 and 3. This can also prevent unfavorable effects where a large signal would be fed back from the rear-stage amplifiers 2 and 3 to the initial-stage amplifier 1.

Abstract: An amplifier chain with sequential DC offset correction for use in a radio receiver is provided. The amplifier chain has at least first and second amplifier stages connected in series. The first and second stages include an amplifier and a track and hold circuit connected in parallel across the amplifier. The track and hold circuit has a tracking state and a holding state. A control signal is coupled to the track and hold circuits of the first and second stages. The control signal is configured to set the track and hold circuits to the tracking state, which may be done simultaneously, and to sequentially set the track and hold circuit of the first stage to the holding state and then set the track and hold circuit of the second stage to the holding state.

Abstract: A two-stage amplifier includes a first stage and a second stage that are DC-connected through a coupling capacitor Cp. A charge pump generates a bias voltage Vp that is applied across the coupling capacitor Cp leads to maintain the time average of the voltage across said coupling capacitor constant.

Abstract: A bias condition of at least one amplifier among amplifiers other than a last-stage amplifier is set in consideration of the relation between an idle current and a saturation current.

Abstract: An amplifier and bypass switch circuit includes a circuit input, a circuit output, an amplifier and a switching circuit. The amplifier has an amplifier control input, and a first amplifier output. The amplifier control input is connected to the circuit input. The amplifier output is connected to the circuit output. The switching circuit includes a control input, a switch input, a switch output and a phase matching network. The switch output is connected to the circuit output. The switch input is connected to the circuit input. The phase matching network preserves phase information when the amplifier and bypass switch circuit switches between an amplifier mode and a bypass mode.

Abstract: A powered transducer preamplifier includes a preamplifier circuit that DC couples the preamplifier input with the preamplifier output. A biasing circuit is coupled to the preamplifier input to apply a bias voltage to power the transducer, and a DC level shifting circuit is DC coupled to the signal path of the preamplifier circuit between the input and the output to compensate for this bias voltage. The DC level shifting circuit avoids the use of reactive components, and thereby reduces phase distortion. A variety of DC level shifting circuits can be used, including a bridge circuit having four matched resistors and an inverter DC coupled between the nodes of the bridge.

Abstract: An audio amplifier circuit comprises a voltage-gain amplifier and a current-gain amplifier in series between an input node and an output node. Power supply lines are provided for providing power to the audio amplifier circuit. An outer negative feedback loop is provided around the current gain amplifier and the voltage gain amplifier, and an inner negative feedback loop is provided around the voltage gain amplifier. A first switch is provided for selectively connecting the power supply lines to the current-gain amplifier. A second switch is provided for selectively switching the inner negative feedback loop or the outer negative feedback loop to the voltage-gain amplifier. A control circuit is also provided to control the switches during power supply switching.

Abstract: A coupler/isolator alternatively couples and isolates unit amplifiers of a multiple stage chopper amplifier to shift gradually and slightly reset timing and amplification timing of the chopper amplifiers. In this way, a first-stage chopper amplifier to an n-th timing of the chopper amplifiers. In this way, a first-stage chopper amplifier to an n-th stage chopper amplifier are sequentially reset. The first-stage chopper amplifier to the n-th stage chopper amplifier are sequentially operated to amplify, in a pipeline format, a differential voltage between a signal voltage input to a signal voltage input terminal and a reference voltage input to a reference voltage input terminal, and supply the amplified differential voltage to a next-stage circuit.

Abstract: A method and apparatus for improving the AC common mode rejection performance of monolithic two op-amp instrumentation amplifiers is disclosed. A new approach to designing the first op-amp of an instrumentation amplifier is provided wherein the frequency of the first op-amp is manipulated such that the dominant pole is pushed out to higher frequencies than is possible using traditional methods while maintaining good open loop gain and closed loop stability. One way to achieve this is by designing the first op-amp such that it has two dominant, low frequency poles and a higher frequency zero to provide stability. With this design of a first op-amp, the range of high common mode rejection ratio is extended to frequencies an order of magnitude higher than achievable by conventional means without additional requirements for bandwidth, power or die area.

Abstract: A radio communication device has a first variable power amplifier 19 and a second variable power amplifier 20 and performs gain control of the variable power amplifiers 19 and 20 by a variable power amplifier control section 27 for controlling transmission power of the radio communication device. At this time, the variable power amplifiers 19 and 20 are switched on and off under the control of a switch control section 25 in response to the theoretical value of transmission power updated based on the transmission power of the radio communication device detected by a transmission power detection section 24 or a transmission power control bit extracted by a base band signal processing section 16 for prolonging the time period over which the variable power amplifier 19 or 20 is off.

Abstract: An amplifier circuit for amplifying an input signal to generate an amplifier output signal incorporates a cascaded series of reflection amplifiers arranged along a signal path and operative to amplify signals propagating in a forward direction along the signal path. The circuit is operative to counteract signal propagation in a reverse direction along the signal path, thereby hindering spontaneous oscillation from arising within the circuit. Incorporation of reflection amplifiers into the circuit enables it to provide high gain, for example 50 dB, while consuming low currents, for example, tens of microamperes. The circuit is especially suitable for use at intermediate frequencies in radio receivers such as mobile telephones.

Abstract: Disclosed in this application is the placement of an additional integrator between the first stage integrator output and the input to the attenuator/low pass filter. This approach reduces the input referred offset by a factor equal to the gain of the additional integrator, and the offset of the additional integrator itself will be divided by the gain of the first-stage integrator.

Abstract: The stages of a multistage amplifier are quickly switched between operational modes, e.g., from a standby mode to an active mode. The delivery of a control signal to each individual stage is delayed so that the modes of the stages are switched, in a desired sequence. The final amplifier stage is isolated from the operational mode switching of the preceding stages by a buffer. For switching the multistage amplifier from the standby mode to the active mode, the stages and the buffer are turned on, in a desired sequence, beginning with the first stage. For switching the multistage amplifier from the active mode to the standby mode, the stages and the buffer are turned off, in a desired sequence, beginning with the buffer. A delay unit includes a plurality of delay units, one connected to each amplifier stage, except the final amplifier stage, and to the buffer.

Abstract: A wideband predistortion system compensates for a nonlinear amplifier's frequency and time dependent AM—AM and AM-PM distortion characteristics. The system comprises a data structure in which each element stores a set of compensation parameters (preferably including FIR filter coefficients) for predistorting the wideband input transmission signal. The parameter sets are preferably indexed within the data structure according to multiple signal characteristics, such as instantaneous amplitude and integrated signal envelope, each of which corresponds to a respective dimension of the data structure. To predistort the input transmission signal, an addressing circuit digitally generates a set of data structure indices from the input transmission signal, and the indexed set of compensation parameters is loaded into a compensation circuit which digitally predistorts the input transmission signal.

Abstract: An integrated power operational amplifier can alternatively be operated in a master or a slave mode, such that a master amplifier can be connected in parallel with one or more slave amplifiers. This arrangement allows very low impedance loads to be driven, as well as allowing the heat dissipation to be distributed over a number of operational amplifiers, thereby raising the maximum dissipation limits of integrated power systems. In addition, by eliminating the ballast resistors, more power can be delivered by the system, for the same supply voltage, and less power is dissipated.

Abstract: A switched capacitor anplifier circuit is provided with two independent reference voltages, one which provides an appropriate bias level for the amplifiers, and one which sets a common mode input level for the amplifiers, thereby allowing the dynamic range to be maximized.