D.c. Coupled Patents (Class 330/181)
  • Patent number: 7804432
    Abstract: An integrated circuit device includes an amplifier circuit that includes first to Nth amplifiers, an A/D converter, first to Nth offset adjustment registers that are provided corresponding to the first to Nth amplifiers and store first to Nth offset adjustment data, first to Nth D/A converters provided corresponding to the first to Nth amplifiers, first to Nth offset value storage sections that store first to Nth offset value data, and a control circuit that calculates the first to Nth offset adjustment data based on the first to Nth offset value data, and sets the first to Nth offset adjustment data in the first to Nth offset adjustment registers.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: September 28, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Akihiro Fukuzawa, Nobuyuki Imai, Satoru Ito
  • Patent number: 7633773
    Abstract: A structure and method for reducing the effects of chip-package resonance in an integrated circuit assembly is described. A series RLC circuit is employed to reduce the output impedance of the power delivery system at the resonance frequency.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: December 15, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Houfei Chen
  • Publication number: 20090212860
    Abstract: An integrated circuit device includes an amplifier circuit that includes first to Nth amplifiers that are cascaded and receives an input signal, an A/D converter that performs an A/D conversion process on a signal amplified by the amplifier circuit, first to Nth D/A converters that are provided corresponding to the first to Nth amplifiers and used to perform an offset adjustment of the first to Nth amplifiers, and a control circuit that sets an offset adjustment of the first to Nth amplifiers using the first to Nth D/A converters and a gain adjustment of the first to Nth amplifiers.
    Type: Application
    Filed: February 20, 2009
    Publication date: August 27, 2009
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Akihiro FUKUZAWA, Satoru ITO, Nobuyuki IMAI
  • Patent number: 5898337
    Abstract: In an output signal level control circuit, a level adjusting section receives an input signal to adjust the input signal in level in response to a level control signal. A branching circuit branches a portion of the input signal adjusted in level by the level adjusting section to produce a branched signal. A detecting section includes the first and second detecting sections and generates a detection resultant signal based on a first detection result of the branched signal by the first detecting section and a second detection result of the branch signal by the second detecting section. The first and second detecting sections are operable at a same time. A control signal generating unit generates the level control signal based on the detection resultant signal to output to the level adjusting section.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: April 27, 1999
    Assignee: NEC Corporation
    Inventor: Atusi Inahasi