Abstract: Embodiments relate to an amplifier circuit. The amplifier circuit includes multiple transistors. Each transistor is configured to receive an input signal and output an amplified signal. The amplifier circuit additionally includes a set of input chopper circuits and a set of output chopper circuits. Each output chopper circuit corresponds to one input chopper of the set of input choppers. Each input chopper circuit and its corresponding output chopper are controlled by one or more control signals from a set of control signals. Each input chopper circuit is configured to selectively connect each transistor of a transistor pair to a first input terminal or a second input terminal based on a value of the one or more control signals. Moreover, each output chopper circuit is configured to selectively connect each transistor of the transistor pair to a first output terminal or a second output terminal based on the value of the one or more control signals.

Abstract: Envelope tracking power supply circuitry includes a look up table (LUT) configured to provide a target supply voltage based on a power envelope measurement. The target supply voltage is dynamically adjusted based on a delay between the power envelope of an RF signal and a provided envelope tracking supply voltage. The envelope tracking supply voltage is generated from the adjusted target supply voltage in order to synchronize the envelope tracking supply voltage with the power envelope of the RF signal.

Abstract: One example discloses a level-shifter circuit, comprising: a pre-driver stage configured to receive differential inputs and generate differential pre-driver outputs; a first output stage coupled to receive the differential pre-driver outputs and generate a single-ended first stage output; a second output stage coupled to receive the differential pre-driver outputs and generate a single-ended second stage output; and wherein the first and second stage outputs together form a differential output.

Abstract: An example transconductance circuit includes a first portion that includes a first degeneration transistor, configured to receive a first input voltage, and a second portion that includes a second degeneration transistor, coupled to the first degeneration transistor and configured to receive a second input voltage. The first portion further includes a first input transistor, coupled to the first degeneration transistor and configured to provide a first output current, while the second portion further includes a second input transistor, coupled to the second degeneration transistor and configured to provide a second output current. Such a transconductance circuit may be used as an input stage capable of reliably operating within drain-source breakdown voltage of the transistors employed therein even in absence of any other protection devices, and may be significantly faster, consume lower power, and occupy smaller die area compared to conventional transconductance circuits.

Abstract: Disclosed is a phase shifter, which includes a signal generator that generates a first signal and a second signal having a phase orthogonal to a phase of the first signal, and outputs the first signal and the second signal, an operator that generates a first current and a second current, and amplifies the first current and the second current, and a signal converter converting a first digital signal and a second digital signal. The operator includes an input circuit converting the first signal and the second signal, a path selection circuit determining paths of the generated first current and the generated second current, and a cascode circuit buffering the first current and the second current. The operator sums the first current and the second current, controls a vector of the first current and a vector of the second current, and generates a voltage signal through an output load.

Abstract: Provided is a control circuit of a buck converter, comprising three transistors, seven resistors and a comparator. Also provided is a server. In this solution, when a phase voltage of a buck converter changes, a controller in the buck converter is controlled to output a signal for turning off a lower MOS transistor, so that after the signal is transmitted through the line, the lower MOS transistor can be controlled to be exactly turned off just when the current is reversed. Such an accurate reverse current detection function can reduce the voltage loss of the buck converter, thereby improving the efficiency of a system in standby or having a light load.

Abstract: In an embodiment, an electronic circuit includes: an input differential pair including first and second transistors; a first pair of transistors in emitter-follower configuration including third and fourth transistors, and an output differential pair including fifth and sixth transistors. The third transistor has a control terminal coupled to the first transistor, and a current path coupled to a first output terminal. The fourth transistor has a control terminal coupled to the second transistor, and a current path coupled to a second output terminal. The fifth transistor has a control terminal coupled to the first transistor, and a first current path terminal coupled to the first output terminal. The sixth transistor has a control terminal coupled to the second transistor, and a first current path terminal coupled to the second output terminal. First and second termination resistors are coupled between the first pair of transistors and the output differential pair.

Abstract: A data driving integrated circuit of the present embodiment may include a digital to analog converter configured to change a digital signal into an analog signal and an amplifier configured to receive the analog signal through an input terminal and output a data voltage to a pixel connected to a data line, wherein the amplifier may receive, as feedback, one of a plurality of output signals from a plurality of output terminals.

Abstract: An amplifier includes a first stage and a second stage. The first stage includes a floating current source to maintain current within a threshold. The first stage also includes a local common mode feedback configured to provide gain to an input signal. Moreover, the second stage includes a driver that provides a load current to a load coupled to the amplifier.

Abstract: Embodiments disclosed herein relate to isolating a receiver circuit of an electronic device from a transmission signal and leakage of the transmission signal. To do so, an isolation circuit is disposed between the receiver circuit and a transmission circuit. The isolation circuit may include multiple variable impedance devices and one or more antennas. The impedances of the variable impedance devices may be balanced such that a signal at a particular frequency or within a particular frequency band can pass through or is blocked by the isolation circuit. The isolation circuit may include one or more double balanced duplexers to achieve the improved isolation. The isolation circuit may also increase bandwidth available for wireless communications of the electronic device.

Abstract: A variable gain amplifier system includes a variable gain amplifier circuit configured to receive an input signal, apply a gain to the input signal, and generate an output signal in accordance with the gain applied to the input signal. The variable gain amplifier circuit is further configured to receive a gain control signal and a bandwidth control signal. A control module is configured to generate the gain control signal to adjust the gain of the variable gain amplifier circuit and generate, separately from the gain control signal, the bandwidth control signal to adjust a bandwidth of the variable gain amplifier circuit by selectively varying an amount of inductance contributed by an inductor circuit of the variable gain amplifier circuit.

Abstract: Aspects of this disclosure relate to a segmented receiver for a wireless communication system. The segmented receiver includes a first receiver segment and a second receiver segment configured to receive respective radio frequency signals. The radio frequency signals can be orthogonally polarized. Branch circuits in each receiver segment can provide a radio frequency signal to different mixers. The different mixers can be included in different receiver segments and receive local oscillator signals from independent local oscillators. Each receiver segment can process a different bandwidth of the radio frequency signal. Two different bandwidths of the radio frequency signal can be processed concurrently by different receiver segments.

Abstract: A linear power supply circuit includes an output transistor provided between an input terminal to which an input voltage is applied and an output terminal to which an output voltage is applied, and a driver configured to drive the output transistor based on the difference between a voltage based on the output voltage and a reference voltage. The driver includes a differential amplifier, a converter, and a first capacitor provided between the output of the differential amplifier and a ground potential. The linear power supply circuit further includes a source follower circuit including a first transistor, and moreover includes a second transistor connected in series with the output transistor and constituting together with the first transistor a current mirror circuit, and a second capacitor connected to the control terminal of the first transistor.

Abstract: Regulator circuitry includes first to third output transistors, a first control transistor and a circuit stage. The first and second output transistors, and the first control transistor have a first channel conductivity type. The second output transistor has a second channel conductivity type. The first and second output transistors have a drain coupled to an output node and a source coupled to a first power supply line. The third output transistor has a drain coupled to the output node and a source coupled to a second power supply line. The circuit stage is configured to drive the gates of the first output transistor, the third output transistor, and the first control transistor based on a specified level of the output voltage.

Abstract: Disclosed is an operational amplifier based on a metal-oxide TFT. The operational amplifier includes an auxiliary amplifier and a bootstrap gain-increasing amplifier. The auxiliary amplifier adopts a two-stage positive feedback structure, including a fifth transistor, a seventh transistor, an eleventh transistor, a first amplifying unit, and a second amplifying unit. A gate of the fifth transistor serves as an input end of the operational amplifier. The bootstrap gain-increasing amplifier includes two second circuits in mutual symmetry. Each of the second circuits includes a first transistor, a second transistor, and a current source unit with a bootstrap structure.

Abstract: Examples of the disclosure include an amplifier system comprising an amplifier having an input to receive an input signal, and an output to provide an amplified output signal, the amplifier having a power level indicative of at least one of the input signal power and the amplified output signal power, and a linearizer coupled to the amplifier and having a plurality of modes of operation including a fully disabled mode and a fully enabled mode, the linearizer being configured to determine the power level of the amplifier, select a mode of operation of the plurality of modes of operation based on the power level of the amplifier, determine one or more linearization parameters corresponding to the selected mode of operation, and control linearization of the amplified output signal based on the determined one or more linearization parameters.

Abstract: An automatic gain control circuit includes a linear-to-log conversion circuit, a current amplifier circuit, and an amplitude sense circuit. The current amplifier circuit includes a current input terminal coupled to an output terminal of the linear-to-log conversion circuit. The amplitude sense circuit includes an input terminal coupled to an output terminal of the current amplifier circuit, and an output terminal coupled to a gain control input terminal of the current amplifier circuit.

Abstract: A voltage-to-current converter circuit comprises an amplifier, a resistor, first and second feedback circuits, and an output circuit. The amplifier is configured to receive a differential input voltage signal. The resistor is coupled between first and second nodes of the amplifier. The first feedback circuit is coupled to a third node of the amplifier, provides feedback to the first and second nodes when the value of the input voltage signal is in a first range, and is turned off otherwise. The second feedback circuit is coupled to a fourth node of the amplifier, provides feedback to the first and second nodes when the value of the input voltage signal is in a second range different from the first range, and is turned off otherwise. The output circuit produces a differential current output signal having a value according to the value of the input voltage signal.

Abstract: Methods and devices to support multiple frequency bands in radio frequency (RF) circuits are shown. The described methods and devices are based on adjusting the effective width of a transistor in such circuits by selectively disposing matching transistors in parallel with the transistor. The presented devices and methods can be used in RF circuits including low noise amplifiers (LNAs), RF receiver front-ends or any other RF circuits where input matching to wideband inputs is required.

Abstract: A first transmission line and a second transmission line that are connected in series to each other are disposed at different positions in a thickness direction of a substrate. A third transmission line is disposed between the first transmission line and the second transmission line in the thickness direction of the substrate. The third transmission line includes a first end portion connected to one end portion of the first transmission line, and a second end portion that is AC-grounded. The first transmission line and the second transmission line are electromagnetically coupled to the third transmission line.

Abstract: An example apparatus includes: a receiver operable to receive a modulated input signal at a receiver input and output a demodulated signal at a receiver output, the receiver comprising a switch having a first current terminal and a first control terminal, the first current terminal coupled to the receiver output. The example apparatus includes a capacitor having a first terminal and a second terminal, the second terminal coupled to the first control terminal and the first terminal coupled to the receiver input. The example apparatus includes a resistor having a third terminal and a fourth terminal, the fourth terminal coupled to the first control terminal. The example apparatus includes a voltage offset source having an input and an output, the output coupled to the third terminal. The example apparatus includes a current source coupled to the first current terminal.

Abstract: In a limiting circuit that limits an output voltage of an operational amplifier, the signal quality of the output voltage is improved. The limiting circuit includes a short-circuit transistor and a gate voltage supply unit. In the limiting circuit, the short-circuit transistor short-circuits a path between an input terminal and an output terminal of the operational amplifier in a case where a voltage between the input terminal of the operational amplifier and the gate is higher than a predetermined threshold voltage. Furthermore, in the limiting circuit, the gate voltage supply unit supplies a voltage to the gate, the voltage depending on the threshold voltage and the output voltage of the output terminal.

Abstract: A transimpedance amplifier (TIA) device design is disclosed. Symmetric components include first and second resistors Ri, Rfb, Re, Rm, Rx, Rc, and Rl, and transistors Q1-Q4. An optional mixer or cascode adds transistors Q5-Q8. Values for resistor components Rx provide extended feedback gain tuning in a TIA-based current amplifier or mixer implementations without greatly affecting the input impedance or requiring more attenuators. Example values for resistor components Rx range from about 50 to about 350 ohms.

Abstract: A transimpedance amplifier circuit for generating an output voltage in accordance with an input current includes an offset resistor, a common emitter inverting amplifier having a first input and a first output, the first input receiving the input current, an emitter follower having a second input and a second output, the second input being coupled to the first output through the offset resistor, the second output outputting the output voltage, a feedback resistor connected between the second output and the first input, a variable current source connected to a node between the offset resistor and the second input, the variable current source configured to provide an offset current to the offset resistor, the offset current having a current value varied in accordance with a control signal, and a control circuit configured to generate the control signal so that an average voltage of the first output approaches a preset voltage value.

Abstract: An apparatus includes a load pair including a first transistor and a second transistor, a common mode feedback circuit comprising a first common mode feedback transistor and a second common mode feedback transistor, wherein a drain of the first common mode feedback transistor is coupled to a source of the first transistor, and a gate of the first common mode feedback transistor is coupled to a drain of the first transistor, and a drain of the second common mode feedback transistor is coupled to a source of the second transistor, and a gate of the second common mode feedback transistor is coupled to a drain of the second transistor, and an offset cancellation stage coupled to outputs of the load pair.

Abstract: In a solid-state imaging element provided with a differential pair of transistors, noise of a signal from the differential pair is reduced. The semiconductor integrated circuit includes a pixel circuit and a pair of TFETs (Tunnel Field Effect Transistors). In the semiconductor integrated circuit, the pixel circuit photoelectrically converts incident light to generate a pixel signal. Further, in the semiconductor integrated circuit, the pair of TFETs amplifies the difference between the pixel signal generated by the pixel circuit and a predetermined reference signal that changes with time, and outputs the amplified difference as a differential amplification signal.

Abstract: A dry cask storage system for spent nuclear fuel includes a detection apparatus having a resonant electrical circuit, with resonant electrical circuit being situated within an interior region of a metallic vessel wherein the SNF is situated. The detection apparatus includes a transmitter that generates an excitation pulse that causes the resonant circuit to resonate and to generate a response pulse. The resonant circuit includes an inductor that is formed with a core whose magnetic permeability varies with temperature such that the frequency of the resonant circuit varies as a function of temperature. The response pulse is then used to determine the temperature within the interior of the vessel where the SNF is situated. Pressure detection is also provided.

Abstract: The present general inventive concept is directed to a method and system to generate a power signal, including summing a non-inverted reference signal and an inverted feedback signal to output a non-inverted first summation signal, summing an inverted reference signal and a non-inverted feedback signal to output an inverted second summation signal, receiving the first summation signal at a non-inverted input of a differential power output driver, and the second summation signal at an inverted input of the differential power output driver, outputting a non-inverted power signal to a first terminal of an impedance load from a non-inverted output of the differential power output driver, and outputting an inverted power signal to a second terminal of the load from an inverted output of the differential power output driver, the non-inverted power signal also being used as the non-inverted feedback signal, and the inverted power signal also being used as the inverted feedback signal.

Abstract: A system includes a pixel that emits light based on a signal provided to the pixel. The system may also include a buffer circuit having a differential pair stage, a cascade stage, and an output stage. The differential pair stage may receive a common mode voltage signal via a first switch in response to the first switch receiving a first signal that causes the first switch to close. The differential pair stage may couple a capacitor to the output stage via a second switch that operate based on a second signal, such that the capacitor reduces an offset provided by one or more circuit components in the differential pair stage, the cascade stage, the output stage, or any combination thereof. The differential pair stage may output the common mode voltage to the pixel via the output stage in response to the first signal being present.

Abstract: A sensor failure prediction system is a sensor failure prediction system that predicts a failure of a physical quantity sensor including a vibrator element which is driven and vibrates by a drive signal and outputs a detection signal based on a physical quantity, and includes a memory that stores reference information on a reference value of the drive signal or the detection signal, and a processor that outputs prediction information on a stepwise or continuous state until the physical quantity sensor fails, based on signal information on a measurement value of the drive signal or the detection signal and the reference information.

Abstract: An operational amplifier 1 comprises transistors Q1 and Q2 forming an input stage, and input resistors R1 and R2 which form a filter together with parasitic capacitors C1 and C2 accompanying the transistors Q1 and Q2. Resistance values R of the resistors R1 and R2 may be set to R=1/(2?·fc·C), where C is the capacitance value of each of the parasitic capacitors C1 and C2, and fc is the target cutoff frequency of the filter. The operational amplifier 1 may also include a power supply resistor R0 which forms a filter together with a parasitic capacitor C0 accompanying a power supply line.

Abstract: In one embodiment, an RF power amplifier includes a first transistor and a second transistor in parallel, wherein a gate of the first transistor and a gate of the second transistor are configured to be driven by an RF source. A third transistor comprising a drain is operably coupled to both a source of the first transistor and a source of the second transistor. A control circuit is operably coupled to a gate of the third transistor and configured to alter a gate-to-source voltage of the third transistor, thereby altering a drain current of each of the first transistor and the second transistor, thereby altering an output power of the RF power amplifier.

Abstract: A transistor amplifier includes at least one differential pair of transistors and a plurality of transformers having a primary winding and a tapped secondary winding. The secondary winding is connected across emitters or sources of each transistor pair. The tap of each secondary has a current source. The primary windings of the plurality of transformers are connected in series. The transistor bases or gates are alternating current (AC) grounded. The collector or drain terminal pairs are connected in parallel. The transistor amplifier exhibits improved input impedance and improved linearity.

Abstract: In some embodiments, a wireless local area network (WLAN) front-end can be implemented on a semiconductor die having a semiconductor substrate, and a power amplifier implemented on the semiconductor substrate and configured for WLAN transmit operation associated with a frequency range. The semiconductor die can further include a low-noise amplifier (LNA) implemented on the semiconductor substrate and configured for WLAN receive operation associated with the frequency range. The semiconductor die can further include a transmit/receive switch implemented on the semiconductor substrate and configured to support the transmit and receive operations.

Abstract: Embodiments of improved CMOS input stage circuits and related methods are provided herein to maintain a near constant transconductance across an entire common-mode input voltage range of the input stage. One embodiment includes a pair of NMOS input transistors and a pair of PMOS input transistors, each coupled to receive a differential input voltages at their gate terminals; a current source coupled to source terminals of the pair of PMOS input transistors and configured to generate a current; a current steering circuit configured to steer the current to the pair of NMOS input transistors and/or to the pair of PMOS input transistors, depending on whether a common mode input voltage (CMV) is greater than, less than, or substantially equal to a cross-over voltage; and a current stealing circuit configured to reduce the current when the CMV is substantially equal to the cross-over voltage.

Abstract: A signal processing circuit includes a signal receiving circuit for generating a first input signal and a second input signal; a signal output circuit for generating a first output signal and a second output signal according to the first input signal and the second input signal; a negative impedance circuit, for amplifying the first input signal at the first input terminal to generate a first amplified input signal at the second output terminal, and for amplifying the second input signal at the second input terminal to generate a second amplified input signal at the first output terminal; a first capacitor; a second capacitor; wherein the first capacitor and the second capacitor have different DC voltage levels at both terminals, such that the impedance-signal variation rate of the negative impedance circuit is lower than a predetermined level.

Abstract: The present application provides an apparatus for processing signals of a high-voltage loop, a detector, a battery device, and a vehicle. The apparatus includes a filter circuit connected to an element to be detected and configured to filter signals from the element to be detected; a differential amplification circuit connected to the filter circuit and configured to amplify the filtered signals; and a processor connected to the differential amplification circuit and configured to process the amplified signals.

Abstract: A low voltage inverter-based amplifier includes a first inverter-based amplification module, a second inverter-based amplification module, an inverter-based feedforward module, and an inverter-based common mode detector. The first inverter-based amplification module receives an input signal. The second inverter-based amplification module receives the input signal through the inverter-based feedforward module, and receives a first output signal from the first inverter-based amplification module. The inverter-based common mode detector receives an amplified signal from the second inverter-based amplification module, and outputs a feedback signal to the second inverter-based amplification module. Since the first and the second inverter-based amplification modules are both inverter-based, the supply voltage of the low voltage inverter-based amplifier is provided to supply one PMOS and one NMOS for normal operation.

Abstract: An instrumentation amplifier configured for providing high common mode rejection is described and includes an input differential stage configured to receive a differential input voltage and a folded cascode amplifying stage configured to receive output current mode signals provided from the input differential pair. A plurality of feedback networks is provided to improve the input stage. The amplifier may operate to provide an enhanced common mode rejection ratio of a single gain block in the instrumentation amplifier. In some examples, the circuitry may have a differential folded cascode amplifying stage which permits high precision and low distortion of amplified signals without degrading the common mode rejection ratio.

Abstract: A negative-operand compatible subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes two sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of two sets of scaled capacitors electrically connected to the difference output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The subtractor circuit includes a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground. A control circuit of the subtractor is configured to, in conjunction with the reset circuit, draw the difference output node to a reset voltage.

Abstract: A circuit includes a first signal swapper including a first terminal coupled to a first current source, a second terminal coupled to a second current source, a third terminal coupled to a first current terminal of a first transistor, and a fourth terminal coupled to a third current terminal of a second transistor. The first signal swapper couples the first and second terminals to the third and fourth terminals responsive to a first control signal. First and second switches couple to a gate of the first transistor. The first switch receives the input oscillation signal and the second switch receives a first reference voltage. Third and fourth switches couple to a gate of the second transistor. The third switch receives the input oscillation signal and the fourth switch receives the first reference voltage. A second signal swapper couples to the first signal swapper and to the first and second transistors.

Abstract: A circuit for receiving signals in an integrated circuit device. The circuit comprises a first equalizer circuit having a first input for receiving a first input signal and generating an output signal at a first output; a second equalizer circuit having a second input for receiving the output signal generated at the first output of the first equalizer circuit and having a second output; and a control circuit having a control output coupled to the second output of the second equalizer circuit; wherein the control circuit provides an offset cancellation signal or a loopback signal to the second output of the second equalizer circuit. A method of receiving signals in an integrated circuit is also described.

Abstract: A preamplifier circuit includes a first transconductor and a floating transconductor. The first transconductor receives a differential voltage from a sample-and-hold circuit and drives the floating transconductor. The first and floating transconductors output amplified versions of the differential voltage that are not affected by capacitive division, which makes the preamplifier circuit fast. The preamplifier circuit also has a low input capacitance because the floating transconductor is not connected to any external circuitry.

Abstract: The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input and generates a first load current. A first output node is coupled to a power supply through a first load resistor. The first load resistor receives the first load current. A first capacitor network is coupled to the first output node and draws a first capacitive current from the first output node. A first current buffer is coupled between the first output node and the first transistor. A current through the first current buffer is a summation of the first load current and the first capacitive current.

Abstract: In a general aspect, a circuit can include an amplifier circuit including a first amplifier, a first feedback path, and a second feedback path. The first feedback path can provide a feedback path from a positive output of the first amplifier to a negative input of the first amplifier. The second feedback path can provide a feedback path from a negative output of the first amplifier to a positive input of the first amplifier, The circuit can also include a loop circuit including a second amplifier, The loop circuit can be configured to provide a local feedback loop for the first amplifier and configured to control current flow into the positive input of the first amplifier and into the negative input of the first amplifier.

Abstract: The present invention relates to a novel and inventive compound device structure for a low noise current amplifier or trans-impedance amplifier. The trans-impedance amplifier includes an amplifier portion, which converts current input into voltage using a complimentary pair of novel n-type and p-type current field-effect transistors (NiFET and PiFET) and a bias generation portion using another complimentary pair of NiFET and PiFET. Trans-impedance of NiFET and PiFET and its gain may be configured and programmed by a ratio of width (W) over length (L) of source channel over the width (W) over length (L) of drain channel (W/L of source channel/W/L of drain channel).

Abstract: An operational amplifier with a constant transconductance bias circuit and a method thereof are introduced. The operational amplifier includes a differential difference amplifier and the constant transconductance bias circuit. The differential difference amplifier has at least one first differential transistor pair and at least one second differential transistor pair. The constant transconductance bias circuit is electrically connected to the differential difference amplifier, and configured to output a first bias voltage to bias the at least one first differential transistor pair and output a second bias voltage to bias the at least one second differential transistor pair. The first bias voltage and the second bias voltage are configured to maintain constant transconductance of the differential difference amplifier.

Abstract: In some examples, an amplifier stage includes a voltage-gain amplifier stage and a negative capacitance circuit coupled to the voltage-gain amplifier stage, the negative capacitance circuit comprising a first transistor that provides a first temperature-biased current.

Abstract: The present invention relates to a novel and inventive compound device structure for a low noise current amplifier or trans-impedance amplifier. The trans-impedance amplifier includes an amplifier portion, which converts current input into voltage using a complimentary pair of novel n-type and p-type current field-effect transistors (NiFET and PiFET) and a bias generation portion using another complimentary pair of NiFET and PiFET. Trans-impedance of NiFET and PiFET and its gain may be configured and programmed by a ratio of width (W) over length (L) of source channel over the width (W) over length (L) of drain channel (W/L of source channel/W/L of drain channel).

Abstract: A low dropout (LDO) device with improved linear mode comprising an error amplifier, a programmable attenuation factor circuit coupled to said error amplifier, a feedback network whose input is electrically connected to said programmable attenuation factor circuit and whose output is electrically coupled to the negative input of said error amplifier, a high side (HS) pre-drive circuit whose input is a high impedance (HiZ) mode signal, a low side (LS) pre-drive circuit whose input is a low pull-down input mode signal, a high side (HS) output stage element electrically coupled to said high side (HS) pre-drive circuit, a low side (LS) output stage element electrically coupled to said low side (LS) pre-drive circuit, and a high side sense (HSENSE) output stage element whose gate is electrically coupled to said high side (HS) pre-drive circuit, and whose gate and source are electrically connected to the output of said error amplifier.