Abstract: The invention provides method and associated controller for improving temperature adaptability of an amplifier; the method may include: receiving a temperature value, and adjusting a supply voltage supplied to the amplifier according to the temperature value.

Abstract: A method and apparatus for increasing the Signal-to-Noise Ratio (SNR) of phononic comb teeth generated by a non-linear resonator. The method comprises generating a drive signal; applying the drive signal to the non-linear resonator with sufficient gain to generate the phononic comb teeth; and filtering the drive signal before applying it to the non-linear resonator to thereby increase the Signal-to-Noise Ratio (SNR) of phononic comb teeth generated by the non-linear resonator. The apparatus may comprise a circuit including a filter disposed between an oscillator generating the drive signal and the non-linear resonator, the filter preferably having a 3 db passband width which is less than a spacing of the phononic comb teeth generated by the non-linear resonator.

Abstract: This document presents an oscillator circuit and method. The oscillator circuit has a crystal to generate an oscillating voltage signal, a load capacitor coupled to the crystal, a capacitive element, and a switching circuit. The switching circuit alternately connects the capacitive element to the load capacitor and disconnects the capacitive element from the load capacitor. The presented oscillator circuit shows the advantages of a lower power consumption and a smaller circuit area.

Abstract: A display driver IC includes a register map, an oscillator, a timing controller, an oscillator scatter, and an intellectual property (IP) block. The register map is configured to store a trim code of a fixed frequency and scatter option information. The oscillator is configured to generate an oscillator clock based on the trim code. The timing controller is configured to generate an internal synchronization signal based on the oscillator clock. The oscillator scatter is configured to output a modified trim code to the oscillator based on the trim code, the scatter option information, and the internal synchronization signal. The intellectual property (IP) block is configured to receive a modified oscillator clock generated in the oscillator based on the modified trim code.

Abstract: A device and method for terahertz signal generation are disclosed. Oscillators are arranged in a two-dimensional array, each oscillator connected to a corresponding antenna. Each oscillator is unidirectional connected to its adjacent oscillators by a phase shifter. A method for generating a steerable terahertz signal utilizes an array of oscillators connected by corresponding phase shifters. A terahertz signal having a fundamental frequency is generated using the array. The phase shift of one or more of the phase shifters is varied in order to vary the fundamental frequency and/or steer the signal generated by the array.

Abstract: An improved noise-corrected phase-locked loop frequency synthesizer configured to reduce noise, such as phase noise and spurious signals, without the use of switching circuits. The synthesizer uses a phase shifter device configured to accept a noise containing frequency signal from a voltage controlled oscillator (VCO) circuit, such as an integer-N single loop PLL synthesizer, as well as noise reducing control signals from a noise detecting sensor or circuit, and output a noise reduced VCO frequency signal. In some embodiments, the noise reducing sensor may be formed from a second, lower noise, phase locked loop circuit. The frequency synthesizer circuit, noise detecting sensor, and the phase shifter device are configured to all run continuously, with the noise reducing sensor and frequency shifter continually acting to reduce noise, produced by higher noise integer-N PLL frequency synthesizer.

Abstract: An oscillator has an oscillator output emitting an oscillating signal. The oscillator includes oscillator cores which each have a same circuit topology. A set of configuration switches couple a selected number of oscillator cores in parallel to generate the oscillating signal. The oscillator cores are arranged with a symmetry around a central axis. The planar inductors of the oscillator cores are arranged in a petal-like pattern with the planar inductors forming the petals of the petal-like pattern. The selected coupling of the oscillator cores in made in response to a selected phase noise threshold of a modulation device which receives the oscillating signal.

Abstract: The present invention is directed to a transmitter system. The system is made up of a reference clock, a differential oscillator and an edge combining power amplifier (ECPA). The clock feeds a low frequency reference signal into the differential oscillator to produce at least two low frequency outputs with opposite phases. Each low frequency output is made up of a number of low frequency subsignals equal to the number of oscillator stages. Each low frequency output is fed into a branch in the ECPA having a number of sub-branches equal to the number of oscillator stages. A processor uses an edge combining algorithm to combine these subsignals into a high frequency signal.

Abstract: A multiple phase oscillator includes a master oscillator that injection locks a first ring oscillator. The free-running frequency of the first ring oscillator is adjustable through a control signal. A second ring oscillator has a same structure as the first ring oscillator and is connected to operate in a free-running mode. The free-running frequency of the second ring oscillator is adjustable through the control signal. A control loop senses the output of the second ring oscillator and adjusts the control signal so that the free-running frequency of the second ring oscillator matches a desired value.

Abstract: Circuits for charging capacitors in connection with oscillators are described. The oscillator may include a mechanical resonator. The circuits may include a charging element and a switched capacitor subcircuit to control operation of the charging element, and may be considered a charging circuit in some scenarios. The charging circuits may provide rapid charging of a capacitor to provide a reference voltage to the oscillator.

Abstract: In a CR oscillation circuit, resistance elements forming a series circuit include a first resistance element having a large temperature coefficient of resistance and a second resistance element having a smaller temperature coefficient of resistance than the first resistance element. At least one of a capacitor and an oscillation resistance element is trimmable. A first switching circuit connected between the series circuit and a non-inverting input terminal of a comparator is turned on when an output signal of the comparator is at a high level, and a second switching circuit is turned on when the output signal is at a low level.

Abstract: Apparatus are provided for voltage-controlled oscillators (VCOs) and related systems. An exemplary VCO includes an active-circuit arrangement employing cross-coupled amplifying elements that facilitate generation of an oscillating signal, plus a resonator arrangement capacitively coupled via resonator terminals to primary terminals of the active-circuit arrangement, to influence an oscillation frequency of the oscillating signal based on a difference between control voltages applied to first and second control terminals of the resonator arrangement. When employing bipolar amplifying elements their control terminals are cross-coupled to the opposing resonator terminals. VCO output may be taken from the primary terminals or from the resonator terminals.

Abstract: Various techniques for generating an output clock based on a reference clock. This disclosure relates to generating an output clock signal based on a reference clock signal. In one embodiment, a method includes generating, using information received from a control circuit, an output clock signal using both a first number of edges or an input clock signal and a second, different number of edges of the input clock signal. In this embodiment, the control circuit runs at a frequency that is less than a frequency of the input clock signal. The received information may indicate, for a pulse of the output clock signal, whether the pulse should be generated using the first number of edges or the second number of edges. In some cases, the second number of edges may be the first number of edges plus one. The first and second number of edges may be programmable quantities.

Abstract: A gated voltage-controlled oscillator receives a gating signal and outputs an oscillating signal having a frequency corresponding to the gating signal. The gated voltage-controlled oscillator includes a delay unit, having a first terminal and a second terminal, and a multiplexer, having a first input terminal, a second input terminal, a select terminal and an output terminal. The first input terminal and the select terminal are coupled to the gating signal. The second input terminal is coupled to the first terminal of the delay unit. The output terminal outputs the oscillating signal and is coupled to the second terminal of the delay unit. The delay unit delays the oscillating signal and outputs the delayed oscillating signal into the second input terminal. The multiplexer outputs a signal of the first input terminal or the second input terminal according to the gating signal.

Abstract: A current controlled operational transconductance amplifier based sinusoidal oscillator circuit that provides oscillation based on the transconductance and parasitic capacitance of the operational transconductance amplifier without externally connected capacitances. The oscillation frequency is adjusted through a variable current source or a variable resistor with a DC voltage source.

Abstract: A MEMS device and method for amplitude regulation of a MEMS device are disclosed. In a first aspect, the MEMS device comprises a MEMS resonator, a limiter coupled to the MEMS resonator, and a regulator coupled to the limiter. The MEMS device includes an amplitude control circuit coupled to the MEMS resonator. The amplitude control circuit controls a supply of the limiter via the regulator to regulate oscillation loop amplitude of the MEMS device. In a second aspect, the method includes coupling a regulator to the limiter, coupling an amplitude control circuit to the MEMS resonator, and controlling a supply of the limiter via the regulator to regulate oscillation loop amplitude of the MEMS device.

Abstract: A phase shift phase locked loop (PSPLL) are described. The phase shift PLL includes a PLL and a phase adjusting circuit coupled to the inputs of the PLL. The phase adjusting circuit has a first input, a first output, a second input, a third input, and a second output. The first output and the second output are coupled to a first input and a second input of the PLL, respectively. The second input of the phase adjusting circuit receives a feedback signal and the third input of the phase adjusting circuit receives a control signal. The phase adjusting circuit receives a reference signal and sends a first output signal and a second output signal based on the reference signal to the PLL to adjust a phase of an output signal of the PLL in an increment less than a time period of the output signal of the PLL.

Abstract: Disclosed herein are a self-oscillation circuit having a means for eliminating a quadrature error and a method for eliminating a quadrature error using the circuit. The self-oscillation circuit having a means for eliminating a quadrature error according to an exemplary embodiment of the present invention includes: a voltage converter converting a current signal from the gyroscope sensor into a voltage signal, a signal magnitude detector measuring a magnitude of a quadrature error signal included in an output signal from the voltage converter, and a quadrature error eliminator generating a signal which has the same phase as the output signal from the voltage converter and the same magnitude as a signal measured by the signal magnitude detector, based on an output signal from the signal magnitude detector and the output signal from the voltage converter.

Abstract: A phase shifter includes controlling a phase of an output signal of an orthogonal modulator; and interchanging two kinds of signals inputted to the orthogonal modulator, interchanging each polarity of the two kinds of signals inputted to the orthogonal modulator, or interchanging both of the above. The two kinds of signals inputted to the orthogonal modulator are two pairs of differential signals.

Abstract: A programmable sinusoidal oscillator circuit is a sinusoidal oscillator circuit that includes a current-feedback operational-amplifier (CFOA) operably connected to two operational transconductance amplifiers (OTAs), two capacitors and a resistor. The programmable sinusoidal oscillator circuit enjoys electronic orthogonal tuning of the frequency and the condition of oscillation by adjusting the biasing currents (voltages) of the OTAs, as well as providing a low output impedance.

Abstract: The invention relates to an oscillator circuit, comprising a clipping element for generating a clipped signal, and a first amplification stage for amplifying and filtering the clipped signal to obtain a filtered signal, wherein the clipping element is configured to generate the clipped signal upon the basis of the filtered signal.

Abstract: The present disclosure provides a tunable signal source having a plurality of oscillator cores having a coupling input, a coupling output, and a power output that is common to each of the plurality of oscillator cores. Also included is a plurality of tunable phase shifters wherein corresponding ones of the plurality of tunable phase shifters are communicatively coupled between the coupling input and the coupling output of corresponding ones of the plurality of oscillator cores, thereby forming a loop of alternating ones of the plurality of oscillator cores and alternating ones of the plurality of tunable phase shifters.

Abstract: A resistance-capacitance oscillation circuit comprises an amplifier and a phase shifting circuit. The phase shifting circuit comprises at least three resistance-capacitance circuit elements, which comprise a resistance and a capacitance. At least one of the resistance-capacitance circuit elements comprises a variable resistance and a variable capacitance. The variable resistance is formed of a first electrode, a second electrode, a part of a semiconductor film, a part of a ferroelectric film, and a fourth electrode. The variable capacitor is formed of the second electrode, a third electrode, a fifth electrode, another part of the ferroelectric film, another part of the semiconductor film, and a paraelectric film.

Abstract: A resistance-capacitance oscillation circuit comprises an amplifier and a phase shifting circuit. The phase shifting circuit comprises at least three resistance-capacitance circuit elements, each of which comprises a resistance and a capacitor. At least one of the resistance-capacitance circuit elements comprises a variable resistance and a variable capacitor. The variable resistance is formed of a first electrode, a second electrode, a part of a semiconductor film, a part of a ferroelectric film, and a fourth electrode. The variable capacitor is formed of the second electrode, a third electrode, a fifth electrode, another part of the ferroelectric film, another part of the semiconductor film, and a paraelectric film.

Abstract: A phase-shift keying (PSK) demodulator and a smart card including the same are disclosed. The PSK demodulator includes a delay circuit and a sampling circuit. The delay circuit generates a plurality of clock signals by delaying the input signal. The sampling circuit samples the input signal in response to the clock signals, and generates output data.

Abstract: A MEMS device and method for amplitude regulation of a MEMS device are disclosed. In a first aspect, the MEMS device comprises a MEMS resonator, a limiter coupled to the MEMS resonator, and a regulator coupled to the limiter. The MEMS device includes an amplitude control circuit coupled to the MEMS resonator. The amplitude control circuit controls a supply of the limiter via the regulator to regulate oscillation loop amplitude of the MEMS device. In a second aspect, the method includes coupling a regulator to the limiter, coupling an amplitude control circuit to the MEMS resonator, and controlling a supply of the limiter via the regulator to regulate oscillation loop amplitude of the MEMS device.

Abstract: A tunable oscillator circuit is disclosed. The tunable oscillator circuit includes an inductor/capacitor (LC) tank circuit comprising a primary inductor coupled in parallel with a first capacitor bank. The LC tank resonates to produce an oscillating voltage at a frequency. The tunable oscillator circuit also includes a 90 degree phase shift buffer coupled to the LC tank and a transconductor. The transconductor is coupled to the 90 degree phase shift buffer and a secondary inductor. The tunable oscillator circuit also includes a secondary inductor that is inductively coupled to the primary inductor and receives a gain-scaled oscillating current from the transconductor. By changing the transconductance, the gain-scaled oscillating current in the secondary inductor will change, thus the effective primary inductance and the oscillation frequency can be tuned.

Abstract: Techniques are generally described herein related to filters including first operational transconductance amplifier (first OTA) and a second operational transconductance amplifier (second OTA). In some examples described herein, the first OTA and second OTA have substantially the same transconductance. The first and second OTAs can be configured to realize filters such as first-order all-pass filters, second-order all-pass filters, higher-order all-pass filters, and quadrature oscillators.

Abstract: Increasing loop gain is a common practice for reducing lock time of phase locked loops. Very high loop gains, however, often result in increasing the lock time or causing loop instability. For very high loop gains, delaying the feedback clock signal along the feedback path of a phase locked loop decreases lock time and prevents instability. A delay circuit may be used at any location along the feedback path of the phase locked loop.

Abstract: An electrical, magnetic or electromagnetic delay line self oscillator is described with a delay line arrangement, an oscillator control circuitry, and a frequency selection impedance connecting the delay line arrangement and the oscillator control circuitry and presenting an impedance to the delay line arrangement. The oscillator control circuitry includes an amplifier, a non linear amplitude control element (N-LACE) such as an active device with a negative differential conductance that provides an output amplitude has a negative second derivative with respect to an input signal, and a driver. The modal characteristics of electromagnetic delay lines can thus be exploited across a wide range of instrumentation applications, and a means is provided to enhance the achievable functionality and/or performance of the instrumentation without the need for expensive additional electrical hardware or electronics.

Abstract: The current-feedback operational amplifier-based sinusoidal oscillator provides oscillations based on a single external resistor and a single external capacitor, which exploit the internal parasitic components of the CFOA. The external resistor and external capacitor are passive, externally connected, and grounded.

Abstract: An oscillator is provided and includes a resistance unit, a capacitance unit, a first inverter and a second inverter. The resistance unit is serially connected between a first reference point and a second reference point. The capacitance unit is coupled between the first reference point and an output point, and includes capacitors. One terminal of each of the capacitors is coupled to the output point, and the other terminal of each of the capacitors is coupled to the first reference point or a reference ground according to a control signal. The input terminal of the first inverter is coupled to the first reference point, and the output terminal of the first inverter is coupled to the second reference point. The input terminal of the second inverter is coupled to the output terminal of the first inverter, and the output terminal of the second inverter is coupled to the output point.

Abstract: An adjustable-frequency oscillator, is formed by two looped systems, functioning at the same frequency but the signals are phase shifted by 90°. Each looped system includes a phase shift device, an active element providing the gain and a resonator having a fixed phase-frequency characteristic. As the phase shift in each loop is imperatively a whole multiple of 2?, the phase shift added in each loop by the phase shift device entails that each resonator introduces a complementary phase shift to comply with the oscillation criterion. This complementary phase shift is produced at a frequency defined by the resonator, this then defining the frequency of oscillation. The frequency is adjusted by two phase shift stages, which carry out the analogue multiplication of the signals coming from the two looped systems by control voltages and the summing of these products.

Abstract: An oscillating apparatus includes: a transfer gate including a P-channel transistor and a N-channel transistor; a first inverter for inverting an output signal of the transfer gate and outputting the inverted output signal of the transfer gate; a second inverter for inverting the output signal of the first inverter and outputting the inverted output signal of the first inverter; a third inverter for inverting the output signal of the first inverter and outputting the inverted output signal of the first inverter; a fourth inverter for inverting the output signal of the third inverter and outputting the inverted output signal of the third inverter to an input-terminal of the transfer gate; a first capacitor connected between an output-terminal of the transfer gate and an output-terminal of the second inverter; and a second capacitor connected between the output-terminal of the transfer gate and a reference potential node.

Abstract: A variable phase amplifier circuit is disclosed and its method of use in tuning devices having resonators. The variable phase amplifier receives an input differential signal pair. The input differential signal pair can be generated by a resonator device. The variable phase amplifier generates a modified differential signal pair in response to receiving the input differential signal pair. The variable phase amplifier provides a means to vary the phase of the modified differential signal pair with respect to the input differential signal pair, in an accurate and stable manner. If the modified differential signal pair with a phase shift introduced in it is fed back to the resonator device, the resonator will change its frequency of oscillation, where the new frequency of oscillation is a function of the phase of the modified differential signal pair.

Abstract: Nth-order voltage- and current-mode arbitrary phase shift oscillator structures are synthesized using n operational trans-conductance amplifiers (OTAs) or second-generation current controlled conveyors (CCCIIs) and n grounded capacitors. Linking up the I/O characteristics of the OTA and the CCCII and the reactance of grounded capacitor, the step of synthesis is first based on the algebraic analysis to oscillatory characteristic equations, resulting in a quadrature oscillator structure. Secondly, instead of the quadrature characteristic, to control each output signal with one another by a desired phase difference > or <90°, selectively superposing any of two fundamental OTA/CCCII-C sub-circuitries benefits the transformation of quadrature to arbitrary-phase-shift characteristic for the sinusoidal oscillator structure. Furthermore, several compensation schemes are presented for reducing the output parameter deviation due to the non-ideal effects.

Abstract: In one embodiment, an RC oscillator is provided. The oscillator includes a current generator circuit configured to generate a current. A capacitor is configured to be charged by the current. An inverter includes an input coupled to the capacitor. An output of the inverter goes high when a voltage across the capacitor reaches a threshold voltage of the inverter. A switch coupled to the output of the inverter and the capacitor is configured to close when the output of the inverter goes high. This discharges the capacitor. The output of the inverter goes low when the capacitor is discharged and the switch is opened. Clock generator logic is configured to receive the output of the inverter and generate a clock signal. The current is proportional to the threshold voltage of the inverter.

Abstract: According to an aspect of the invention, an oscillating circuit includes: a first MOS transistor having a first drain terminal and a first source terminal; a load element connected to the first drain terminal; and an oscillator connected to the first source terminal and outputs a fundamental signal and a harmonic signal, wherein the harmonic signal is amplified so that the amplified harmonic signal is output from the first drain terminal.

Abstract: A configurable PSRO measurement circuit is used to measure the frequency dependent capacitance of a target through silicon via (TSV) or other conductive structure. Measurements of the target structure are aided by using adjustable resistors and a de-embedding structure to measure the effects of parasitic capacitance, CPAR. Current is measured to both the device under test (DUT) and the de-embedding structure. From these measurements, the frequency dependent capacitance of the DUT is calculated.

Abstract: Generation of Terahertz range (300 GHz to 3 THz) frequencies is increasingly important for communication, imaging and spectroscopic systems, including concealed object detection. Apparatus and methods describe generating multiple phase signals which are phase-locked at a fundamental frequency, which are then interleaved into an output which is a multiple of the fundamental frequency. By way of example phase generators comprise cross-coupling transistors (e.g., NMOS) and twist coupling transistors (NMOS) for generating a desired number of phase-locked output phases. A rectifying interleaver comprising a transconductance stage and Class B amplifiers provides superimposition of the phases into an output signal. The invention allows frequency output to exceed the maximum frequency of oscillation of a given device technology, such as CMOS in which a 324 GHz VCO in 90 nm digital CMOS with 4 GHz tuning was realized.

Abstract: An oscillator that increases the accuracy of an output frequency, without using a charge pump, has an oscillation circuit, first and second voltage supply circuits, and a calibration value generation circuit. The first voltage supply circuit includes a resistor and a capacitor, the resistance and capacitance of which are determined so that a first voltage reaches a reference voltage within a reference time. The second voltage supply circuit includes first and second switching means, which perform switching when receiving pulse signals corresponding to the frequency of the oscillation circuit to raise the second voltage. A calibration value generation circuit provides the oscillation circuit with a calibration value that lowers the frequency when the second voltage reaches the reference voltage before the first voltage and raises the frequency when the second voltage reaches the reference voltage after the first voltage.

Abstract: Techniques for mitigating VCO pulling are described. In an aspect, VCO pulling may be mitigated by (i) injecting an oscillator signal, which is a version of a VCO signal from a VCO, into a transmitter and (ii) using coupling paths from the transmitter to the VCO to re-circulate the oscillator signal back to the VCO. In one design, an apparatus includes a VCO and a coupling circuit. The VCO generates a VCO signal at N times a desired output frequency. The coupling circuit receives an oscillator signal generated based on the VCO signal and injects the oscillator signal into a transmitter to mitigate pulling of the frequency of the VCO due to undesired coupling from the transmitter to the VCO. The apparatus may include a phase adjustment circuit that adjusts the phase of the oscillator signal and/or an amplitude adjustment circuit that adjusts the amplitude of the oscillator signal.

Abstract: There is provided a system for comparing the phase characteristics of three generated clock signals, each having a unique phase relationship with an original clock signal, with the original clock signal and to select a signal based on the proximity of the phase characteristic of the three signals to the original signal. The selection of a clock signal that most closely approximates the original significantly reduces lock time when attempting to synchronize an internal clock with an external clock. Additionally, there is provided a method for comparing three clock signals with an original clock signal and selecting from the three clock signals one that is approximately in phase with the original clock signal.

Abstract: A resonant circuit arrangement is for generating an amplitude-shift-keyed and/or phase-shift-keyed signal. The resonant circuit arrangement includes a capacitive storage element having a first terminal and a second terminal. The first terminal is electrically connectable to a control voltage and the second terminal is electrically connected to a reference potential. The resonant circuit arrangement also includes an inductive storage element having a third terminal and a fourth terminal, where the third terminal is electrically connectable to the reference potential, a first switch for electrically connecting the fourth terminal to the reference potential, a second switch for electrically connecting the fourth terminal and the first terminal, and a control unit for driving the first and second switches based on transmission data.

Abstract: Increasing loop gain is a common practice for reducing lock time of phase locked loops. Very high loop gains, however, often result in increasing the lock time or causing loop instability. For very high loop gains, delaying the feedback clock signal along the feedback path of a phase locked loop decreases lock time and prevents instability. A delay circuit may be used at any location along the feedback path of the phase locked loop.

Abstract: An embodiment for low power-consumption RC oscillator is disclosed. A voltage transforming unit transforms a power supply voltage to an internal voltage. A current mirroring unit is coupled to the voltage transforming unit and receives the internal voltage to provide constant two current outputs with different phases. A current charging/discharging unit includes first and second nodes to receive the two constant current outputs of the current mirroring unit, wherein first and second capacitors are coupled to the first and second nodes, respectively. The first and second capacitors are charged by the two constant current outputs. A voltage sensing and outputting unit is coupled to the first and second nodes, senses voltage levels of the first and second nodes and outputs clock signals when one of the sensed voltage levels is greater than a logic threshold. A pulse generating unit generates pulse signals in response to the clock signals.

Abstract: The present invention offers an object proximity detector and object position detector. The variation of frequency of an oscillator is used to detect the proximity of an object to a sensor plate. The dependence of the sensitivity of the detector on the area of the sensor plate is reduced by conducting the sensor plate to two capacitors in series. The conducting wire of the sensor plate can be flexible without causing error detection. In the sensor element of the sensor oscillator, a resistor is connected at one terminal of the sensor plate to form a high pass filter. A resistor and a capacitor are added to the sensor oscillator to form a low pass filter. The high pass filter is used to reduce the low frequency electromagnetic interference. The low pass filter is used to reduce the high frequency electromagnetic interference.

Abstract: An oscillator circuit has a crystal oscillator amplifier having only two clock input terminals, one being an input terminal and the other being an output terminal. The input terminal allows a user of the integrated circuit to choose between connecting a first clock signal generated from a crystal or a second clock signal generated by a non-crystal source to the input terminal. Control circuitry has a capacitor coupled in parallel with a transistor. Both are coupled in series with a resistive device at an output of the control circuitry to provide a control signal. Clock generation circuitry coupled to the crystal oscillator amplifier provides an oscillating output signal in response to an enable signal. In one form a comparator circuit provides the oscillating output signal. The control signal is used to ensure that inputs to the comparator circuit repeatedly cross each other over time.

Abstract: Provided is a colpitts quadrature voltage controlled oscillator capable of obtaining quadrature orthogonal signals using a quadrature combination between a base and a collector of each transistor, without using an additional circuit such as a coupled transistor, a coupled transformer, a multiphase RC filter, etc. Accordingly, since nonlinearity, increased phase noise, a decrease in the Q-factor of an LC resonator, and increased power consumption can be avoided, a colpitts quadrature voltage controlled oscillator that has low phase noise, low electric power consumption, and a compact size can be implemented.

Abstract: An oscillator includes a first comparator circuit, a second comparator circuit, an oscillation signal generator circuit, and a frequency voltage generator circuit. The first comparator circuit generates a first pulse when a frequency voltage reaches a first reference voltage, and the second comparator circuit generates a second pulse when the frequency voltage reaches a second reference voltage. The oscillation signal generator circuit generates an oscillation signal by latching a first voltage in response to the first pulse and latching a second voltage in response to the second pulse. The frequency voltage generator circuit raises or lowers the frequency voltage in response to the oscillation signal. The driving capability of the first comparator circuit is reduced at the latching of the first voltage and is restored at the latching of the second voltage.