Abstract: A method in a circuit comprises providing a first clock by a resistor-capacitor (RC) oscillator; demodulating a plurality of input signals to form a plurality of demodulated input signals; discriminating frequency ranges of the plurality of demodulated input signals according to the first clock; determining whether a first predetermined number of consecutive demodulated input signals among the plurality of demodulated input signals fall into a first predetermined frequency range; triggering a crystal oscillator to provide a second clock to calibrate the first clock if the first predetermined number of consecutive input signals fall into the first predetermined frequency range.

Abstract: An oscillator that includes a first source current leg and first sink current leg to source current and sink current, respectively, during a startup mode of oscillator operation. The oscillator includes a second source current leg and a second sink current leg to source current and sink current, respectively, during a second mode of oscillator operation.

Abstract: A shear-mode quartz resonator designed to mechanically oscillate at a predetermined frequency and electronic circuits for inhibiting oscillation of the shear-mode quartz resonator in response to externally applied mechanical forces which otherwise induce mechanical vibration of the shear-mode quartz resonator at frequencies significantly less than the predetermined frequency. The shear-mode quartz resonator includes a cantilevered quartz beam having relatively large metallic electrodes attached on opposite sides thereof, the relatively large metallic electrodes, in use, being coupled to an external oscillator circuit. The beam also has relatively smaller sense and rebalance electrodes attached on the same opposite sides of said quartz beam as said relatively large metallic electrodes. The relatively smaller sense and rebalance electrodes being coupled, in use, with said electronic circuits for inhibiting oscillation of the shear-mode quartz resonator in response to externally applied mechanical forces.

Abstract: An oscillator formed from low cost discrete semiconductors and passive devices creates a linear periodic ramp of constant frequency with ramp slope based on an external voltage signal. Parameters are stable over a wide range of temperatures and variations of transistor parameters that normally degrade in extreme environments. The oscillator period can be phase and frequency synchronized to an external clock source over a wide range of frequencies. The oscillator ramp generator phase can be synchronized on a cycle by cycle basis for incorporation in power converters employing spread spectral EMI reduction techniques, multi-converter systems employing clock interleaving for distribution bus filter optimization, and resonant mode converters employing zero voltage switching techniques. Oscillator ramp rate is independent of frequency and can be synchronized to DC (inhibit) for use in ultra low power burst mode power conversion.

Abstract: A current-feedback operational-amplifier Based Relaxation oscillator provides oscillation based on a current feedback operation amplifier and two external resistors which exhibit a low output impedance terminal. This current-feedback operational-amplifier Based oscillator is used as a component for a capacitive, resistive and capacitive-resistive sensor electronic interfacing circuit.

Abstract: Disclosed is a method for generating an oscillating signal and an oscillator circuit.

Abstract: The present invention is directed to an oscillator circuit comprising an oscillator input for providing an input signal, a first integrator circuit comprising a first integrator capacitor and a first integrator output, a comparator, a discharge circuit for discharging said first integrator capacitor once per cycle of said oscillator circuit, and an oscillator output for providing an output signal, wherein said oscillator circuit further comprises a second integrator circuit comprising a second integrator capacitor and a second integrator output, and wherein said oscillator circuit is arranged for allowing said input signal to be subsequently integrated by said first and second integrator circuit in an alternating manner, and for providing said integrated output signal of said first and second integrator circuit subsequently to said comparator in said alternating manner.

Abstract: A relaxation oscillator includes a capacitor connected to a comparator input, current sources switched to supply power to the capacitor based on an output of the comparator, and a duplicate integrator shifting a voltage on the capacitor to offset a propagation delay through the comparator. The duplicate integrator includes current sources and a capacitor matching and switched in tandem with those within the relaxation oscillator, plus an additional current source, and is selectively switched into connection with the comparator input. By canceling the comparator propagation delay, the oscillator output frequency can be stably controlled through selection of resistive and capacitive values, using cheaper technology and tolerating large temperature, voltage and process variations.

Abstract: The relaxation oscillator includes a comparator and a latch. The comparator includes a comparator output and a comparator input that is configured to receive a first input signal in response to a first signal and configured to receive a second input signal in response to a second signal. The latch includes a latch-set input that is configured to be coupled to the comparator output in response to a third signal, a latch-reset input that is configured to be coupled to the comparator output in response to a fourth signal and a latch output that is configured to output the second signal. The relaxation oscillator is configured to achieve an approximately fifty percent duty cycle without requiring the use of a second comparator.

Abstract: Apparatus includes a single-pin input interface, which is operative to sense a voltage across a capacitor of a Resistor-Capacitor (RC) network in which the capacitor is repetitively charging and discharging so that the voltage oscillates as a function of time. A measurement circuit is coupled to measure time durations in which the capacitor is charging and in which the sensed voltage lies between first and second predefined thresholds. A clock generation circuit is coupled to generate an output clock signal having a frequency, and to adjust the frequency responsively to the measured time durations.

Abstract: In the many microelectronics applications, delays present in circuitry can affect both the design and the function of the circuitry. One example of delays impacting the function of a circuit is a relaxation oscillator, where delays present in comparator circuits and latches can cause its frequency to vary beyond desired ranges. Here, a relaxation circuit with delay compensation is described.

Abstract: In one embodiment, an oscillator circuit is configured to oscillate at a base frequency. The oscillator is configured to receive a synchronization signal and restart a period of the oscillator signal responsively to the synchronization signal.

Abstract: An oscillator circuit providing quadrature outputs and enabling instantaneous control over phase, frequency and amplitude of the output waveforms is disclosed. In one embodiment, the oscillator circuit comprises an oscillation loop, at least one capacitor switching circuit coupled to the oscillation loop, and a synchronization signal having an output coupled to the at least one capacitor switching circuit. The synchronization signal may be derived internally from the oscillation loop or externally from an external oscillator.

Abstract: An oscillator structure has a sync signal processor with an input interface for an external clock based sync signal and an output interface for a duty cycle indication signal depending on a signal property of the sync signal and an oscillator with an input interface for the duty cycle indication signal and the sync signal and an output interface for an oscillation signal synchronized with the external clock and having a duty cycle adjusted according to the duty cycle indication signal.

Abstract: A frequency jittering circuit modulates a hysteretic band of an oscillator such that the clock generated by the oscillator has a jitter frequency, and thus a switching mode power supply operative on the clock will have a jittering switching frequency.

Abstract: The present invention relates to an oscillator outputting two triangle waves having the same amplitude and whose phases are inverted; and a pulse width modulator using the oscillator. A capacitor 3 is charged or discharged by a charge pump circuit 2 controlled by a Schmitt circuit 1, and a voltage integrated by a two-output differential amplification circuit 6 is positively fed back to the input of the Schmitt circuit 1 to output two triangle waves having the same amplitude and whose phases are inverted. Since the output stage is composed of a differential amplification circuit, the circuit has low output impedance and is protected from wiring capacity and connected input capacity, and since integral operation is caused to be performed by the differential amplification circuit, the distortion in the waveform of the triangle waves can be prevented.

Abstract: An oscillator circuit that generates an oscillation signal is provided. The oscillator circuit includes an oscillator that generates the oscillation signal based on positive feedback of a signal, a synchronization signal generating section that generates a compulsory synchronization signal having an edge that (i) crosses a zero cross point at an ideal timing of an edge of the oscillation signal every predetermined number of cycles of the oscillation signal and (ii) has a gradient in the same direction as the edge of the oscillation signal, and a combining section that injects the compulsory synchronization signal into a positive feedback path of the oscillator.

Abstract: A controlled endpoint sawtooth waveform generator and methodology is implemented by a circuit that uses charge sharing between capacitors to produce a sawtooth having one or both endpoints that are suspended between the power supply rail and ground. The circuit may comprise a timing capacitor to which a charging source is coupled, and a switched capacitor coupled to the timing capacitor through a first controlled switch and to a source of switched capacitor reference voltage through a second controlled switch. The first and second controlled switches are responsive to a control signal, that may be internally or externally provided, for mutually exclusive switch operation. An output sawtooth thereby is produced having one endpoint determined by a fixed voltage source and the other endpoint in accord with the capacitance ratio of the timing and switched capacitors.

Abstract: An oscillator of a semiconductor memory device, wherein a reference voltage that flexibly shifts according to the shift in a power supply voltage is generated, and a reference clock is generated using the reference voltage. It is thus possible to generate the reference clock having a constant cycle regardless of the shift in the power supply voltage which can keep constant the duration period of internal control signals of devices, such as a timer and a pump circuit, which are synchronized to the reference clock.

Abstract: An integrated circuit includes an oscillator circuit, where a frequency of an oscillator output signal provided by the oscillator circuit is adjustable by either coupling a resistor to an input pin, or by applying an external clock signal to the input pin. The oscillator circuit includes a comparator, a follower, a current-controlled oscillator, and a switch circuit. The switch circuit is coupled between the input pin and a node that is coupled to the current-controlled oscillator. Also, the follower is arranged to cause the voltage at the node to be at a pre-defined voltage unless the voltage at the node is overdriven by an external clock signal. The comparator circuit is arranged to determine whether the signal at the input pin is a clock signal. If it is determined that the signal at the input pin is a clock signal, the switch circuit is opened.

Abstract: A low power oscillator circuit for a self-refresh timer in a memory array is disclosed. When a voltage (V1) of a comparison node (N1) exceeds a first reference voltage (Vref1), a differential amplifier (101) in an oscillator (1) causes a pulse generator (110) to output a pulse. A charge/discharge circuit (105) discharges the comparison node (N1) in response to pulse. In this event, a control circuit (4) disables a first control signal (CT1) to halt operation of the differential amplifier (101). When the voltage (V1) exceeds a second reference voltage (Vref2) equivalent to the sum of threshold voltages of a discharge circuit (43) in consequence of gradually charging the comparison node (N1) by the charge/discharge circuit (105) after it was discharged, the control circuit (4) activates the first control signal (CT1) to operate the differential amplifier (101).

Abstract: A current controlled oscillator is described comprising: a latch comprising two logic inverters to maintain a switch state for a determined duration, the latch having two complementary output voltages; a differential switch pair comprising a first and a second switch controlled by the two complementary output voltages respectively to steer a control current to a first and a second node alternatively; a third and fourth switch driven on by a high level voltage at one of the first and second node to set and reset the latch; and a fifth and sixth switch controlled by the two complementary output voltages respectively to pull down voltages at the first and second node alternatively, wherein the first and fifth switch are controlled by a same control signal and the second and sixth switch are controlled by a same control signal; whereby the frequency of switching is a function of the capacitance of the first and second node and the control current.

Abstract: A demodulator circuit (10) includes an oscillator (12) and an injection circuit (14). An Automatic Frequency Control (AFC) signal adjusts the tail current of a current source (28) provided in the oscillator (12) and the tail current of a current source (44) provided in the injection circuit (14). A phase detector (16) compares the phase of the signal generated by the oscillator (12) with the phase of the injected input signal. The phase detector (16) generates an output signal V0 having a value of zero when the input signal is in quadrature with the signal generated by the oscillator (12), but generates a non-zero signal that is used to adjust the AFC signal when the input signal and the signal generated by the oscillator (12) are not in quadrature.

Abstract: An oscillator circuit that adjusts the oscillation voltage such that the voltage oscillates in a uniform manner independent of changes to frequency. Slope compensation is derived from the oscillation voltage. The adjustment is implemented by using a window comparator to establish a range of operation of the oscillation voltage. When the oscillation voltage is outside the range of operation, the window comparator instructs a counter circuit to either count up or count down, depending on the value of the oscillation voltage relative to the range. This counting then is used to adjust the amount of current which charges the capacitor. Thus, when the peak voltage is too low, the amount of current is adjusted upward. When the peak voltage is too high, the amount of current is adjusted downward. In this fashion, the oscillation voltage is maintained at a substantially uniform value, while the frequency is synchronized to an external clock signal.

Abstract: An oscillator circuit produces first and second oscillating logic signals that are of a same frequency and are non-overlapping in a first logic state. This oscillator includes a flip-flop circuit to produce third and fourth oscillating logic signals of opposite polarities, this flip-flop circuit being driven by first and second driving logic signals. First and second logic gates receive the third and fourth logic signals and produce the first and second logic signals, the logic state transitions in the first and second logic signals being produced as a function of the logic state transitions of the third and fourth logic signals. The first and second logic gates are organized so as to introduce a delay into the transitions from a second logic state to the first logic state, in the first and second logic signals, with respect to transitions in the third and fourth logic signals.

Abstract: In a method of calibration of a voltage controlled oscillator (VCO), the VCO (100) provides an output signal which is used to drive a dividing oscillator (10) such as a relaxation oscillator (RO). The RO has at least two states, one in which the RO provides an output signal which has a first frequency that is related to the VCO output signal by a first ratio (e.g. 1/N) and one in which the relaxation oscillator provides a RO output signal which has a second frequency that is related to the VCO output signal by a second ratio (e.g. 1/(N+1)). By measuring the first and second frequencies (and knowing the relationship between the first and second ratios), the VCO frequency is calculated and stored (110). Several VCO frequencies can be calculated and stored for several applied voltages. As a result the VCO can be driven to any selected frequency in the calibrated range and can be used to provide an injection frequency for a radio.

Abstract: A dual-multivibrator circuit using a pair of mutually triggering multivibrator sections is connected to operate in a free-running mode when no external synchronization signal is applied to the circuit input, and in synchronism with a master pulse train of substantially the same pulse repetition rate when such a master pulse train is applied to the circuit input.

Abstract: An improved timer oscillation circuit capable of synchronizing an oscillation frequency, which is determined by a time constant of a resistance and a capacitance, to a clock signal, which includes a first voltage comparator, controlled by a clock signal, for charging a first voltage on a second capacitance and for outputting a result obtained by comparing the charged voltage on the second capacitance and a voltage from the first capacitance; and a second voltage comparator, controlled by the clock signal, for charging a voltage outputted from the first capacitance on a third capacitance and for outputting a result by comparing the charged voltage and an electric potential of the second voltage, so that it can be advantageously adopted to a digital circuit by outputting an oscillation signal having a cycle determined by a time constant of a resistance and a capacitance and which is synchronized to a clock signal.

Abstract: An oscillation circuit includes inversion circuits and delay circuits wherein at least one of the inversion circuits includes multiple inverters connected in series to one another and wherein the driving capability of a first stage inverter inserted immediately after the delay circuit at the input of the oscillation circuit is lower than that of a final stage inverter inserted immediately before the delay circuit at the output of the oscillation circuit.

Abstract: An integrated voltage controlled oscillator (VCO) circuit which utilizes the relative capacitance ratio between capacitors and the relative resistance ratio between resistors in an integrated circuit (IC) to output a signal having a predictable frequency for a given control signal voltage. The VCO output frequency will not vary more than 3.0% from one IC chip implementing the VCO circuit, to the next. This low variance between IC chips is derived from the phenomenon whereby the respective ratios of capacitance and resistance between capacitors and resistors in the IC will not vary more than .+-.1.5% from the ratios of like capacitors and resistors on other IC chips. The integrated VCO circuit includes a control signal subcircuit, integrator subcircuit, filter subcircuit, and comparator unit subcircuit.

Abstract: An integrated oscillator includes an amplifier having first and second voltage inputs, and first and second current outputs, and a current mirror having an input coupled to the second current output of the amplifier and an output coupled to the first current output of the amplifier. The output of the current mirror and the first current output of the amplifier are coupled through a bonding pad to an external capacitor. A first comparator has a first input coupled to the first current output of the amplifier and a second input for receiving a first threshold voltage, and a second comparator has a first input coupled to the first current output of the amplifier and a second input for receiving a second threshold voltage. A flip-flop has a first input coupled to the output of the first comparator, a second input, and an output coupled to the second voltage input of the amplifier.

Abstract: A voltage controlled triggered oscillator includes a NAND gate and a set of series connected triggerable delay circuits, the output of the NAND gate being fed back to one of its inputs through the delay circuits. A trigger signal is applied to another input of the NAND gate and to triggering inputs of the delay circuits. When the trigger signal is asserted, each delay circuit produces an output signal of state which tracks the state of its input signal but with a predetermined delay so that the NAND gate output oscillates with a frequency determined by the delay times of the delay circuits and the propagation time of the NAND gate. When the trigger signal is deasserted the NAND gate output is terminated and each delay circuit drives its output signal high regardless of the state of its input signal so that the oscillator may be rapidly retriggered.

Abstract: This high accuracy, RC oscillator, particularly for monitors, has different switch-over thresholds independent from such variable parameters as the saturating voltage of transistors, and has a high operating frequency. The oscillator comprises a capacitor having an output terminal, a capacitor power current source, and a control section. The control section is composed of a plurality of differential stages sharing a common input and each having an input connected to a different switch-over threshold. The control section further comprises a switch-over drive stage connected to the oscillator output terminal and to an input terminal thereof for controlling activation and deactivation of the different differential stages (and hence, of the respective associated thresholds) according to the signal present at the output and input terminals of the oscillator.

Abstract: There are three oscillator circuits which oscillate at different frequencies, each oscillator circuit including a gate having an input and an output. The output of the first gate is connected to an inverter and the input of the second gate. The output of the inverter is connected to the input of the third gate. The output of the second and third gates is connected across a piezoelectric transducer to produce a warble sound.

Abstract: A current to frequency converter comprising a current source, for example a photocell, a voltage to frequency converter, an integrator in the feedback loop of the converter, the current source being connected to the summing junction of the converter and integrator such that the frequency of output pulses from the converter is directly proportional to the magnitude of current injected from the converter to the summing junction, and a controlled circuit for attenuating the current injected from the converter to the summing junction to increase the frequency of output pulses. The controlled attenuating circuit includes a transistor switching arrangement for introducing increased resistance in the path for current injected from the converter to the summing junction in response to the presence of a control signal.

Abstract: An oscillation circuit having a reference voltage circuit for forming a reference voltage by dividing a power supply voltage. The reference voltage circuit supplies the reference voltage to one of the input terminals of the comparing circuit. A charge/discharge voltage is supplied from a junction between a transmission gate circuit and a CR circuit to the other input terminal of the comparing circuit. The comparing circuit compares the charge/discharge voltage with the reference voltage to produce pulse signals.

Abstract: A phase-lock system including an oscillator providing a switching output that continuously switches between first and second states, a trigger circuit for inducing switching of the oscillator, a sensing circuit monitoring the switching output and providing an anticipating indication of an imminent switching thereof from the first to the second state, and a primary voltage source providing a variable voltage that periodically varies from and returns to a given voltage level. Also included is a detector circuit monitoring the variable voltage and detecting the presence of the given voltage level and a synchronizing circuit responsive to the sensing and detector circuits and providing an input to the trigger circuit, the synchronizing circuit being operative to cause switching of the oscillator in response to the simultaneous provision of the anticipating indication by the sensing circuit and detection of the given level by the detector circuit.

Abstract: A test pattern generator comprises vertical line pulse generating circuit (20) for generating a first pulse train (VL) and a second pulse train (Hi), the first pulse train being used to display vertical lines on a raster scan display apparatus and including, between successive pulses of the second pulse train, a number of pulses equal to the number of vertical lines. A horizontal sync pulse generating circuit (30) receives the second pulse train and generating a horizontal sync pulse train (M sync). A vertical blanking and sync pulse generating circuit (40, 42, 44, 46) is connected to the horizontal sync pulse generating circuit for generating a vertical sync pulse train (V sync) and a vertical blanking pulse train (Vb), and a horizontal line pulse generating circuit (50) generates a horizontal line pulse train (HL), used to display horizontal lines, in response to the horizontal sync pulse train and the vertical blanking pulse train.

Abstract: An oscillator unit having a charge storage device periodically rapidly charged through a small resistor and slowly discharged through a large resistor under control of a comparator for producing an oscillatory output and a switch actuatable by means of a frequency controlled zero-crossing multiplier to selectively discharge the storage device and thereby repeatedly resynchronize the oscillator unit with the frequency input to the multiplier.

Abstract: A horizontal oscillator for a CRT device runs at a rate higher than the line rate, and has a wide lock-in range. The horizontal sync signal is delayed in an adjustable monostable circuit and coupled to the oscillator for allowing a centering adjustment of one full line. The oscillator output signal is coupled through a discharge circuit for rapid discharge of the subsequent circuit in the CRT device as desired.

Abstract: A self-starting, non-latching, pulse modulator which will function as an analog divider of first and second input quantities, or as a linear pulse period modulator responsive to one of the quantities, or as a linear pulse frequency modulator responsive to the other of the quantities, depending upon how the first and second input quantities are controlled. The first input quantity is connected to charge a capacitor. The second input quantity is compared in a first comparator with the voltage across the capacitor. A second comparator compares the voltage across the capacitor with a reference voltage. The outputs of the first and second comparators are connected, respectively, to the first and second inputs of a flip-flop which has its first output connected to a monostable multivibrator. The second output of the flip-flop and the output of the monostable multivibrator are both connected so that either one can momentarily activate a discharge circuit for discharging the capacitor.

Abstract: A vertical sawtooth generator adaptable for integrated circuit application self-oscillates under control of a latch circuit. A circuit controls the linearity of the charging capacitor ramp voltage. High frequency components of the recurrent ramp occurring due to the retrace discharge current are reduced by controlling the discharge currents. The ramp rate is controlled by a single resistor external to an integrated circuit.

Abstract: A voltage controlled oscillator having a substantially linear output over a wide range is used in video games to address picture memory means to thereby determine the size of the objects displayed on a raster type video screen. The oscillator produces an output signal having a frequency determined by an analog input voltage which is proportional to the desired size of the objects. The oscillator includes a variable current source controlled by the analog input voltage which stores charge in a capacitor. A pair of AND gates sink charge from the capacitor as determined by threshold means which senses the stored voltage. The periodic change in the output of the threshold means constitutes the output signal.

Abstract: An oscillator for producing rectangular pulses comprises a Schmitt trigger controlled by an R.C. element connected in series, a constant current source for charging up the capacitor and a current image circuit for ensuring that the discharge current of the capacitor is consistent with its charging current.

Abstract: A clock circuit comprising a synchronizable voltage controlled oscillator in combination with a programmable address means, which address means is adjusted commensurate with the acoustic velocity of the workpiece, provides clock pulses from the oscillator having a stable and accurate acoustic velocity dependent frequency. An entrant surface responsive electrical signal responsive to an ultrasonic search signal entering the workpiece is also provided to the clock circuit for assuring that the clock pulses are synchronized with the receipt of the electrical signal.

Abstract: A vertical deflection circuit used in television receivers, comprising a free-running oscillator capable of synchronous oscillation triggered by a vertical synchronizing signal separated from a composite synchronizing signal is disclosed. The vertical deflection circuit has a switch means which operates under synchronous control by the vertical synchronizing pulse and prevents the application of a vertical trigger signal to the free-running oscillator at least for the period from the time at which the free-running oscillator has been triggered to the time corresponding to the end of the vertical synchronizing pulse period of the composite synchronizing signal.

Abstract: An oscillating apparatus allowing for synchronization to an external sinusoidal source, and in which a unidirectional element is so located that the oscillating device may be replaced without the necessity of altering circuit elements to maintained synchronization and the desired nominal frequency of operation.