Abstract: Circuits and processes for locking a voltage-controlled oscillator (VCO) at a high frequency signal are described. A circuit may include an adjustable current converter (ACC), coupled at an input terminal to a power source, operable to output a control signal (VC) at an output terminal. A first switch may be coupled to the ACC and to the VCO. The VCO, when in an “ON” state, receives the control signal and outputs a high frequency signal (VHF). A digital filter may be coupled to the VCO and operable to receive the VHF. Based on the VHF, the digital filter generates a data signal having a data value. The circuit may also include a digital-to-analog converter (DAC) operable to receive the data signal and, based on the data value, output an adjustment signal to the ACC. The ACC may adjust the control signal based on the adjustment signal received from the DAC.

Abstract: An electrical device (100) that comprises at least one signal filter (104) comprising a plurality of mechanical resonators (106 108, 110) in a substrate (102) and at least one further mechanical resonator (112) in the substrate (102) configured to oscillate at a reference frequency of an oscillator signal. An electrical system (300) comprising an electrical oscillator (306) a transceiver (302) and an antenna (310), and an electrical device (100). A method (1300) for providing an electrical device (100).

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal, wherein the signal propagation circuit includes: a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit; and a fifth inverted signal output circuit including an input terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.

Abstract: An apparatus for generating a steady state positive voltage (PVS) signal and a steady state negative voltage (NVS) signal is presented. The apparatus includes a bias signal generation module for generating a steady state reference voltage signal (RVS) based on a varying supply voltage signal (VDD), the RVS having a voltage level less than the PVS. The apparatus further includes a positive signal generation module (PSGM) generating the PVS, the PSGM including a first capacitor, the PSGM employing the first capacitor to generate a portion of the PVS based on the RVS. The apparatus further includes a negative signal generation module (NSGM) generating the NVS, the NSGM including a second capacitor, the NSGM employing the second capacitor to generate a portion of the NVS based on the RVS.

Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.

Abstract: Systems, methods, and devices of the present disclosure relate, generally, to compensating for frequency error of a reference signal supplied to a clock-tracking-loop due to temperature. Error characteristics of a crystal oscillator that supplies the reference signal are used to compensate for possible frequency errors. Other systems, methods and devices are disclosed.

Abstract: Techniques are disclosed relating to rapidly downshifting the output frequency of an oscillator. In some embodiments, the oscillator is configured to operate in a closed-loop mode in which negative feedback is used to maintain a particular output frequency (e.g., in a phase-locked loop (PLL)). In some embodiments, the negative feedback loop is configured to maintain the output of the oscillator at a particular frequency based on a reference clock signal and the output of the oscillator. The nature of a negative feedback loop may render rapid frequency changes difficult, e.g., because of corrections by the loop. Therefore, in some embodiments, the loop is configured to switch to an open-loop mode in which a control input to the oscillator is fixed. In some embodiments, the loop switches to open-loop mode in response to a trigger signal and control circuitry forces the oscillator to a new target frequency.

Abstract: A circuit includes multiple stages cascaded in a ring topology such that each stage has a preceding stage, a succeeding stage, an alternate-preceding stage, and an alternate-succeeding stage. Each stage includes a MOS transistor of a first type, a MOS transistor of a second type and a resistor. The MOS transistor of a first type receives a first input that is output from the preceding stage, and outputs a second output to the alternate-preceding stage. The MOS transistor of a second type receives a second input that is output from the alternate-succeeding stage, and outputs a first output to the succeeding stage. The resistor provides coupling and level-shifting between the first output and the second output.

Abstract: A circuit may comprise a first node, a ring oscillator, a regulator, and a Kvcc compensation circuit. The first node may be a supply node to provide a supply voltage for the circuit. The ring oscillator may be formed from inverters. The regulator may use a single transistor between the first node and a second node for powering the oscillator. The K compensation circuit may be used to provide to the oscillator a variable capacitive load that is dependent on the supply at the first supply node, and it may drag oscillator frequency down when the first node supply goes up.

Abstract: Apparatus and associated methods relate to automatically generating a data structure representation of an on-chip inductive-capacitive (LC) tank circuit by determining parasitic inductances in each of the segments of conductive paths that connect a main inductor to one or more selectable VCO components such as capacitors and varactors, for example. In an illustrative example, one or more of the selectable VCO components may be arranged, when selected, to form a parallel resonant LC tank with the main inductor. A method may include defining nodes ai terminating each of the segments along the conductive paths between the main inductor terminals and a drive circuit. By modelling the paths as multi-port inductors and transformers, resonant frequency of the VCO may be more accurately predicted by simulation.

Abstract: A start-up circuit for a ring current-controlled oscillator (CCO) includes a replica CCO current generator, a replica ring CCO, and a buffer. The ring CCO is connected to a CCO driver and the buffer. The CCO driver generates a CCO current based on a reference current. The ring CCO generates a CCO output voltage at a first oscillating frequency based on the CCO current. The replica CCO current generator generates a replica CCO current based on a reference voltage. The replica ring CCO generates a replica CCO output voltage at a second oscillating frequency based on the replica CCO current. The buffer provides a first current to the ring CCO when the first oscillating frequency is lower than a desired oscillating frequency, and drains a second current from the ring CCO when the first oscillating frequency is greater than the desired oscillating frequency.

Abstract: The present invention provides an oscillator circuit and associated oscillator device. The oscillator circuit comprises a negative-temperature-coefficient (NTC) bias current generating circuit and a set of oscillator sub-block circuits. The NTC bias current generating circuit is coupled between a supply voltage and a ground voltage, and is arranged to generate at least one NTC bias current. The set of oscillator sub-block circuits are coupled to each other to form an oscillator. Each oscillator sub-block circuit of the set of oscillator sub-block circuits comprises a plurality of transistors coupled between the supply voltage and a node within the NTC bias current generating circuit, wherein the NTC bias current generating circuit and the aforementioned each oscillator sub-block circuit share at least one transistor in the plurality of transistors.

Abstract: Techniques are disclosed relating to rapidly downshifting the output frequency of an oscillator. In some embodiments, the oscillator is configured to operate in a closed-loop mode in which negative feedback is used to maintain a particular output frequency (e.g., in a phase-locked loop (PLL)). In some embodiments, the negative feedback loop is configured to maintain the output of the oscillator at a particular frequency based on a reference clock signal and the output of the oscillator. The nature of a negative feedback loop may render rapid frequency changes difficult, e.g., because of corrections by the loop. Therefore, in some embodiments, the loop is configured to switch to an open-loop mode in which a control input to the oscillator is fixed. In some embodiments, the loop switches to open-loop mode in response to a trigger signal and control circuitry forces the oscillator to a new target frequency.

Abstract: An apparatus for generating a steady state positive voltage (PVS) signal and a steady state negative voltage (NVS) signal is presented. The apparatus includes a bias signal generation module for generating a steady state reference voltage signal (RVS) based on a varying supply voltage signal (VDD), the RVS having a voltage level less than the PVS. The apparatus further includes a positive signal generation module (PSGM) generating the PVS, the PSGM including a first capacitor, the PSGM employing the first capacitor to generate a portion of the PVS based on the RVS. The apparatus further includes a negative signal generation module (NSGM) generating the NVS, the NSGM including a second capacitor, the NSGM employing the second capacitor to generate a portion of the NVS based on the RVS.

Abstract: The invention relates to an apparatus for extracorporeal removal of protein-bound toxins from blood plasma comprising a first line device, a second line device, a third line device and a fourth line device, a dialyzer or hemofilter arranged between the first line device and the second line device and/or an adsorber, means for generating a field, at least partially surrounding the first line device and/or the dialyzer or hemofilter and/or the adsorber, a controllable fluid conveyance device arranged in the first line device and/or the second line device, and at least one controllable body fluid conveyance unit arranged in the third line device and/or the fourth line device, a filter, wherein the permeate side of the filter is connected to the first line device and the second line device, and the side of the filter to be dialyzed is connected at its inlet to the third line device, which can be connected to a patient and is connected at its outlet to the fourth line device which can be connected to the patient,

Abstract: An oscillator includes: an oscillation stage circuit that is connected between a first electrode and a second electrode of a resonator and performs an oscillation operation; a variable capacitance element that is connected to the first or second electrode of the resonator and adjusts an oscillation frequency; a bandgap reference circuit that generates a reference voltage having magnitude, which changes depending on the temperature, by using a resistor inserted in a current path through which a current having magnitude, which changes depending on the temperature flows; and a bias current generating circuit that generates a bias current of the oscillation stage circuit based on the reference voltage, and that, thereby, reduces a change in the oscillation frequency due to the temperature dependence of the impedance of the resonator or the temperature dependence of the sensitivity of the variable capacitance element.

Abstract: An oscillator system for an integrated circuit includes a first oscillator circuit, a second oscillator circuit, and calibration system. During a sampling routine, the calibration system is used to determine a sampled value based on a comparison of the output of the second oscillator and an external clock signal. The sampled value is stored in a memory. During a calibration routine, the calibration system determines a comparison value based on a comparison of the output of the second oscillator circuit and the output of the first oscillator circuit. The calibration circuit compares the comparison value with the sampled value to generate a tuning value to tune the frequency of the first oscillator circuit.

Abstract: An oscillator system includes a voltage controlled oscillator (VCO) circuit. The VCO circuit includes an output for providing an oscillation signal and input to receive a voltage that controls the frequency of the oscillation signal. The oscillator system includes a frequency to voltage circuit that receives the oscillation signal and produces a voltage that is dependent upon the frequency of the oscillation signal. The oscillator system includes a comparison circuit including an amplifier. The amplifier includes an inverting input, a non inverting input, and an output. During a first phase of the comparison circuit, the non inverting input receives a reference voltage and the inverting input is coupled to the output of the amplifier via a switch and to a capacitor wherein the capacitor samples the voltage of the output.

Abstract: Techniques are disclosed relating to rapidly downshifting the output frequency of an oscillator. In some embodiments, the oscillator is configured to operate in a closed-loop mode in which negative feedback is used to maintain a particular output frequency (e.g., in a phase-locked loop (PLL)). In some embodiments, the negative feedback loop is configured to maintain the output of the oscillator at a particular frequency based on a reference clock signal and the output of the oscillator. The nature of a negative feedback loop may render rapid frequency changes difficult, e.g., because of corrections by the loop. Therefore, in some embodiments, the loop is configured to switch to an open-loop mode in which a control input to the oscillator is fixed. In some embodiments, the loop switches to open-loop mode in response to a trigger signal and control circuitry forces the oscillator to a new target frequency.

Abstract: A device and method can be used to manage the operation of a ring oscillator circuit. A master oscillator circuit generates a master supply voltage. The master supply voltage associated with a stable oscillation rate of the master oscillator circuit. The master oscillator circuit is supplied with current and is structurally identical to the ring oscillator circuit. A capacitive circuit is loaded with a load voltage originating from the master supply voltage. In response to a control signal, the ring oscillator circuit is supplied with a current controlled by a voltage delivered by the capacitive circuit, in such a way as to provide a stable oscillation rate for the ring oscillator circuit.

Abstract: Embodiments of signal bias generators and regulators are described generally herein. Other embodiments may be described and claimed.

Abstract: A circuit may comprise a first node, a ring oscillator, a regulator, and a Kvcc compensation circuit. The first node may be a supply node to provide a supply voltage for the circuit. The ring oscillator may be formed from inverters. The regulator may use a single transistor between the first node and a second node for powering the oscillator. The K compensation circuit may be used to provide to the oscillator a variable capacitive load that is dependent on the supply at the first supply node, and it may drag oscillator frequency down when the first node supply goes up.

Abstract: The invention relates to a method for operating a mechanical resonator in an electronic oscillator, comprising determining a state space description of the resonator, in which state variables are the mass, the stiffness or dimensions of components used in the crystal resonator; providing a table with frequency correction factors as a function of a state space of a resonator; finding a frequency correction factor corresponding to the determined state space; and multiplying the output frequency of the resonator with the correction factor, and to an electronic oscillator, comprising a mechanical resonator, wherein an output frequency of the oscillator is multiplied by a frequency correction factor, the frequency correction factor being obtained from determination of the state variables of the resonator, in particular dominant mechanical state variables.

Abstract: It is an object of the present invention to solve a problem that malfunction of communication is generated by varying a frequency of a clock due to noise from outside in a case where there is no supplied signal in a circuit which performs negative feedback control so that the supplied signal and the feedback signal can maintain a fixed phase relationship between the signals. The present invention provides a configuration including a PLL circuit and an oscillator circuit, where a switch for switching an output between a signal from the PLL circuit and a signal from the oscillator circuit to the signal output portion is provided to switch from a connection to the PLL circuit to a connection to the oscillator circuit in a case where there is no received signal.

Abstract: Embodiments of signal bias generators and regulators are described generally herein. Other embodiments may be described and claimed.

Abstract: A voltage controlled oscillator arrangement is disclosed. The arrangement includes a voltage controlled oscillator and a bypass component. The voltage controlled oscillator has an output and a tuning port. The output provides an output signal at an operating frequency. The tuning port is configured to select the operating frequency according to an applied voltage. The voltage controlled oscillator has active portions and inactive portions. During the active portions, the output signal is at a non-zero value. The bypass component is configured to apply a bypass compensating signal to the tuning port during the active portions of the voltage controlled oscillator. The bypass compensating signal compensates for an oscillator temperature of the voltage controlled oscillator.

Abstract: Oscillator regulation circuitry is provided for regulating a frequency of an output signal generated by an oscillator. Oscillator regulation circuitry has frequency sensing circuitry for sensing the frequency of the output signal and generating a first signal depending on the frequency, and control circuitry which generates the oscillator control signal based on the comparison between the first signal and a non-oscillating reference signal. The frequency sensing circuitry includes at least one switched capacitor. This approach provides improved noise reduction, less sensitivity to process, temperature and voltage variations, and a more linear scaling of the frequency with the reference signal, compared to previous techniques.

Abstract: Embodiments of signal bias generators and regulators are described generally herein. Other embodiments may be described and claimed.

Abstract: A low-power voltage controlled oscillator is provided. The voltage controlled oscillator includes (2n+1) first circuit components (n is an integer of one or more). An output terminal of the first circuit component in a k-th stage (k is an integer of one or more and 2n or less) is connected to an input terminal of the first circuit component in a (k+1)-th stage. An output terminal of the first circuit component in a (2n+1)-th stage is connected to an input terminal of the first circuit component in a first stage. One of the first circuit components includes a second circuit component and a third circuit component whose input terminal is connected to an output terminal of the second circuit component. The third circuit component includes a first transistor and a second transistor whose source-drain resistance is controlled in accordance with a signal input to a gate through the first transistor.

Abstract: Various techniques for generating an output clock based on a reference clock. This disclosure relates to generating an output clock signal based on a reference clock signal. In one embodiment, a method includes generating, using information received from a control circuit, an output clock signal using both a first number of edges or an input clock signal and a second, different number of edges of the input clock signal. In this embodiment, the control circuit runs at a frequency that is less than a frequency of the input clock signal. The received information may indicate, for a pulse of the output clock signal, whether the pulse should be generated using the first number of edges or the second number of edges. In some cases, the second number of edges may be the first number of edges plus one. The first and second number of edges may be programmable quantities.

Abstract: A method for reducing the phase noise of a oscillator includes monitoring a phase slope of a resonator, and controlling the resonator to operate the resonator at a high phase slope condition, wherein the resonator comprises a piezoelectric material, or piezoelectric quartz.

Abstract: A voltage controlled oscillator includes a voltage-to-current converter and a current controlled oscillator, where the voltage-to-current converter is used for converting an input voltage to generate an output current, and the current controlled oscillator is used for generating an output frequency signal according to the output current. In addition, the voltage-to-current converter includes an input terminal, a resistor, a current mirror and a current generating circuit, where the input terminal is for receiving the input voltage; the resistor is coupled to the input terminal; the current mirror is coupled to the resistor, and is used for mirroring a reference current to generate a mirrored current, where the reference current is formed according to at least a current flowing through the resistor; and the current generating circuit is coupled to the current mirror, and is used for generating the output current according to at least the mirrored current.

Abstract: A wide frequency, low voltage oscillator includes multiple delay elements, in which each delay element includes two inverters coupled through a latching element into a differential-type configuration. Two current-source PMOS devices bias the latching element in a high-gain region at low-voltage. By coupling these current-source PMOS devices into the delay elements, the start-up voltage of the latching element is reduced. Each delay element is also biased using a replica bias circuit that scales the supply/control voltage of the oscillator and provides the scaled supply/control voltage to control the lower rail of oscillation amplitude. By coupling the replica bias circuit to the lower rail, the lower rail of the oscillation amplitude follows the changes to the supply/control voltage.

Abstract: One embodiment relates to a method of compensating for crystal frequency variation over temperature. An example method includes obtaining an indication of temperature, computing a temperature compensation value based on the indication of temperature and a piecewise linear temperature compensation approximation, and compensating for a temperature offset in a crystal reference signal by adjusting a division ratio of a fractional divider in a phase-locked loop. The piecewise linear temperature compensation approximation can represent an approximation of frequency error in a crystal reference signal originating from a crystal over temperature. The piecewise linear temperature compensation approximation can be, for example, a linear approximation, a quadratic approximation, or a cubic approximation.

Abstract: A voltage controlled oscillator (VCO) includes a current controlled oscillator, a voltage-to-current converter, and a sensing circuit. The sensing circuit includes a delay unit, and the sensing circuit is configured to generate a plurality of compensation control signals in response to a time delay of the delay unit. The voltage-to-current converter is configured to generate a current signal in response to a VCO control signal and the plurality of compensation control signals. The current controlled oscillator is configured to generate an oscillating signal in response to the current signal.

Abstract: A semiconductor device contrived to prevent a reference voltage and a reference current which are supplied to a high speed OCO from varying with a change in ambient temperature and/or a change in an external power supply voltage and to reduce the circuit area of a power supply module. The high speed OCO outputs a high speed clock whose magnitude is determined by the reference current and the reference voltage. A logic unit adjusts the values of the reference current and reference voltage, according to the reference voltage and reference current trimming codes related to detected ambient temperature and operating voltage.

Abstract: A narrow band receiver or transceiver for processing electrical signals. The narrow band receiver or transceiver includes an amplifier, a voltage controlled oscillator and a tuning assembly comprising at least one control loop for tuning of the voltage controlled oscillator. At least a gain control of the amplifier is coupled to the control loop for simultaneously tuning the output amplitude of the voltage controlled oscillator and the gain of the amplifier. A compensation of the effect of variation on the gain of the amplifier, which includes an LC tank circuit, is performed by using an information in another LC tank circuit of the voltage controlled oscillator in the control loop.

Abstract: The present disclosure relates to an oscillation circuit including a differential negative resistance element, a resonance circuit connected to the differential negative resistance element, and a stabilization circuit connected in parallel with the negative resistance element to suppress parasitic oscillation. The stabilization circuit includes a variable shunt resistor and an adjusting device for adjusting the shunt resistor.

Abstract: According to an example embodiment, a device includes a resonant circuit configured and arranged to provide a peak current flow at a resonance frequency. A trimming circuit provides variable impedances to the resonant circuit and thereby changes the resonance frequency for the resonant circuit. A driver circuit is configured to generate a trimming signal that oscillates at a desired frequency. A switch circuit couples and decouples the driver circuit to the resonant circuit for driving the resonant circuit with the trimming signal. An amplitude detection circuit detects amplitudes for signals generated in response to the trimming signal being connected to the resonant circuit. A processing circuit correlates detected amplitudes from the amplitude detection circuit with different impedance values of the variable trimming circuit.

Abstract: A phase-locked loop double-point modulator may include a frequency divider having a ratio which can be changed by a first modulation signal, and an oscillator, a frequency of which can be changed by a second modulation signal correlated to the first modulation signal. A calibration circuit may be configured, in a calibration mode, to match the gains of the first and second modulation signals based on frequency measurements of the oscillator for two different calibration values of the second modulation signal. The phase-locked double-point modulator may also include an attenuator having a constant ratio greater than 1 and placed in the path of the second modulation signal, and a selector switch configured to be controlled by the calibration circuit to reduce the ratio of the attenuator in the calibration mode.

Abstract: The present application discloses a voltage-controlled oscillator device and a method of correcting the voltage-controlled oscillator. The voltage-controlled oscillator device comprises predistortion module, configured to predistort an input voltage to obtain a predistorted voltage; and a voltage-controlled oscillator, configured to generate an output signal with a corresponding oscillation frequency according to the predistorted voltage, wherein the predistortion module corrects a non-linear characteristic of the voltage-controlled oscillator, so that there is a linear relationship between the input voltage and the oscillation frequency of the output signal. The voltage-controlled oscillator device may be applied to a phase-locked circuit in a communication system.

Abstract: A phase shift phase locked loop (PSPLL) are described. The phase shift PLL includes a PLL and a phase adjusting circuit coupled to the inputs of the PLL. The phase adjusting circuit has a first input, a first output, a second input, a third input, and a second output. The first output and the second output are coupled to a first input and a second input of the PLL, respectively. The second input of the phase adjusting circuit receives a feedback signal and the third input of the phase adjusting circuit receives a control signal. The phase adjusting circuit receives a reference signal and sends a first output signal and a second output signal based on the reference signal to the PLL to adjust a phase of an output signal of the PLL in an increment less than a time period of the output signal of the PLL.

Abstract: An oscillator circuit including a first capacitor provided with a first terminal; a resistor provided with a reference terminal; a first current generator provided with a connection terminal; a second current generator provided with a second connection terminal. Further, the circuit includes a switching matrix between the first and second generators and resistor and the at least one first capacitor.

Abstract: A digital frequency synthesizer with an automatic calibration system. The digital frequency synthesizer is calibrated by initiating a coarse tuning operation to rapidly reach a preliminary frequency that is proximate to the desired final frequency. A calibration procedure is then executed for adjusting gain in the frequency synthesizer based on the preliminary frequency. This test involves applying one or more test signals to the frequency synthesizer and measuring a signal generated in the frequency synthesizer. This measured signal corresponds to a gain response of the circuit at the preliminary frequency. When the expected gain is known, any difference relative to the gain of the measured signal is used to adjust the gain in a circuit of the frequency synthesizer such that the actual gain substantially matches the expected gain.

Abstract: An all-digital frequency detector is provided, which includes a phase-frequency detector receiving a reference clock and an input clock, two sample/hold circuits sampling the phase-frequency detector outputs responsive to a ninety-degree phase shifted reference clock and a ninety-degree phase shifted input clock, a plurality of logical operators to generate an output frequency detection signal and a output clock responsive to the difference between the reference clock and the input clock.

Abstract: In one embodiment, a voltage-controlled oscillator (VCO) is provided that includes: a plurality of differential inverters coupled to form a loop, each differential inverter having a differential pair of transistors configured to steer a tail current from a current source, the current source sourcing the tail current responsive to a bias voltage, wherein each transistor in the differential pair couples to a power source through a corresponding switching-capacitor circuit; and a bias circuit configured to generate the bias voltage such that a transconductance for each transistor in the differential pairs is proportional to a factor that is a function of a ratio of transistor widths within the bias circuit.

Abstract: An LC oscillator tank that generates a tank oscillation at a phase substantially equal to a temperature null phase. The oscillator further includes frequency stabilizer circuitry coupled to the LC oscillator tank to cause the LC oscillator tank to operate at the temperature null phase. In one aspect of the disclosure, a feedback loop may split the output voltage of the LC tank into two voltages having different phases, where each voltage is independently transformed into a current through programmable transconductors, The two currents may be combined to form a resultant current which is then applied to the LC tank. The phase of the resultant current is such that the LC tank operates at an impedance condition that achieves frequency stability across temperature.

Abstract: An electrical circuit includes a circuit element and a common mode rejection circuit element. The circuit element is configured to operate at a selected frequency within a variable frequency range and the common mode rejection circuit element is configured to reject a common mode current through the circuit element, wherein the common mode rejection circuit element is adjustable.

Abstract: A method for reducing signal edge jitter in an output signal from a numerically controlled oscillator includes processing an input signal with a first accumulator to provide a first accumulator output signal and continuing to use a carry in the processing of the input signal with the first accumulator in the event of an overflow. The method further includes processing the input signal with a second accumulator to provide a second accumulator output signal and rejecting a carry in the processing of the input signal with the second accumulator in the event of an overflow. The method further includes outputting the second accumulator output signal at an output of the numerically controlled oscillator and synchronizing the second accumulator using the first accumulator output signal.

Abstract: A modulation section including a feedback circuit configured to conduct feedback control of an output signal from a voltage controlled oscillator based on an inputted modulation signal, and a feed-forward circuit configured to calibrate the modulation signal and outputting the calibrated modulation signal to the voltage controlled oscillator; a signal output section configured to output, to the modulation section, a predetermined reference signal instead of the modulation signal when a calibration is conducted; and a gain correction section configured to, in a state where the feedback circuit is forming an open loop, calculate a frequency transition amount of the reference signal outputted by the voltage controlled oscillator, and correct a gain used for calibrating the modulation signal at the feed-forward circuit based on the calculated frequency transition amount.