Abstract: In a particular implementation, a method to reduce noise/clock jitter and to generate a “stretched” output clock to optimize for jitter of the output clock is disclosed. The method includes: generating two or more clock phases upon detecting a transient voltage by a detector circuit, generating an output clock signal based on one of the two or more clock phases; and altering a phase speed of the output clock signal to correspond to a phase speed of an input clock signal.

Abstract: In an embodiment a ring oscillator circuit includes a chain of cascade-coupled inverter stages coupled between an oscillator supply voltage node and a reference voltage node, the oscillator supply voltage node configured to provide an oscillator supply voltage, a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node configured to provide a system supply voltage, the current generator circuit being configured to inject a current into the oscillator supply voltage node and a biasing circuit including a first bias control transistor and a second bias control transistor coupled in series between the reference voltage node and the oscillator supply voltage node, wherein the first bias control transistor is configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to the oscillator control signal being indicative that the ring oscillator circuit is in an inactive operation state.

Abstract: Various implementations described herein are related to a device. The device may include first circuitry that receives a clock signal and provides one or more phase-shifted pulse signals based on the clock signal. The device may include second circuitry that receives an input voltage, receives the clock signal, and provides an internal control signal based on the input voltage and the clock signal. The device may include third circuitry that receives the internal control signal, receives the one or more phase-shifted pulse signals, and provides an output clock signal based on the internal control signal and the one or more phase-shifted pulse signals.

Abstract: A circuit includes a phase-locked loop configured to receive a reference clock signal and to generate a first clock signal having a first frequency. A secondary clock generation circuit is configured to generate a second clock signal having a second frequency lower than the first frequency. A voltage detection circuit is coupled to receive a supply voltage and configured to detect a droop in the supply voltage and generate a clock control signal in response to detecting a droop in the supply voltage. A selection circuit is coupled to the voltage detection circuit to receive the clock control signal and is configured to select one of the first clock signal and the second clock signal based on the clock control signal.

Abstract: Apparatuses and methods using current-starved ring oscillator biased by floating gate transistors with a variety of applications including as a power-free radiation detector or silicon age determination or odometer system.

Abstract: A power converter includes a current-monitoring on-state controller that is configured to adjust the timing of a switch-mode voltage conversion stage of the power converter. For example, the timing of the turn-on of a MOSFET associated with a buck converter operated in a discontinuous conduction mode (e.g., quasi-resonant) can be adjusted based on a zero crossing of current through a tank inductor also associated with the buck converter. More particularly, the MOSFET may be turned on after a predetermined delay is initiated after current through the tank inductor reaches zero. The predetermined delay is based on a resonance period defined by the characteristic capacitance of the MOSFET and the inductance of the tank inductor.

Abstract: Various examples with respect to dual threshold clock control are described. A method involves sensing an input voltage of a processing circuit with a first mechanism and a second mechanism different from the first mechanism. The method also involves regulating a first droop of the input voltage using the first mechanism. The method further involves regulating a subsequent droop of the input voltage after the first droop using the second mechanism.

Abstract: A clock and data recovery device associated with a data receiving apparatus, the clock and data recovery device including an oscillator configured to generate a clock signal; and a regulator configured to supply current to the oscillator, the regulator including, a first current source configured to supply a first current to the oscillator, and a second current source configured to supply a second current to the oscillator such that the second current is supplied to the oscillator, after a period of time, to de-emphasize the first current, the period of time being based on the first current.

Abstract: A passive leakage management circuit for a switch leakage current includes a switch being operable in a first operating mode, wherein the switch output supplies an output current having a first predetermined voltage. In a second operating mode, the switch output supplies a leakage current having a second voltage, a first current path, and a leakage current path.

Abstract: Droop monitors spread across a system-on-chip (SoC) monitor for voltage droops in regulated supply voltage supplied to logic circuitry of the SoC. In the event of a voltage droop, a clock signal supplied to the logic circuitry is stretched, to temporarily increase a period of the clock signal. The droop monitors may include a sensing delay line provided voltage at the regulated supply voltage, and a reference delay line supplied with a reference voltage, with operations of the delay lines monitored to determine a voltage droop.

Abstract: A clock duty cycle calibration and frequency multiplier circuit used in a square wave frequency multiplier has a multiplexing module, which performs a phase-inversion operation on a clock signal according to a control signal; a calibration module which adjusts the duty cycle according to a control signal, and outputs a clock signal with a 50% duty cycle; a delay module, which performs a delay operation on the clock signal according to a control signal; a detection module, which compares the clock signal and outputs a feedback signal; a control module, which outputs a control signal according to the feedback signal; a frequency multiplication module, which performs a frequency multiplication operation on the clock signal. Therefore, high-precision clock signal frequency multiplication is implemented with relatively low circuit complexity and low cost.

Abstract: The voltage regulator device has a wide band amplifier having an input reference voltage, Vref and an input feedback voltage, Vfbk. The device has a source follower coupled to the wide band amplifier, the source follower coupled to an output of the wide band amplifier. The device has a VDD source, a regulator output, and a current source coupled to the source follower and the VDD source. The device has a low frequency path comprising a first transistor. The first transistor has a first gate, a first source, and a first drain. The first source is coupled to the VDD source. The first gate is coupled to a slow node, and the first drain is coupled to the regulator output. The low frequency path comprises a RC network, which has a capacitor, a resistor, and the slow node configured between the resistor and the capacitor. The device has a high frequency path comprising a second transistor. The second transistor has a second gate, a second source, and a second drain. The second source is coupled to the VDD source.

Abstract: A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.

Abstract: Oscillator circuits and methods are disclosed. In an embodiment, a circuit includes a voltage controlled oscillator (VCO) and a regulator coupled to a supply input of the VCO. The circuit also includes an oscillation dampening circuit coupled to an output of the regulator. A resistance or a capacitance of the oscillation dampening circuit is configured to vary based on current provided to the VCO.

Abstract: Disclosed are circuits and methods for increasing an output frequency of an inductance-capacitance (LC) oscillator. In some embodiments, the LC oscillator can be implemented as a voltage-controlled oscillator (VCO) having differential outputs. When the VCO is implemented on a die, wirebond connections from the outputs to a ground results in an effective inductance that impacts a maximum frequency associated with the VCO. An electrical connection such as a wirebond between the differential outputs yields a reduction in the effective inductance thereby increasing the maximum frequency. In some embodiments, the wirebond between the differential outputs can be configured so that its contribution to mutual inductance is reduced or substantially nil.

Abstract: A circuit generates a compensation signal that can remove noise in a VCO introduced by a supply signal (i.e., supply-side noise). The circuit includes two transistors connected in series. A resistor is connected between the gate of the first transistor and the supply signal, and a capacitor is connected between the gate of the second transistor and the supply signal. The circuit is designed so that the transconductance of one transistor is greater than or equal to twice the transconductance of a second transistor. The compensation signal is supplied through a capacitor, which compensates for capacitors in a VCO, to an internal supply node of the VCO. At the internal supply node, the compensation signal removes (or greatly reduces) the noise introduced by the supply signal noise, resulting in a less-noisy output signal from the VCO.

Abstract: A method and a phase locked loop (PLL) circuit for implementing compact current mode logic inductor capacitor voltage controlled oscillator for high speed communications, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a current mode logic (CML) inductor capacitor (LC) Voltage Controlled Oscillator (VCO). The PLL circuit includes a reference circuit generates a virtual ground node for biasing noise sensitive components, providing level shifted VCO increment and decrement tuning values from a phase detector coupled by a respective resistor to tune a varactor of the LC VCO, and providing a loop filter function. The virtual ground node tracks a logic power supply noise, incurring no jitter penalty, and eliminating the need for a separate power supply for the PLL circuit.

Abstract: There is provided an oscillator capable of lowering the power supply voltage without degrading the phase noise, while employing the conventional circuit configuration. According to one aspect of the present invention, there is provided an oscillator comprising: an oscillation circuit; a bias generation circuit for generating a bias signal to drive the oscillation circuit; and a booster circuit for boosting a power supply voltage to generate a boosted voltage for driving the bias generation circuit. In addition, the oscillation circuit, the bias generation circuit, and the booster circuit are provided in a single IC chip, and the booster circuit may receive the power supply voltage VDD from the power supply arranged at the exterior of the IC chip.

Abstract: An oscillator circuit includes an adjustable frequency oscillator configured to free-run at a first frequency below a desired second target frequency. This adjustable frequency oscillator is configured to modulate a frequency of its periodic output signal upwards from the first frequency to the second frequency in response to a feedback bias current. A divider is also provided, which is configured to convert the periodic output signal to a reduced-frequency control signal. This reduced-frequency control signal is provided to a frequency-to-current (F2C) converter, which is configured to drive the adjustable frequency oscillator with the feedback bias current (e.g., pull-down current) in response to the reduced-frequency control signal.

Abstract: A voltage controlled oscillator (VCO) core for cancelling a supply noise is described. The VCO core includes an input node that receives the supply noise. The VCO core also includes a noise path coupled to the input node. The VCO core additionally includes a cancellation path coupled to the input node and the noise path. The cancellation path includes a programmable gain circuit coupled with a first terminal of a varactor. The supply noise passes through the programmable gain circuit to produce a cancellation noise.

Abstract: LC tank and ring-based VCOs are disclosed that each include a differential pair of transistors for steering a tail current generated by a current source responsive to a bias voltage. A biasing circuit generates the bias voltage such that a transconductance for the transistors in the differential pairs is inversely proportional to a resistance.

Abstract: A power management apparatus and method for maintaining a substantially constant duty cycle of a reference clock signal in a multi-power oscillator, includes a first output power transistor in electrical parallel with a series arrangement of a second output power transistor and a switch, and a crystal oscillator capacitively coupled to a common gate of the first and second output power transistors, wherein a level of the reference clock signal power output is a normal power level when the switch is open and the level of the reference clock signal power output is a higher power level when the switch is closed to operate the second output power transistor in parallel with the first output power transistor.

Abstract: In one embodiment, a voltage-controlled oscillator (VCO) is provided having an output signal having a frequency responsive to a tuning signal. The VCO includes: a plurality of inverters coupled to form a loop, each differential inverter having a differential pair of transistors configured to steer a tail current from a current source, the current source sourcing the tail current responsive to a bias voltage, each inverter stage including a plurality of switched-capacitor circuits configured to control a signal delay through the inverter stage response to the tuning signal so as to control the frequency of the output signal; and a bias circuit configured to generate the bias voltage responsive to a reference signal such that an amplitude of the output signal is substantially independent of the output signal frequency and depends upon the reference signal.

Abstract: With some embodiments, a VCO (voltage controlled oscillator) operates at an integer multiple (N) above a desired transmission frequency. In accordance with one embodiment, a chip is provided with a VCO to generate a signal and a frequency dividing circuit to provide a reduced frequency version of the signal to a transmit mixer. The transmit mixer is followed by a power amplifier that is on the same die as the VCO. The power amplifier is to generate an OFDM output transmission.

Abstract: According to one embodiment, a phase locked loop (PLL) circuit includes an application unit, a correlator, an integrator and a power supply noise canceller. The application unit applies the test signal to a power supply voltage. The correlator extracts a frequency error signal as a monitor signal and calculates a correlation value for the test signal and the monitor signal to generate a correlation signal. The integrator integrates the correlation signal to generate an integral signal. The power supply noise canceller provides a cancellation gain corresponding to the integral signal to the power supply voltage to which the test signal is applied, to generate a control signal.

Abstract: Systems and methods for amplitude loop control for oscillators. In some embodiments, an electronic circuit may include oscillator circuitry configured to produce a periodic signal, and control circuitry operably coupled to the oscillator circuitry, the control circuitry including switched capacitor circuitry configured to determine a difference between maximum and minimum peak voltage values of the periodic signal, the control circuit configured to control a voltage amplitude of the periodic signal based upon the difference. In other embodiments, a method may include receiving a clock signal from a clock generator, determining, using a switched capacitor circuit, a first peak voltage value of the clock signal, determining, using the switched capacitor circuit, a second peak voltage value of the clock signal, and controlling a bias current applied to the clock generator based upon a difference between the first and second peak voltage values.

Abstract: An oscillation circuit including a reference voltage generation circuit that adds a proportional-to-absolute-temperature (PTAT) output, which increases in proportion to an absolute temperature, to a complementary-to-absolute-temperature (CTAT) output, which decreases in proportion to an absolute temperature, to generate and output a reference voltage. The oscillation circuit generates an oscillation signal having a desired and fixed frequency.

Abstract: A dynamic level shifter circuit and a ring oscillator implemented using the same are disclosed. A dynamic level shifter may include a pull-down circuit and a pull-up circuit. The pull-up circuit may include an extra transistor configured to reduce the current through that circuit when the pull-down circuit is activated. A ring oscillator may be implemented using instances of the dynamic level shifter along with instances of a static level shifter. The ring oscillator may also include a pulse generator configured to initiate oscillation. The ring oscillator implemented with dynamic level shifters may be used in conjunction with another ring oscillator implemented using only static level shifters to compare relative performance levels of the static and dynamic level shifters.

Abstract: A signal generating circuit for a real time clock device is disclosed, having an oscillating circuit, a voltage detecting circuit, and a control circuit. The oscillating circuit is used for generating oscillating signals. The voltage detecting circuit is used for detecting a voltage level coupled with the signal generating circuit. The control circuit is coupled with the oscillating circuit and the voltage detecting circuit. When the voltage level detected by the voltage detecting circuit locates in a predetermined range, the control circuit configures the oscillating circuit to generate the oscillating signals with a larger current at a first interval and to generate the oscillating signals with a smaller current at a second interval. The control circuit further generates a clock signal according to the oscillating signals at a third interval.

Abstract: A circuit of inductance/capacitance (LC) voltage control oscillator (VCO) includes an LC VCO unit, a peak detector and a processing unit. The LC VCO unit receives a current control signal and outputs an oscillating voltage signal. The peak detector receives the oscillating voltage signal to obtain an averaged voltage value. The processing unit receives the averaged voltage value to accordingly output the current control signal and feedback to the LC VCO unit. The processing unit also detects whether or not the averaged voltage value has reached to a saturation state and a corresponding critical current. After the current control signal reaches to the critical current, the current control signal is set within a variance range near the critical current.

Abstract: A substantially temperature-independent LC-based oscillator uses bias control techniques. Temperature independence may be achieved by controlling the harmonic frequency content of the output of the oscillator by controlling the amplitude. Amplitude control may be achieved by inserting a control mechanism in the feedback loop of the oscillator.

Abstract: A MEMS device and method for amplitude regulation of a MEMS device are disclosed. In a first aspect, the MEMS device comprises a MEMS resonator, a limiter coupled to the MEMS resonator, and a regulator coupled to the limiter. The MEMS device includes an amplitude control circuit coupled to the MEMS resonator. The amplitude control circuit controls a supply of the limiter via the regulator to regulate oscillation loop amplitude of the MEMS device. In a second aspect, the method includes coupling a regulator to the limiter, coupling an amplitude control circuit to the MEMS resonator, and controlling a supply of the limiter via the regulator to regulate oscillation loop amplitude of the MEMS device.

Abstract: A PLL circuit includes an oscillator, a detection block, an integral path and a proportional path. The oscillator generates an oscillation signal. The detection block detects a phase difference between the oscillation signal and a reference signal and generates an integral signal that represents an integral value of the phase difference and a proportional signal that represents a current value of the phase difference. The integral path includes a regulator that receives the integral signal and supplies a regulated integral signal to the oscillator, and the regulator has a feedback loop including an error amplifier. The proportional path supplies the proportional signal, separately from the integral signal, to the oscillator. The oscillator generates the oscillation signal having an oscillation frequency controlled by both of the regulated integral signal and the proportional signal such that the phase of the oscillation signal is locked to the phase of the reference signal.

Abstract: An illustrative system includes an amplifier operably connected to a phase shifter. The amplifier is configured to amplify a voltage from an oscillator. The phase shifter is operably connected to a driving amplitude control, wherein the phase shifter is configured to phase shift the amplified voltage and is configured to set an amplitude of the phase shifted voltage. The oscillator is operably connected to the driving amplitude control. The phase shifted voltage drives the oscillator. The oscillator is at an internal resonance condition, based at least on the amplitude of the phase shifted voltage, that stabilizes frequency oscillations in the oscillator.

Abstract: A large gain is used to start up the oscillation of the crystal quickly. Once the oscillation starts, the amplitude is detected. A control circuit determines based on the measured amplitude to disable a low resistance path in the controlled switch array to reduce the applied gain below the power dissipation specification of the crystal. Another technique introduces a mixed-signal controlled power supply multi-path resistive array which tailors the maximum current to the crystal. A successive approximation register converts the amplitude into several partitions and enables/disables one of several power routing paths to the inverter of the oscillator. This allows a better match between the crystal selected by the customer and the on-chip drive circuitry to power up the oscillator without stressing the crystal. The “l/f” noise of the oscillator circuit is minimized by operating transistors in the triode region instead of the linear region.

Abstract: A DC power supply circuit comprises an output configured to provide a power supply signal to an RF element for generating an RF output signal. Furthermore, the DC power supply circuit comprises an input configured to receive the RF output signal. The DC power supply circuit is configured to generate the DC power supply signal based on the received RF output signal.

Abstract: A plasma processing apparatus includes a plasma generating device configured to generate a plasma within a processing vessel by using a high frequency wave generated by a microwave generator 41 including a magnetron 42 configured to generate the high frequency wave; detectors 54a and 54b configured to measure a power of a traveling wave that propagates to a load side and a power of a reflected wave reflected from the load side, respectively; and a voltage control circuit 53a configured to control a voltage supplied to the magnetron 42 by a power supply 43. Further, the voltage control circuit 53a includes a load control device configured to supply, to the magnetron 42, a voltage corresponding to a power calculated by adding a power calculated based on the power of the reflected wave measured by the detector 54b to the power of the traveling wave measured by the detector 54a.

Abstract: An oscillation circuit section is provided which can attain the reduction of a consumed power amount and the reduction of a manufacturing cost. In a semiconductor device, voltages are generated to drive the oscillation circuit section by using a plurality of MOS transistors which are connected in serial and each of which is in a diode connection. At this time, each voltage is generated based on a power supply voltage and a ratio of the threshold voltages of the plurality of MOS transistors. Therefore, it is possible to suppress the threshold voltage of each MOS transistor, to save an area of each MOS transistor, and to reduce the consumed power amount of the oscillation circuit section.

Abstract: A constant voltage circuit which can realize a low consumption current, and a crystal oscillation circuit using the constant voltage circuit. The constant voltage circuit is provided with a temperature characteristic regulation element, in order to minimize a difference between a negative slope of a voltage response of a constant voltage to a temperature change and a negative slope of a voltage response of the smallest operation voltage that can oscillate in the crystal oscillation circuit to the temperature change, so that the consumption current of the crystal oscillation circuit is decreased. When the constant current generated by the constant voltage circuit is decreased, the consumption current of the constant voltage circuit is decreased, and the consumption current of the whole oscillation device is decreased.

Abstract: A technique for tracking changes in bias conditions of a microelectromechanical system (MEMS) device includes applying an electrode bias signal to an electrode of the MEMS device. The technique includes applying a mass bias signal to a mass of the MEMS device suspended from a substrate of the MEMS device. The technique includes generating the mass bias signal based on a target mass-to-electrode bias signal level and a signal level of the electrode bias signal.

Abstract: A crystal oscillator circuit is configured to output an oscillation signal. A bias circuit responds to control signal to generate a bias current for application to the crystal oscillator circuit. A current generator generates a sense current from the control signal. The sense current is compared to a reference current by a comparator circuit. The comparator circuit generates a ready signal in response to the comparison. The ready signal is indicative of whether the oscillation signal output from the crystal oscillator circuit is ready for use by other circuitry. The reference current may be generated by a circuit which replicates the bias circuit.

Abstract: A system and method are provided for combined generation of I and Q signal references according to a periodic input signal and selective phase interpolation of an output signal with reference thereto. A ring oscillator portion generates an oscillator signal, and includes a plurality of delay stages interconnected in cascade to collectively execute an odd number of signal state inversions within a closed loop. The delay stages establish at respective nodes defined therebetween correspondingly delayed oscillator signal versions, successively shifted in phase by a predetermined phase difference. A signal injection portion selectively applies to at least one node of the ring oscillator portion a current bias according to the periodic input signal, and selectively adjusts each current bias in amplitude. The oscillator signal is thereby frequency locked to the periodic input signal, defining I/Q references with respect to the delayed oscillator signal version established at the current biased node.

Abstract: A temperature-compensated oscillator includes a temperature sensor, a temperature compensation circuit, a voltage-controlled oscillation circuit adapted to output an oscillation signal on which temperature compensation is performed based on the temperature compensation voltage, an output circuit adapted to output an ON/OFF signal based on a relationship between variation of the detected-temperature voltage output by the temperature sensor and a reference voltage, a switch circuit adapted to supply the temperature compensation circuit with electrical power in response to the ON/OFF signal, and a sample-and-hold circuit adapted to be switched between a state of outputting the temperature compensation voltage to the voltage-controlled oscillation circuit while holding the temperature compensation voltage output by the temperature compensation circuit, and a state of outputting the temperature compensation voltage held to the voltage-controlled oscillation circuit while cutting the connection to the temperature c

Abstract: A DC power supply circuit comprises an output configured to provide a power supply signal to an RF element for generating an RF output signal. Furthermore, the DC power supply circuit comprises an input configured to receive the RF output signal. The DC power supply circuit is configured to generate the DC power supply signal based on the received RF output signal.

Abstract: A temperature-compensated oscillator includes a temperature compensation circuit adapted to output a temperature compensation voltage, a voltage-controlled oscillation circuit on which temperature compensation is performed based on the temperature compensation voltage, a switch circuit adapted to perform ON/OFF control on power supply to the temperature compensation circuit, and a sample-and-hold circuit adapted to perform switching control between an ON state of outputting the temperature compensation voltage to the voltage-controlled oscillation circuit while being connected to the temperature compensation circuit and holding the temperature compensation voltage output from the temperature compensation circuit when the power is supplied to the temperature compensation circuit, and an OFF state of outputting the temperature compensation voltage held to the voltage-controlled oscillation circuit while cutting connection to the temperature compensation circuit when the power supply to the temperature compensat

Abstract: According to one embodiment, a switching unit switches between a first state in which the current source is connected to a first capacitance element and a ground electric potential is connected to a second capacitance element and a second state in which a current source is connected to the second capacitance element and the ground electric potential is connected to the first capacitance element. A comparison unit compares a voltage charged in the first capacitance element and a reference voltage with each other in the first state and compares a voltage charged in the second capacitance element and the reference voltage with each other in the second state. A generation unit generates a periodical pulse based on a comparison result acquired by the comparison unit. The switching unit alternately switches between the first state and the second state based on the comparison result acquired by the comparison unit.

Abstract: A reference circuit for an oscillator module is provided. The reference circuit includes a reference voltage generation unit and a reference current generation unit. The reference voltage generation unit includes an electric element having a voltage proportional to absolute temperature (PTAT voltage) and provides a reference voltage based on the PTAT voltage. The reference current generation unit is coupled to the reference voltage generation unit and provides a reference current to the oscillator circuit to serve as an input current based on the PTAT voltage. The oscillator circuit generates a clock signal based on the reference voltage and the input current. The reference voltage and the input current are proportional to absolute temperature and have the same change trend relative to absolute temperature, such that the clock signal is a temperature insensitive signal. An oscillator module including an oscillator circuit and the foregoing reference circuit is also provided.

Abstract: An oscillation circuit of a semiconductor apparatus includes a first level regulation unit configured to regulate an output voltage at an output node according to a difference between a reference voltage and the output voltage, and a second level regulation unit coupled between a power supply voltage terminal and a source voltage terminal.

Abstract: A ring oscillator that is more insensitive to power supply ripple utilizes an amplifier circuit having a first input coupled to a reference voltage. A current is generated that represents a control voltage supplied to the oscillator control circuit. That current is mirrored and supplied as a control current to the oscillator. An amplifier is used in a feedback loop to ensure that incremental variations in source to drain voltage of a first transistor of the current mirror is present in a second transistor of the current mirror to make the control current more immune to supply ripple.

Abstract: In accordance with some embodiments of the present disclosure, an oscillator may include a crystal resonator and a squaring circuit coupled to the crystal resonator and configured to convert a sinusoidal signal produced by the crystal resonator to a square-wave signal, the squaring circuit comprising a bias circuit configured to transmit a selected bias voltage for the squaring circuit, the selected bias voltage selected from a plurality of potential bias voltages. In accordance with this and other embodiments of the present disclosure, an oscillator may include a crystal resonator, an inverter coupled in parallel with the crystal resonator, and a programmable voltage regulator coupled to the inverter. The programmable voltage regulator may be configured to supply a first supply voltage to the inverter during a startup duration of the oscillator, and supply a second supply voltage to the inverter after the startup duration, wherein the second supply voltage is lesser than the first supply voltage.