Abstract: A random number generator that includes control circuit, an oscillation circuit, an oscillation detection circuit and a latch circuit is introduced. The control circuit sweeps a configuration of a bias control signal among a plurality of configurations. The oscillation circuit generates an oscillation signal based on the configuration of the bias control signal. The oscillation detection circuit detects an onset of the oscillation signal, and outputs a lock signal. The latch circuit latches the oscillation signal according to a trigger signal to output a random number, wherein the trigger signal is asserted after the lock signal is outputted, and the configuration of bias control signal is locked after the lock signal is outputted. A method for generating a random number and an operation method of a random number generator are also introduced.

Abstract: A method and apparatus for detecting a microphone condition of a microphone, the method comprising: applying an electrical stimulus to a microphone; measuring an electrical response to the electrical stimulus at the microphone; comparing the electrical response to an expected response; and determining the microphone condition based on the comparison.

Abstract: A processing system includes a pseudo-random bit sequence (PRBS) control unit and a PRBS generator that is used to dynamically generate a PRBS from, for example, a first PRBS and a second PRBS. The PRBS generator is coupled to the PRBS control unit. The PRBS generator generates the second PRBS by dynamically adjusting from a first set of flip-flops of a master set of flip-flops that generate the first PRBS to a second set of flip-flops of the first master set of flip-flops that generate the second PRBS. The PRBS generator includes a plurality of PRBS logic engines coupled to a first PRBS multiplexer, the first PRBS multiplexer being used to select either the first PRBS or the second PRBS that is output by the PRBS generator.

Abstract: Systems and Methods for determining a physiological parameter are disclosed. The physiological sensing device can measure a physiological parameter, determine a mood based on the physiological parameter, and render one or more songs associated with the mood.

Abstract: A system and method used for generating encryption keys on multiple devices and for encrypted data transfer between two or multiple devices. A sender system includes at least one sender device with nonlinear I-V characteristics. A receiver system includes at least one receiver device with nonlinear I-V characteristics. The at least one sender device with nonlinear I-V characteristics generates at least one sender output value used to create a string of characters or bits or bytes or numbers. The string of characters is used to encrypt data which is sent to the receiver device. The at least one receiver device with nonlinear I-V characteristics generates at least one receiver output value, and uses the at least one receiver output value to create the string of characters from the at least one receiver output value. A receiver processing unit generates the data from the encrypted data using the string of characters.

Abstract: A random number generator that includes control circuit, an oscillation circuit, a dynamic header circuit, an oscillation detection circuit and a latch circuit is introduced. The control circuit sweeps a configuration of a bias control signal among a plurality of configurations. The dynamic header circuit generates a bias voltage based on the configuration of the bias control signal. The oscillation circuit generates an oscillation signal based on the bias voltage. The oscillation detection circuit detects an onset of the oscillation signal, and outputs a lock signal. The latch circuit latches the oscillation signal according to a trigger signal to output a random number, wherein the trigger signal is asserted after the lock signal is outputted, and the configuration of bias control signal is locked after the lock signal is outputted. A method for generating a random number and an operation method of a random number generator are also introduced.

Abstract: A circuit for data encryption is provided. The circuit includes an encryption controller configured to randomly generate a frequency parameter defining different timeframes corresponding to different frequencies. The circuit also includes a random-clock-signal generator configured to receive the frequency parameter to synthesize an encryption clock signal based on a base clock signal. The encryption clock signal includes a random combination of different clock frequencies respectively over multiple different timeframes. Additionally, the circuit includes an encryption sub-circuit configured to receive plain data and to encrypt the plain data by a sampling replacement driven by the encryption clock signal to obtain encrypted data.

Abstract: An embedded device is provided that is configured to randomize execution time of a boot process of the embedded device performed responsive to a reset signal, wherein reset release time is nondeterministic. The embedded device may include a randomizer component configured to generate a timeout signal after a random interval, wherein to randomize execution time, the embedded device is further configured to execute a first portion of a reset process, signal the randomizer component to generate the timeout signal after a first random interval, wait for the timeout signal, and execute a second portion of the reset process responsive to the timeout signal.

Abstract: A pseudo random number generator implemented in hardware. The pseudo random number generator comprises a state post processing circuit for processing two state values to produce a random number. The circuit having a first combinatorial logic comprising a XOR or XNOR gate configured to process a first pair of bits from the state values, a second combinatorial logic comprising an OR or AND gate configured to process a second pair of bits from the state value, and third combinatorial logic comprising an OR or AND gate configured or process a third pair of bits from the state value. The circuit has fourth combinatorial logic configured to process the outputs of the first three set of combinatorial logic so as to provide a result bit of the random number. The fourth combinatorial logic comprises an AND or OR gate and a XOR or XNOR gate.

Abstract: A random number generating circuit includes M random number generators, where M is an integer greater than or equal to 2, configured to be independent of each other and generate M random number sequences, a delay adjustment circuit configured to output N sets of the M random number sequences including N different relative time differences or N different combinations of a plurality of relative time differences, where N is an integer greater than or equal to 2, by adjusting one or more relative time differences between the M random number sequences, and a logic operation circuit configured to perform an exclusive OR operation between the M random number sequences included in a set, for each of the N sets of the M random number sequences.

Abstract: In one implementation, a system providing remote access set-up for electronic devices includes a mobile device and a profile server communicatively coupled to the mobile device via a network. The profile server includes a hardware processor, and a server memory storing a profile management software code and a profile information associated with a user of the mobile device. The hardware processor executes the profile management software code to receive, via the network, a platform ID of a configurable hardware platform communicatively coupled to the mobile device, and to determine, based on the platform ID, platform assets including a default configuration associated with the configurable hardware platform.

Abstract: A physically unclonable function (PUF) device is provided. The PUF device includes: a plurality of PUF cells configured to generate an output. Each of the plurality of cells includes a sense amplifier, a load circuit. The sense amplifier includes a first circuit and a second circuit configured to generate a bit line and a complementary bit line. The sense amplifier having a first circuit and a second circuit configured to generate a bit line and a complementary bit line. The first circuit generates an output at a first output node and the second circuit generates an output at the second output node. The load circuit having a first transistor and a second transistor configured to generate a bias to the sense amplifier to obtain a mask bit at a first output node and a second output node. The control terminal of the first transistor is controlled by a first selection bit, and a control terminal of the second transistor is controlled by a second selection bit.

Abstract: In an example, a system is disclosed for behavioral conditioning through games using a systematic process of cue deconstruction, reaction prompting, and the novel application of classical and operant conditioning techniques. The invention describes the design and production of specially configured clients with given conditioned and unconditioned stimuli for reinforcement and punishment, their provision through a server, and the collection of user metrics for behavioral profiling.

Abstract: A page request is received from a browser. A page script corresponding to the page request is allocated from a plurality of page scripts corresponding to the page request. The page script is transmitted to the browser for generation of a script execution parameter by execution of the page script by the browser. A page verification request is received from the browser, where the page verification request includes the script execution parameter. Whether a page verification request is expired is determined, where if the page verification request is expired, generating error prompt information indicating a page expiration. If the page verification request is not expired, whether the script execution parameter is valid, is determined. If the script execution parameter is valid, the validity is indicated, otherwise the page request is rejected.

Abstract: Systems and methods for encrypting a dataset are provided. The methods may include deriving an ephemeral key, and encrypting the dataset using the ephemeral key to produce a ciphertext. The ephemeral key, without being saved after the encrypting, may be re-derivable on demand and operable to decrypt the ciphertext.

Abstract: A digital clock generator for a digital clock domain interfaced to another clock domain through a FIFO, includes division selector circuitry to provide an input randomizing sequence of clock division factors, selected from a defined set of clock division factors corresponding to a target average clock division, and division arbitration circuitry to generate a drift-corrected randomizing sequence of clock division factors, based at least in part on the input randomizing sequence of clock division factors, and an accumulated drift correction signal. A clock drift control loop generates the accumulated drift correction signal, based at least in part on an accumulated clock drift relative to the target average clock division. Clock generation can be based on randomized division with the drift-corrected randomizing sequence of clock division factors. The drift-corrected randomizing sequence of clock division factors can be generated so that clock drift is bounded based on a FIFO depth.

Abstract: A system and method for providing a rapid, yet highly secure cryptographic application, to provide enhanced protection for digital data. At least one random value and Deterministic Sequence Generator (DSG) seeds are mathematically processed to create an initialization value (IV). The initialization value (IV) is mathematically processed with a user key to generate a set of initial DSG vectors. The initial DSG vectors are then inputted into a DGS component, and, using the initial DSG vectors, the DSG component creates an additive table and a substitution table. An initial internal working key is generated from the user key and the initial DSG vectors. An addition, an XOR and a substitution operation is applied to each byte of plaintext data in combination with the internal working key to enable the cipher to quickly and effectively encrypt the plaintext data. Once encrypted, the encrypted data may be stored in memory for subsequent use and/or transmitted to another party.

Abstract: A display driver IC which adjusts an oscillator frequency is provided. The display driver IC includes: a register map which stores a trim code, a window size, compensation information, and a compensation option; an oscillator which generates an oscillator clock based on the trim code; a timing controller which generates an internal synchronization signal based on the oscillator clock; a DSI block which outputs a first data valid signal which is activated based on a data clock and image data packet update; and a frequency compensating block which compares a periodic value of the oscillator clock calculated based on the data clock and the internal synchronization signal with a target periodic value and generates a compensation trim code obtained by compensating the trim code based on the compensation option, in accordance with the first data valid signal.

Abstract: A network device transparently intercepts HTTP transmissions between a user device and a web server. The network device stores user preference information, which allows the intermediate network device to apply the user preference information to retrieved content that is directed to the user's mobile device.

Abstract: In one embodiment, a device in a network obtains characteristic data regarding one or more traffic flows in the network. The device incrementally estimates an amount of noise associated with a machine learning feature using bootstrapping. The machine learning feature is derived from the sampled characteristic data. The device applies a filter to the estimated amount of noise associated with the machine learning feature, to determine a value for the machine learning feature. The device identifies a network anomaly that exists in the network by using the determined value for the machine learning feature as input to a machine learning-based anomaly detector. The device causes performance of an anomaly mitigation action based on the identified network anomaly.

Abstract: An oscillator circuit that includes a voltage source, a resistor, a capacitor, and a nonlinear device. The capacitor and the nonlinear device may be coupled in parallel with one another. The resistor may be coupled in series with the capacitor and the nonlinear device. The voltage source may be coupled in series with the resistor. The voltage source may supply the oscillator circuit with a direct current input signal. The nonlinear device may include an active layer coupled to a first electrode and a second electrode. In response to the direct current input signal, the oscillator circuit may output a spike train including a spike bunch.

Abstract: A network of storage units has a data path, which is at least a portion of the network. The network also has a dynamic time-varying or cycle-varying code generation unit and a code comparator unit that together make up an unlock signal generation unit; and a gateway storage unit. If the gateway storage unit does not store an unlock signal or the unlock signal generation unit does not generate and transmit an unlock signal, the gateway storage unit does not insert a data path segment in the data path. If the unlock signal generation unit is operated such that it generates an unlock signal, and it transmits that unlock signal to a gateway storage unit, and the gateway storage unit stores the unlock signal value, then the gateway storage unit inserts a data path segment into the data path.

Abstract: A method is provided for generating an elliptic curve cryptography key pair that uses two topologically identical pseudo-random number generators operating in parallel and in step with each other. One generator operates in the scalar number domain and the other generator operates in the elliptic curve point domain. Parallel sequences of pseudo-random elliptic curve points aG and corresponding scalars a are generated in this manner. A scalar a becomes a private key and an elliptic curve point aG is a public key of a key pair. Each generator is advanced by one iteration successively, and the isomorphic relationship ensures that the point domain generator always contains values which are multiples of the system base point according to values contained in the corresponding position in the number domain generator. In one embodiment, the pseudo-random number generators are each characterized as being lagged Fibonacci generators.

Abstract: An embedded device is provided that is configured to randomize execution time of a boot process of the embedded device performed responsive to a reset signal, wherein reset release time is nondeterministic. The embedded device may include a randomizer component configured to generate a timeout signal after a random interval, wherein to randomize execution time, the embedded device is further configured to execute a first portion of a reset process, signal the randomizer component to generate the timeout signal after a first random interval, wait for the timeout signal, and execute a second portion of the reset process responsive to the timeout signal.

Abstract: A method for securely providing a receiver unit with a replica pseudo-random noise code is provided. The replica pseudo-random noise code is provided in a restricted manner based on a result of an admissibility check. In order to carry out the admissibility check, values are recorded and are compared with predefined threshold values.

Abstract: A method for providing pink noise and improving computational efficiency including providing NS stochastic signal generators, generating a respective first random number g with variance ? and generating a respective second random number u for each respective stochastic signal generator at each discrete time n, comparing the respective second random number u with an update probability for the respective stochastic signal generator at each discrete time n, if the respective u is greater than the update probability, then not changing a respective output of the respective stochastic signal generator, if the respective u is less than or equal to the update probability, then updating the respective output of the respective stochastic signal generator to be equal to the first random number, and summing at each discrete time n the respective output of each of the NS stochastic signal generators.

Abstract: A clock circuit includes a circuit configured to use a regulated voltage on a regulated voltage node to provide a frequency modulated clock signal having a frequency vacillating between a first frequency and a second frequency. The clock circuit includes an auxiliary loading circuit coupled to the regulated voltage node and configured to selectively provide load compensation for a load difference of the circuit. The load difference is a difference between a first load corresponding to the first frequency and a second load corresponding to the second frequency. The circuit may include a frequency divider circuit configured to use the regulated voltage on the regulated voltage node to generate the frequency modulated clock signal by frequency dividing an input clock signal according to a divide value vacillating between a first divide value and a second divide value.

Abstract: Techniques for encrypting short-term data using layered encryption based on difficult to obtain secrets are described herein. Data that will be encrypted is designated as the source data for a first iteration of a layered encryption. An index indicates a data block within a large set of random data. The data block is encrypted and the encrypted data block is combined with the source data for the iteration to produce set of cryptographic data for the current iteration. The set of cryptographic data is used to generate cryptographic key data that is used to encrypt the index and the encrypted index is stored. The set of cryptographic data is then used as the source data for the next iteration.

Abstract: A random, number generating apparatus includes a first ring oscillator and a second ring oscillator, each having a quantity of delay elements different from, the other, a signal output unit, a selecting unit, a logic circuit, and a random signal output unit. The signal output unit receives a first signal output from the first ring oscillator and a second signal output from, the second ring oscillator and outputs the first signal or the second signal. The selecting unit selects a signal to be output from the signal output unit. The logic circuit receives the signal selected by the selecting unit and the output from the signal output unit and outputs an output signal. The random signal output unit receives the output signal output from the logic circuit and a clock signal and outputs a random signal.

Abstract: Certain aspects of the present disclosure generally relate to randomization of positioning reference signal (PRS) frequency offsets and muting patterns in long term evolution (LTE) for enhanced observed time difference of arrival (eOTDOA). According to certain aspects, a method is provided for wireless communications which may be performed, for example, by a base station (BS). The method generally includes randomly selecting at least one parameter used to determine a set of time-frequency resources for transmitting positioning reference signals (PRS) and transmitting PRS on the determined set of time-frequency resources. The user equipment (UE) may randomly select the at least one parameter used to determine the set of time-frequency resources to measure for the PRS from the BS and measure PRS on the determined set of time-frequency resources.

Abstract: A protected circuit includes a logic circuit having one or more input nodes and one or more output nodes. The logic circuit has a network of logic elements and one or more logic encryption elements. A logic encryption element includes a memory cell, such as a correlated electron switch for example, coupled with a configurable sub-circuit that is configured by a value stored in the memory cell to encrypt a signal or a signal path. A mapping of values at the one or more input nodes to values at the one or more output nodes corresponds to a desired mapping when values stored in the one or more memory cells match component values of a prescribed key vector. The memory cells may be programmed after fabrication of the circuit.

Abstract: The invention is, firstly, a cryptographic apparatus for encrypting unencrypted data, comprising an input module for inputting the unencrypted data and an output module for outputting encrypted data, and a key automaton (44) adapted for converting the unencrypted data into the encrypted data, and the key automaton (44) is an composition of automata said composition of automata having a set of states and a set of input signals identical to each other and being implemented as a permutation automaton without output signals, said composition of automata comprises at least one factor automaton without output signals, each of the unencrypted data and the encrypted data has a character set identical to each other, and the set of states and the set of input signals, respectively, consist of blocks obtained from all possible combinations of said character set, wherein the blocks are of a predetermined block length. The invention is, furthermore, a cryptographic apparatus for decrypting encrypted data.

Abstract: A method and system. Ciphertext is generated by applying both an initialization vector and an encryption key directly to plaintext. The initialization vector is combined with the ciphertext to generate encrypted data, by using an embedding rule to perform the combining.

Abstract: A device may include an integrated circuit and a jitter generator located on the integrated circuit. The jitter generator may include a random number generator to generate a random number in response to a clock input signal. The jitter generator may also include delay-causing circuitry to receive the clock input signals, where the delay-causing circuitry may create a delayed clock input signal. The jitter generator may also include a phase mixer to receive the random number, the delayed clock input signal, and the clock input signal, where the phase mixer additionally outputs a clock output signal having the clock input signal and having jitter.

Abstract: A radar warning receiver is disclosed. The radar warning receiver includes an antenna, a signal detection unit, a signal identification unit and an alarm. The antenna collects radio frequency (RF) signals. The signal detection unit is configured to generate a group of frequency and amplitude signals based on the collected RF signals. Specifically, the signal detection unit includes a pair of limiting amplifiers for converting the collected RF signals into corresponding pulsed output signals that track the actual frequency oscillations of the collected RF signals, and a pseudo-random noise generator for injecting noise into one of the limiting amplifiers. Based on the frequency and amplitude signals, the signal identification unit determines whether or not any of the collected RF signals includes a threat signal. The alarm is utilized to present a threat signal to a human operator.

Abstract: A method of providing security in a computer system includes producing a plurality of sub-keys from key material and a respective address of a memory location in a memory and possibly other information. The method may include mixing the sub-keys together using a binary tree of exclusive-or operations, and to produce an intermediate result. The method may include performing a scrambling operation on the intermediate result to produce a key with which a block of ciphertext may be produced. And the method may include performing a write operation to write the block of ciphertext at the memory location having the respective address. In this regard, the memory may include a window of memory locations each of which stores a respective block of ciphertext produced with a respective key that changes from memory location to memory location.

Abstract: A low PAPR sequence design method for a wireless communication system includes the following steps: setting relevant parameters of a designed sequence at first, then carrying out multiple iterations, generating multiple length-designated sequences having elements 0 and 1 and obeying the Bernoulli distribution of designated probability density parameters according to the parameters during primary iteration, screening the generated sequences according to the PAPRs of the sequences, updating the parameters of the next iteration based on the screened sequences, and finally mapping the sequence having the minimum PAPR to obtain a sequence with a low PAPR with elements of ?1 and 1 after terminating the iterations. Compared with the prior art, the present invention allows the design of a sequence with a low PAPR with an arbitrary length, and the sequence only contains +1 and ?1 as elements and has good autocorrelation performance.

Abstract: An oscillator includes a reference current generating circuit, a modulator circuit, and an oscillating circuit. The reference current generating circuit generates a first reference current. The modulator circuit generates a modulation current according to the first reference current and a feedback voltage, wherein the modulation current is negatively correlated with the feedback voltage. The oscillating circuit receives at least the modulation current, and generates an oscillating signal with an oscillating frequency according to at least the modulation current, wherein the oscillating frequency is varied according to the modulation current. The oscillator may be employed by a direct current (DC)-to-DC voltage converter.

Abstract: A tunable tunnel diode based digitized noise source includes a digitized noise source for producing a sequence of random digital signals. The digitized noise source includes a tunnel diode for providing a current signal that includes quantum shot noise. The digitized noise source can also include a current-to-voltage converter coupled to the tunnel diode for converting the current signal to a voltage signal, a filtering and amplification circuit coupled to the current-to-voltage converter for producing an amplified voltage signal, and a digitization circuit for converting the amplified voltage signal into the sequence of digital signals that represents random bits. The tunable tunnel diode based digitized noise source further includes an entropy estimator coupled to the output of the digitization circuit for estimating an entropy of the sequence of digital signals and for providing a feedback bias voltage to the tunnel diode.

Abstract: Aperiodic clock generation with clock spur suppression is based on cascaded randomizers, such as for mixed signal devices. A clock generator circuit includes an input node to receive the input periodic clock signal having an input-clock frequency. A first randomizer circuit coupled to receive the input clock signal from the input node, to perform signal randomization to suppress spurious signal content associated with (a) the input clock signal, and (b) the first randomizer circuit, and to generate an intermediate clock signal. A second concatenated randomizer circuit is coupled to receive the intermediate clock signal, to perform signal randomization to suppress spurious signal content associated with (a) the intermediated clock signal, and (b) the second randomizer circuit, and to generate an aperiodic output clock signal having a pre-defined average output-clock frequency that is less than the input-clock frequency. Example randomizers are a delta-sigma divider and a pulse swallower (in any order).

Abstract: Example embodiments disclosed herein relate to noise level estimation. A method for noise level estimation is disclosed. The method includes, responsive to an increase of a signal level of a noise signal, calculating an impulsive noise probability of the noise signal, the impulsive noise probability indicating a likelihood that the noise signal is an impulsive noise. The method also includes determining a variable smoothing factor for noise level estimation based on the impulsive noise probability, the variable smoothing factor being associated with a previous estimated level of the noise signal. The method further includes smoothing the noise signal with the variable smoothing factor so as to determine a current estimated level of the noise signal. Corresponding system and computer program products are also disclosed.

Abstract: A method and system of enforcing a computer policy uses a central server to manage user profiles, policies and encryption keys. The server securely supplies the keys to client devices only after checking that the policy has been complied with. The checks include both the identity of the user and the machine identity of the client device. The keys are held in a secure environment of the client device, for example in a Trusted Platform Module (TPM), and remain inaccessible at all times to the end user. Theft or loss of a portable client device does not result in any encrypted data being compromised since the keys needed to decrypt that data are not extractable from the secure environment.

Abstract: A switching power converter may include a power switch coupled to a primary winding of a transformer, and a primary controller configured to turn on and off the power switch, a synchronous rectifier switch coupled to a secondary winding of a transformer, and a synchronous rectifier controller configured to turn on and off the synchronous rectifier switch. The synchronous rectifier controller may monitor a voltage across the synchronous rectifier switch. The synchronous rectifier controller may determine a period of a resonant oscillation of the voltage across the synchronous rectifier switch following at least one cycling off of the synchronous rectifier switch. The synchronous rectifier controller may adjust the minimum off-time period for the synchronous rectifier switch based on the period of the resonant oscillation. The synchronous rectifier controller may adaptively adjust a minimum off-time period for the synchronous rectifier switch.

Abstract: The present invention provides a method of generating a sequence of pseudo-random numbers which are difficult to predict. The method includes: (i) generating a plurality of candidate pseudo-random numbers by a respectively corresponding plurality of (differently structured) linear feedback shift registers; (ii) generating a “selector number” from one or more additional linear feedback shift registers; and (iii) selecting a candidate number from the plurality of candidate numbers, based on the “selection number” to produce a selected pseudo-random number for output.

Abstract: The present invention provides a method of generating a sequence of pseudo-random numbers which are difficult to predict. The method includes: (i) generating a plurality of candidate pseudo-random numbers by a respectively corresponding plurality of (differently structured) linear feedback shift registers; (ii) generating a “selector number” from one or more additional linear feedback shift registers; and (iii) selecting a candidate number from the plurality of candidate numbers, based on the “selection number” to produce a selected pseudo-random number for output.

Abstract: An apparatus, system, and method are provided for affording digital to analog converter (DAC) quantization noise that is independent of an input signal. In operation, an input signal for a DAC is received. Further, a particular signal is added to the input signal for the DAC, such that an output signal of the DAC includes quantization noise that is independent of the input signal (e.g. includes white noise, etc.), as a result of the particular signal being added to the input signal for the DAC.

Abstract: A system for creating protected functional descriptions of integrated circuits provides encrypted gate delay information preventing deduction of gate function from gate delay but allowing simulation of the integrated circuit with accurate propagation delay calculation. Individual gate delay values may be modified so that they obscure actual gate delays but so that the modified individual gate delays total to equal the actual cumulative gate delay along a given data propagation path.

Abstract: An image sensor pixel noise measurement circuit includes a pixel array on an integrated circuit chip. The pixel array includes a plurality of pixels including a first pixel to output a first image data signal, and a second pixel to output a second image data signal. A noise amplification circuit on the integrated circuit chip is coupled to receive the first and second image data signals from the pixel array. The noise amplification circuit is coupled to output an amplified differential noise signal in response to the first and second image data signals received from the pixel array. A fast Fourier transform (FFT) analysis circuit on the integrated circuit chip is coupled to transform the amplified differential noise signal output by the noise amplification circuit from a time domain to a frequency domain to analyze a pixel noise characteristic of the pixel array.

Abstract: An apparatus for generating a bandwidth extended signal from an input signal includes a patch generator and a combiner. The input signal is represented for first and second bands by first and second resolution data, respectively, the second resolution being lower than the first. The patch generator generates first and second patches from the first band of the input signal according to first and second patching algorithms, respectively. A spectral density of the second patch generated using the second patching algorithm is higher than a spectral density of a first patch generated using the first patching algorithm. The combiner combines both patches and the first band of the input signal to obtain the bandwidth extended signal. The apparatus scales the input signal according to the first and second patching algorithms or scales the first and second patches, so that the bandwidth extended signal fulfills a spectral envelope criterion.

Abstract: An apparatus for generating a bandwidth extended signal from an input signal includes a patch generator and a combiner. The input signal is represented for first and second bands by first and second resolution data, respectively, the second resolution being lower than the first. The patch generator generates first and second patches from the first band of the input signal according to first and second patching algorithms, respectively. A spectral density of the second patch generated using the second patching algorithm is higher than a spectral density of a first patch generated using the first patching algorithm. The combiner combines both patches and the first band of the input signal to obtain the bandwidth extended signal. The apparatus scales the input signal according to the first and second patching algorithms or scales the first and second patches, so that the bandwidth extended signal fulfills a spectral envelope criterion.