Abstract: A time-to-digital converter (TDC) uses voltage as a representation of time offset. A voltage change is induced over a time period from a start signal to a stop signal. The final voltage is then measured, and the voltage measurement is mapped to a time value representing the time between the start signal and the stop signal. The voltage change can be increasing or decreasing, e.g., by charging or discharging a capacitive circuit between the start signal and the stop signal. The voltage can be measured using an analog-to-digital converter (ADC) or other voltage measurement circuit. The voltage measurement can be mapped to the time value in any manner, such as, for example, using a transfer function or using a mapping table that provides a time value for each possible voltage measurement value.

Abstract: Systems, apparatus and methods are provided for compressing data. A method may include receiving an input data block to be compressed, determining numbers of occurrences for distinct symbols in the input data block, generating reduced numbers of occurrences for the distinct symbols based on the numbers of occurrences for the distinct symbols and encoding the input data block using the reduced numbers of occurrences as probability distribution of the distinct symbols in the input data block.

Abstract: The disclosure provides a system, comprising: a MEMS capacitive transducer, comprising one or more first capacitive plates coupled to a first node and one or more second capacitive plates coupled to a second node; biasing circuitry coupled to the first node, operable to provide a biasing voltage to the one or more first capacitive plates; and test circuitry coupled to the second node, operable to: selectively apply one or more current sources to the second node, so as to charge and discharge the MEMS capacitive transducer and so vary a signal based on a voltage at said second node between an upper value and a lower value; determine a parameter that is indicative of a time period of the variation of the signal; and determine a capacitance of the MEMS capacitive transducer based on the parameter that is indicative of the time period.

Abstract: A method can include, amplifying an analog input signal to generate an amplified analog signal; modulating the amplified analog signal into a digital data stream; filtering the digital data stream with a first digital filter to generate a first filtered data stream, and selectively changing a gain of the amplifier in response to the first filtered data stream. While the digital data stream is filtered with the first digital filter, the digital data stream is filtered with a second digital filter to generate a second filtered data stream. An output digital value corresponding to the analog input signal in response to the second filtered data stream. Corresponding systems and devices are also disclosed.

Abstract: An analog to digital converter (ADC) is disclosed. The ADC includes a DAC which generates a first signal based on an analog input and a digital input word, and a comparator which generates a comparator output having a value corresponding with a sign of a difference between first and second signals. During a first time period, the second signal is equal to a reference signal, the first signal is equal to an analog input, and the comparator generates a first comparator output. During a second time period, the second signal is equal to the reference signal, the first signal is equal to a the analog input plus a predetermined signal, and the comparator generates a second comparator output. A SAR logic circuit generates the digital input word for the DAC based on the first and second comparator outputs.

Abstract: A comparison circuit includes an input interface configured to receive input signals and an output interface configured to deliver an output signal. A comparator is coupled between the input interface and the output interface. An amplifier is coupled between the input interface and the comparator. A neutralization circuit is configured to neutralize any change of state of the output signal starting from each moment in time at which the change of state of the output signal occurs and lasting for a second duration of propagation that compensates for a duration of propagation of signals within the amplifier.

Abstract: A semiconductor device includes a trimming circuit for a power management circuit. The trimming circuit includes an analog to digital converter (ADC) circuit with a comparator circuit, a successive approximation register (SAR) circuit having an input coupled to an output of the comparator circuit, a control circuit coupled to the SAR circuit, a digital to analog converter (DAC) circuit having inputs selectively couplable to digital output signals of the SAR circuit and an output coupled to a first input of the comparator circuit, and a variable resistance circuit configured to be selectively coupled to output signals of the ADC circuit.

Abstract: A driver arrangement (10) comprises a digital controller (11) that is configured to receive a digital input signal (SDI) and a driver (12) that comprises a driver input (14) and a driver output (15) and is configured to provide an analog output signal (SANO) at the driver output (15). The driver arrangement (10) comprises a coupling circuit (13) that comprises a digital-to-analog converter (19) and a feedback circuit (24). The digital-to-analog converter (19) comprises a converter input (20) coupled to the digital controller (11) and a converter output (21) coupled to the driver input (14). The feedback circuit (24) is coupled to the driver output (15) and to a feedback input (17) of the digital controller (11).

Abstract: The invention relates to a method for starting and stopping an internal combustion engine of an industrial truck, wherein said industrial truck comprises an electric starter and an auxiliary hydraulic starter. Said method comprises steps of testing safety conditions (103), detecting instructions or requests from the operator (104), and testing auxiliary hydraulic starting conditions (105).

Abstract: Successive approximation register (SAR) and ramp analog to digital conversion (ADC) methods, systems, and apparatus are disclosed. An analog voltage signal may be converted into a multiple bit digital value by generating bits of the multiple bit digital value by performing a SAR conversion on the analog voltage signal, where the bits corresponding to a SAR voltage level, and generating other bits of the multiple bit digital value by performing one or more ramp conversions on the analog voltage signal, the ramp conversion comparing the analog voltage signal to a ramp of voltage levels based on the SAR voltage level. The SAR and ramp ADC can provide multi-sampling using one SAR conversion and multiple ramp conversions. The SAR can set the voltage level of a first ramp of a multiple ramp conversion, which can then be used to preset the voltage level prior to subsequent ramps.

Abstract: A telecommunications system is provided that can re-sample a digitized signal at a resample rate that is based on one or more factors to better utilize bandwidth. The factors can include the bandwidth of the signal that the digitized signal represents, the amount of bandwidth owned or used by the carrier, the full bandwidth of the designated RF band, the bandwidth of the serial link, the frame length of the serial link, the segmentation of the frames on the serial link, and the capability of the equipment at the receiving end of a serial link. The re-sampled signal can be transmitted to another unit that is remote to the unit transmitting the signal. The other unit can include a re-sampling device that restores the re-sampled signal to a digital signal that can be converted to an analog signal for wireless transmission.

Abstract: The present disclosure is directed dynamic compression/decompression (codec) configuration. In general, a device may include a codec configuration module to determine a configuration for use by the codec based on configuration criteria. The configuration criteria may include, for example, data characteristic information, system condition information and user expectation information. The configuration information may be used to select a codec configuration from one or more available codec configurations. For example, a benchmark module also in the device may determine the available codec configurations. After a codec configuration has been selected, it may be set in the codec. It may also be possible for the codec configuration module to monitor for changes in device operation (e.g., changes in the configuration criteria) and to update the codec configuration based on the monitored changes.

Abstract: A fieldbus adaptor connected between a fieldbus that handles a digital signal and a field device that handles an analog signal, the fieldbus adaptor comprising a first connection unit detachably connected to the fieldbus, a second connection unit detachably connected to the field device, and a conversion unit provided between the first connection unit and the second connection unit, the conversion unit bidirectionally converting the digital signal handled by the fieldbus and the analog signal handled by the field device.

Abstract: A fieldbus adaptor connected between a fieldbus that handles a digital signal and a field device that handles an analog signal, the fieldbus adaptor comprising a first connection unit detachably connected to the fieldbus, a second connection unit detachably connected to the field device, and a conversion unit provided between the first connection unit and the second connection unit, the conversion unit bidirectionally converting the digital signal handled by the fieldbus and the analog signal handled by the field device.

Abstract: A wireless headset with an integral display is provided, the headset capable of communicating via a wireless network to a cellular telephone, cellular telephone adaptor, land-line telephone, land-line telephone adaptor, computer, personal digital assistant, or other device capable of communicating via the wireless network. The wireless headset of the invention includes an input transducer (e.g., a microphone), an output transducer (e.g., a speaker), a wireless networking subsystem and a controller/controller interface. The headset may also include means for attaching the headset to the user in order to allow hands-free operation. The integral display, fabricated using any of a variety of suitable technologies, allows headset and system information to be displayed (e.g., battery levels, signal levels, call status, caller identification, incoming call alert, current time, current date, elapsed use time, etc.). The integral display can also be used to aid headset/system configuration (e.g.

Abstract: A transceiver includes an analog-to-digital converter (ADC) having an embedded processing circuit and an embedded digital-to-analog converting (DAC) unit. The ADC is arranged to convert an analog input signal into a digital output signal during a first operational phase of the transceiver. The embedded processing circuit is arranged to generate a digital code according to the analog input signal and an analog signal. The DAC unit is coupled to the embedded processing circuit, wherein the embedded DAC unit is arranged to convert the digital code into the analog signal during the first operational phase, and is arranged to convert a digital input signal into an analog output signal during a second operational phase of the transceiver.

Abstract: Embodiments of the present invention provide systems, devices and methods for modeling and correcting amplitude and quadrature phase errors generated within analog components of a receiver. A frequency-dependent correction method is employed that closely tracks the frequency dependent nature of the mismatch between the I and Q polyphase filter responses. In particular, digital correction is performed on a signal based on a modeled error function generated during a calibration of the receiver.

Abstract: In the power supply apparatus which performs voltage conversion of an input voltage (Vbat), with a predetermined set voltage as a target value, and outputs the converted voltage, a boost ratio setting unit sets a boost ratio (XCP) of the charge pump circuit based on the input voltage (Vbat) and a predetermined set voltage. A voltage adjustment unit is a regulator circuit, and adjusts voltage (Vx) so that output voltage (Vout) of the charge pump circuit approaches the set voltage. An output voltage setting unit generates a predetermined set voltage as a digital value (Dset). An A/D converter performs analog-digital conversion of the input voltage (Vbat). The boost ratio setting unit sets the boost ratio based on a result of comparing an input voltage (Ddet) that has undergone analog-digital conversion, and the set voltage (Dset).

Abstract: A radio communication device performs baseband processing by subjecting a received signal to an AD conversion at a predetermined sampling frequency and converting a digital signal resulting from the AD conversion into a baseband signal by frequency conversion. The device includes a frequency converting unit configured to convert the resulting digital signal into a complex baseband signal. The device further includes a waveform shaping unit configured to subject the baseband signal to waveform shaping, and a down-sampling unit configured to subject the baseband signal to sample discrete reduction.

Abstract: Embodiments described herein may include example embodiments of a method, article and apparatus for compressing data utilizing a combinatorial encoder with specified occurrences which may be used for communicating between two or more components connected to an interconnection medium (e.g., a bus) within a single computer or digital data processing system, and/or for communication between computing platforms via a network or other interconnection medium.

Abstract: A re-configurable circuit acts as an Analog-to-Digital Converter (ADC) and as a digital-to-analog converter (DAC). An array of binary-weighted capacitors stores an analog input. Switches connect different capacitors in the array to fixed voltages that cause charge-sharing with a terminal capacitor. The voltage of the terminal capacitor is compared by a re-configurable comparator stage for each different combination of the capacitors. The comparison results are analyzed to determine the closest digital value for the analog input. In DAC mode, the array capacitors are switched based on an input digital value. The switched capacitors connect to a charge-sharing line to generate an analog voltage that is applied to the re-configurable comparator stage. A differential amplifier generates a buffered analog voltage that is fed back to the other input of the re-configurable comparator stage for unity gain. The gain of the re-configurable comparator stage adjusts for ADC and DAC modes.

Abstract: Antenna system connectable to a base station, the antenna system comprising a digital radio unit connectable to at least one antenna element, wherein the digital radio unit comprises: at least one micro radio for receiving/sending digital radio signals having a digital down-converter/a digital up-converter and a digital signal converter. The at least one micro radio converts the digital radio signals to analogue RF (radio frequency) signals and vice versa. The at least one micro radio has at least one hub for processing digital radio signals and control signals and for routing said digital radio signals and control signals via at least one serial link and at least one interface. The at least one serial link is provided between the at least one hub and the at least one micro radio.

Abstract: There is provided a signal processor with a plurality of antennas connected for transmitting and receiving wireless signals, including a plurality of analog reception processing units, AD converters, DA converters, and analog transmission processing units, wherein each of the analog reception processing units converts the wireless signal received through the antenna into an analog baseband signal and outputs the signal to the AD converter, each of the DA converters converts the digital baseband signal into analog format and outputs the signal, and each of the analog transmission processing units shifts the frequency band of the analog baseband signal output from the DA converter to the high frequency side. The signal processor further includes a transmission switch which switches among the DA converters respectively connected to the analog transmission processing units and a reception switch which switches among the AD converters respectively connected to the analog reception processing units.

Abstract: The performance (compression ratio) of an entropy coding compressor can be improved by separating its output into two streams: encoded output symbols compressed according to a probability model, and literal symbols that were not present in the probability model when the corresponding input symbol was to be encoded. The literal symbols are collected into a group and compressed separately. The compressed literals are stored at a discernable place relative to the encoded output symbols (e.g., at the beginning or end of the sequence of encoded output symbols).

Abstract: Nuclear spectroscopy systems have improved over the course of time especially with the advent of digital pulse processing. One disadvantage of digital processing, however, is that it has eliminated the older, universally compatible interface standard of analog signals. Digital component interfaces are often defined by computer software, protected by copyright and unique to a single manufacturer. Consequently, all components of an entire spectroscopy system must be from a single manufacturer. This not only dictates system wide component replacement, but also impedes optimization that would otherwise occur were component compatibility the rule rather than the exception. The present innovation describes a method and apparatus to relieve the present incompatibility between digital components of a nuclear spectroscopy system that are supplied by more than one manufacturer.

Abstract: A discrete-time programmable-gain analog-to-digital converter (ADC) input circuit with multi-phase reference application, provides a high input impedance level substantially independent of input capacitor size and input signal gain setting. An input voltage is sampled at the common mode voltage of the input, using one or more reference capacitor(s) that has been charged in a previous clock phase to the reference feedback voltage. The sampled input voltage is then applied in series with a quantizer-controlled reference voltage to the input of an integrator in a second clock phase. The summing mode of the integrator is maintained at the reference common-mode voltage. Since the charge pulled from the input voltage source is substantially determined only by the quantization error and input noise voltage, the circuit has a high signal input impedance. Since the input voltage source is sampled with respect to its common-mode voltage, the common-mode input impedance is also high.

Abstract: A combined AD/DA converting apparatus includes an input signal selection circuit configured to select one analog signal out of a plurality of analog input signals based on an input selection signal; an input sample hold circuit configured to sample and hold the analog input signal; a DA converter configured to convert a digital signal into an analog signal; a comparator circuit configured to output a comparison signal that indicates a size relation between the analog input signal and the analog signal; a sequential comparison register configured to define sequentially each place of a digital signal stored in the register based on the comparison signal; and a selection circuit configured to output the digital signal to the DA converter when the conversion selection signal indicates AD conversion, and to output the digital input signal to the DA converter when the conversion selection signal indicates DA conversion.

Abstract: Method and apparatus for playing analog audio in an electronic audio system having multiple audio codecs, only one of which has a direct hardware connection to the analog audio source. First analog audio data is received from the analog audio source at a first audio codec, and converted to digital audio data using the first audio codec. The digital audio data is stored in a memory, and read back from the memory, transferred to a second audio codec. The digital audio data is then converted to second analog audio data using the second audio codec, and output from the second audio codec. An audio controller may be used to store the digital audio data in a loopback buffer within the memory, read the digital audio data from the loopback buffer, and may further be programmed to operate in a prepare loopback state, a loopback running state, and a recording state.

Abstract: A signal converting apparatus for integrating an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC) and an integration unit thereof are provided. The present invention integrates ADC and DAC, that do not operate simultaneously, into a signal converting apparatus (SCA), wherein a control signal decides whether an analog-to-digital mode or a digital-to-analog mode is selected. By sharing the operational amplifiers and other components in the SCA, the chip area and the cost are significantly reduced. In addition, in the integration unit, by switching a plurality of capacitor sets with various capacitances, the capacitance coefficients required for switching ADC and DAC are obtained.

Abstract: An arithmetic code decoding apparatus including a context index predictor which predicts a context index, a pipeline arithmetic code decoder which executes a decoding process of the bitstream using the predicted context index and outputs a decoded symbol based on prediction, a context index generator which receives the previous decoded symbols, the syntax element, and context information of the bitstream, and generates a correct context index, a binarization table searcher which searches the binarization table using the decoded symbol for a value of the syntax element, and a prediction failure detector which outputs a prediction failure signal when the two context indices do not match, wherein when the prediction failure signal is output, the pipeline arithmetic code decoder flashes the decoding process executed using the predicted context index, re-executes a decoding process using the correct context index, and outputs a correct decoded symbol.

Abstract: CMP methods in which a polishing pad is moved relative to a wafer and a retainer ring implement instructions for applying required pressure to the wafer for CMP operations. Accuracy of computations of the pressures, and of conversion of the pressure to force, is improved without use of high resolution components, such as high resolution digital devices. Such improved accuracy is achieved using both digital and analog operations, and by converting values of required pressure or force from one set of units to a second set of units and then back to the first set of units. A quantization process is performed using data processed by average resolution digital devices. The process transfers both pressure/force scale and pressure/force set point data between separate processors to obtain computed values of pressure and force having acceptable accuracy, such that quantization errors are eliminated or significantly reduced.

Abstract: A DAC/ADC system for generating reference clocks for DAC/ADC by a look-up table method. The DAC/ADC system includes a sampling signal generator, a DAC, and an ADC. The sampling signal generator generates first and second sampling signals according to first and second reference clocks by a look-up table method, respectively. The DAC receives a digital input signal and converts it into an analog output signal according to the first sampling signal. The ADC receives an analog input signal and converts it into a digital output signal according to the second sampling signal.

Abstract: An Analog-to-Digital-Converter (ADC) converts an analog signal to digital data. The ADC includes a modulator, a decimation filter, and a time dither clock reduction circuit. The modulator receives the analog signal and a feedback signal and, based there upon, produces a modulated signal at a modulator clock rate. The decimation filter couples to the modulator, receives the modulated signal, and decimates and filters the modulated signal to produce the digital data. The time dither clock reduction circuit receives the modulated signal and provides the feedback signal to the modulator. The time dither clock reduction circuit applies both clock reduction and time dithering to the modulated signal to produce the feedback signal. At each modulator clock cycle, the time dithering clock reduction circuit considers modulated signals for a dithering factor, N, previous modulator clock cycles and a modulated signal for a current modulator clock cycle.

Abstract: CMP systems and methods in which a polishing pad is moved relative to a wafer and a retainer ring implement instructions for applying required pressure to the wafer for CMP operations. Accuracy of computations of the pressures, and of conversion of the pressure to force, is improved without use of high resolution components, such as high resolution digital devices. Such improved accuracy is achieved using both digital and analog operations, and by converting values of required pressure or force from one set of units to a second set of units and then back to the first set of units. A quantization process is performed using data processed by average resolution digital devices. The process transfers both pressure/force scale and pressure/force set point data between separate processors to obtain computed values of pressure and force having acceptable accuracy, such that quantization errors are eliminated or significantly reduced.

Abstract: An A/D converter has a successive approximation register having a plurality of A/D registers each corresponding to one of A/D inputs. A capacitor in a comparator is charged by a voltage determined based on a value held in an A/D register corresponding to an A/D input to be A/D converted before starting A/D conversion of the A/D input, thereby reducing noise generated at the time of selecting A/D inputs to enhance A/D conversion accuracy.

Abstract: Monitoring a converter (1) includes detecting whether a value of an input variable (2) for the converter (1) assumes a first prescribed input reference value (41) and checking whether an output variable (3) from the converter (1) likewise assumes a corresponding, second prescribed output reference value (61). This means that the operation of the converter is tested only at occasional instants, specifically only using individual, prescribed values. The fact that only prescribed values (41, 61) are compared with instantaneous values of the input and output variables (2, 3) means that the invention can be implemented using very simple means. The method is particularly suitable for monitoring the operation of a converter (1) in a control or protective device for an electrical switchgear assembly. In this context, when a malfunction in the converter (1) is detected, all protective functions which are dependent on the converter (1) are preferably turned off.

Abstract: A non-uniform analog-to-digital converter (ADC) produces digital output data representing the magnitude of an analog input signal having a non-uniform magnitude probability distribution. The digital output data represents the analog input signal with relatively high resolution for the input signal's more frequently occurring magnitudes and with relatively lower resolution for the input signals less frequently occurring magnitudes.

Abstract: An integrated circuit chip for interfacing a digital computer to sensors and controlled devices can be configured to accept and provide a variety of analog and discrete input and output signals. The circuit includes a plurality of signal conditioning cells, a plurality of signal conversion cells, and input and output signal multiplexors.

Abstract: The present invention provides an isolated analog-to-digital converter system including an analog-to-digital subsystem including an analog-to-digital converter for converting an analog signal to a digital control stream. A microcontroller subsystem provides power, clock signals, and control signals as a single combined signal for the analog-to-digital converter, the single combined signal comprising a pulse train having a nominal frequency and having control pulse width modulated thereon. An isolation subsystem electrically isolates the analog-to-digital converter subsystem from the microcontroller subsystem. The isolation subsystem includes a first transformer, coupled to the microcontroller subsystem, which receives the single combined signal as a differential input signal. A full-wave rectifier, coupled to the first transformer, rectifies the differential input signal to produce at least one power supply voltage for the analog-to-digital converter subsystem.

Abstract: Huffman encoding, particularly from a packed data format, is simplified by using two different table formats depending on code length. Huffman tables are also reduced in size thereby. Decoding is performed in reduced time by testing for the length of valid Huffman codes in a compressed data stream and using an offset corresponding to a test criterion yielding a particular test result to provide a direct index into Huffman table symbol values while greatly reducing the size of look-up tables used for such a purpose.

Abstract: A low power sample rate converter adapted for use with a telecommunications system transceiver. The sample rate converter includes a first circuit that provides an input signal characterized by a first sample rate and a delayed version of the input signal. A second circuit periodically multiplies, at a second sample rate, samples in the input signal by a first predetermined coefficient in accordance with a predetermined transfer function and provides a first signal in response thereto. A third circuit periodically multiplies, at the second sample rate, samples in the delayed version of the input signal by a second predetermined coefficient in accordance with the predetermined transfer function and provides a second signal in response thereto. A fourth circuit combines the first signal and second signal providing a rate-converted version of the input signal as an output signal in response thereto.

Abstract: The invention relates to a changeover device which uses both analog and digital signals as input signals and supplies an analog output signal. The changeover device contains a digital-to-analog converter whose output level is adjustable. Matching to the level of the analog input signal is thus achieved. Preferred applications of the invention are picture-in-picture insertions in which an additional picture in analog form is intended to be inserted into a main picture in digital form.

Abstract: A semiconductor integrated circuit for performing data transfer integrated circuit includes a first circuit, a second circuit, and first and second data converters. The first circuit outputs data of a plurality of bits. The second circuit receives the data from the first circuit via a data bus. The first data converter converts the data from the first circuit by a first conversion rule and outputs the data to the data bus. The second data converter converts the data from the data bus back to original data by a second conversion rule and outputs the data to the second circuit.

Abstract: An electronically calibrated sensor (100) includes a sensing element (102) with an output coupled to a signal conditioning circuit (104). The signal conditioning circuit (104) is adapted to be highly computationally efficient and operable for compensating for temperature and part-to-part variation on the sensing element output for providing a useable sensor output signal. The signal conditioning circuit (104) includes an analog-to-digital/digital-to-analog (ADC/DAC) conversion device (112). The ADC/DAC (112) is operable to perform both analog input signal analog-to-digital conversion and digital output signal digital-to-analog conversion. The ADC/DAC (112) is further adapted to provide analog control signals to input signal conditioning circuits (104, 106).

Abstract: A self-calibrating reversible pipeline analog to digital converting architecture configured to convert an input analog signal to an output digital signal and further to convert an input digital signal to an output analog signal is disclosed. The reversible pipeline architecture self-calibrates to compensate for adverse effects upon the linearity during signal conversion using a digital correction procedure. The same digital correction coefficients are used during both analog to digital conversion as well as during digital to analog conversion. The self-calibrating reversible converting architecture includes a reduced gain stage to create the necessary redundancy for the digital correction. Furthermore, the self-calibrating reversible converting architecture includes an overflow reduction stage to generate redundancy for the digital correction.

Abstract: An analog-to-digital converter circuit is disclosed that is capable of converting both positive and negative analog input signals, and that is capable of operating as either an analog-to-digital converter or a digital-to-analog converter. The converter includes a modifying filter, a series of substantially identical converter stages, and a restoring filter. An original reference signal is provided, coupled to a resistor array to provide a stage reference signal to each converter stage that is equivalent to the value of the bit of an N-bit binary word corresponding to that stage. An incoming analog signal is modified to ensure that it is positive before applying it in parallel to the converter stages. Each converter stage compares the modified analog signal to the sum of its own reference signal and the value of all stage reference signals for prior converter stages where the digital output of the stage was a binary "1.

Abstract: An analog-to-digital converter circuit is disclosed that is capable of converting both positive and negative analog input signals, and that is capable of operating as either an analog-to-digital converter or a digital-to-analog converter. The converter includes a modifying filter, a series of substantially identical converter stages, and a restoring filter. An original reference signal is provided, coupled to a resistor array to provide a stage reference signal to each converter stage that is equivalent to the value of the bit of an N-bit binary word corresponding to that stage. An incoming analog signal is modified to ensure that it is positive before applying it in parallel to the converter stages. Each converter stage compares the modified analog signal to the sum of its own reference signal and the value of all stage reference signals for prior converter stages where the digital output of the stage was a binary "1.

Abstract: Using only one R2R network, driven by a digital logic, it is possible to implement both a D/A and A/D converter, An existing stabilized voltage V.sub.cc is used instead of a separate reference voltage source. The D/A and A/D converter is calibrated with this voltage and an operational amplifier circuited as a comparator. Starting with the known voltage value V.sub.cc and the assigned bit combination, it is possible to measure analog voltages from analog voltage sources using further operational amplifiers circuited as comparators.

Abstract: In a codec having a coding section A/D converting an analog signal into a digital signal, and a decoding section D/A converting a received digital signal into an analog signal, a decoding timing generating circuit (50) is provided to generate a D/A conversion timing signal (S50) on the basis of a clock signal (S30b) generated by a coding PLL circuit (30) and a reading completion signal (S61a) supplied from decoding controller (61). In synchronism with this signal (S50), a D/A converter 62 converts the digital signal Di read by the decoding controller 61, into an analog signal, and sends it to the decoding filter 63. The decoding filter (63) operates synchronism with the clock signal (S30b) generated by the coding PLL circuit (30) to filter the output of the D/A converter (62), and outputs it as the analog signal (Ao).

Abstract: There is provided a signal converting apparatus using a semiflash type A/D converter comprising an analog-digital (A/D) converting section and a digital-analog (D/A) converting section, wherein the apparatus has an input switching circuit for switching in a manner such that an input of the D/A converting section is set to a conversion output of the A/D converting section during the A/D converting operation and the input of the D/A converting section is set to an external input during the D/A converting operation.