Abstract: A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 4/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.

Abstract: The present disclosure provides a data shifting operation apparatus having multiple operation modes that includes a preprocessing circuit, a first and a second shifting circuits and a multiplexer. The preprocessing circuit stores an input data group, having a data amount equal to a desired data amount M, to an under-operation data group, having the data amount equal to a maximum usage data amount N, from a most significant bit, and receives a shift amount S to calculate a total shift amount. The first and the second shifting circuits respectively cyclically shift the under-operation data group for the shift amount and the total shift amount to generate a first and a second shifted data groups. The multiplexer selects S data from the most significant bit of the second shifted data group and (M?S) data from the (N?S)-th bit of the first shifted data group to output a final shifted data group.

Abstract: Implementing a database system using a plurality of sequentially ordered drives to store sequential portions of columns of the database, but where the database system is usable by a system configured for use with in-memory database systems. The method includes loading one or more columns of a database into main memory of a computing system as a table based database. The method further includes dividing a column of the database into sequential portions. Each of the sequential portions is of sufficient size to create efficient transfers using hard disk controllers to transfer an entire sequential portion. The method further includes writing each of the sequential portions sequentially onto sequentially ordered drives in a round robin fashion such that sequential portions of the column are on sequential drives.

Abstract: A computer-implemented method is provided for determining parallel process paths in process data. In a first step, a status hierarchy is generated from process steps stored in a storage means, wherein the process steps are read from the storage means and are added to the status hierarchy, and wherein for each added process step, a predecessor/successor relation is added to at least one further process step to the status hierarchy. In a second step, a process hierarchy of the process instance comprising nodes and edges is deduced from the process steps stored in the status hierarchy and the respective predecessor and/or successor relations.

Abstract: There is provided a computer-implemented method of optimizing a query. An exemplary method retrieves a subset of rows from a sample table based on a query for a table associated with the sample table. The query specifies the table. The sample table is generated in a previous optimization of the query. The sample table includes a scrambled, random selection of rows from the table. A cardinality of the table is determined based on the subset. A query plan is generated based on the query and the cardinality.

Abstract: A digital communication interface includes a deserializer module, a gearbox module, and a parallel communication channel connecting the gearbox module to the deserializer module. The deserializer module has a fixed deserialization factor. The gearbox module has a temporal translation factor to change bit-length of words received through the parallel communication channel to bit-length suitable for a downstream data path.

Abstract: A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.

Abstract: Various aspects described herein relate to managing a soft buffer for decoding hybrid automatic repeat/request (HARQ) based transmissions in wireless communications. A legacy soft buffer size of a legacy soft buffer can be determined for decoding HARQ based transmissions in legacy communications, where the legacy communications are based on a first transmission time interval (TTI) of a first duration. Ultra low latency (ULL) communications can be received, where the ULL communications are based on a second TTI that is less than the first duration. A ULL soft buffer size for a ULL soft buffer for decoding HARQ based transmissions in the ULL communications can be determined. Contents of the ULL soft buffer can be managed based at least in part on the ULL soft buffer size.

Abstract: The subject matter described herein includes methods, systems, and computer readable media for efficiently scrambling data in high speed communications networks. One exemplary method includes, in a network equipment test device, providing a scrambler for scrambling data to be transmitted to a device under test. Scrambling the data includes separating a scrambling algorithm into a scramble key portion and a data portion. Scrambling the data further includes pre computing and storing the scramble key portion. Scrambling the data further includes precomputing and storing the data portion. Scrambling the data further includes logically combining the precomputed scramble key portion with the precomputed data portion to produce a data bus width scrambled output data. The method further includes transmitting the scrambled output data over a network to the device under test.

Abstract: Systems, methods, and devices to communicate in a white space are described herein. In some aspects, wireless communication transmitted in the white space authorizes an initial transmission by a device. The wireless communication may include power information for determining a power at which to transmit the initial transmission. The initial transmission may be used to request information identifying one or more channels in the white space available for transmitting data. In some aspects, a device for wireless communication is disclosed. The device may include a data interleaver with at least a first mode and a second mode. The modes may correspond to transmitting using either two or four channels of the white space.

Abstract: Method and system for improving the security of storing digital data in a memory or its delivery as a message over the Internet from a sender to a receiver using one or more hops is disclosed. The message is split at the sender into multiple overlapping or non-overlapping slices according to a slicing scheme, and the slices are encapsulated in packets each destined to a different relay server as an intermediate node according to a delivery scheme. The relay servers relay the received slices to another other relay server or to the receiver. Upon receiving all the packets containing all the slices, the receiver combines the slices reversing the slicing scheme, whereby reconstructing the message sent.

Abstract: A bit interleaving method involves applying a bit permutation process to bits of a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N?/M folding sections (N? being a subset of N selected cyclic blocks and being a multiple of M/F), each of the constellation words being associated with one of the F×N?/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.

Abstract: A laser machining system and a method thereof are disclosed. The disclosed laser machining system comprises a laser generator, an array photo detector, a processer, and a position controller. The laser generator is configured to emit laser via a first light path onto a work piece. The array photo detector is configured to receive the thermal radiation from the work piece via a second light path, different from the first light path, to generate a thermal radiation image. The processor, electrically coupled to the laser generator and the array photo detector, is configured to calculate a temperature centroid of the thermal radiation image and generate a distance control signal according to the temperature centroid. The position controller, electrically coupled to the processor, is controlled by the distance control signal to make a present distance between the laser machining system equal to a working distance.

Abstract: A concatenated encoder is provided that includes an outer encoder, a symbol interleaver and a polar inner encoder. The outer encoder is configured to encode a data stream using an outer code to generate outer codewords. The symbol interleaver is configured to interleave symbols of the outer codewords and generate a binary stream. The polar inner encoder is configured to encode the binary stream using a polar inner code to generate an encoded stream. A concatenated decoder is provided that includes a polar inner decoder, a symbol de-interleaver and an outer decoder. The polar inner decoder is configured to decode an encoded stream using a polar inner code to generate a binary stream. The symbol de-interleaver is configured to de-interleave symbols in the binary stream to generate outer codewords. The outer decoder is configured to decode the outer codewords using an outer code to generate a decoded stream.

Abstract: A method for facilitating a secured data transmission in near field communication is provided. The method includes dynamically interleaving data to be transmitted, using randomization and transmitting the dynamically interleaved data and the interleaved settings/parameters to the destination. Further, a receiver device performs dynamic de-interleaving of received data using the received interleaved settings/parameters. Further, in order to ensure security to the data transmission, the system may use Random Skip Count (RSC) values. If necessary, new dynamic interleaving settings/parameters are calculated based on an RSC value and the new settings/parameters are used to dynamically interleave the data. The process of interleaving can be performed in 2-dimensional or 3-dimensional formats.

Abstract: Systems and methods for decoding bitstreams are described. The bitstreams may be encoded using a punctured convolution code and received from a wireless network. A puncture pattern associated with a modulation and coding scheme used to encode the bitstream is determined, and punctured log-likelihood ratios (LLRs) generated from the bitstream are ignored while decoding the bitstream. The puncture pattern may be characterized by one or more algorithms that identify punctured LLRs in a repetitive sequence of LLRs. A decoder may exclude punctured LLRs from calculations related to bitstream decoding. The decoder may comprise a Viterbi decoder or an algebraic decoder. Other aspects, embodiments, and features are also claimed and described.

Abstract: A system and method for modulation diversity uses interleaving. Code bits are placed into groups and are then shuffled within each group.

Abstract: A method for producing N-bit output words of RLL-encoded data having both a global constraint Go and an interleave constraint Io on bits of a first value includes receiving N-bit input words of RLL-encoded data having both a global constraint Gi and an interleave constraint Ii on bits of like value; and producing the output words from respective input words by sliding-window encoding of each input word to replace predetermined bit-sequences with respective substitute sequences such that Go<Gi; wherein each substitute sequence is unique and violates a run-length limit associated with the interleave constraint Ii such that Io>Ii.

Abstract: The disclosure herein describes systems and methods for representing text. For example, one disclosed embodiment is a method including the steps of receiving a plurality of text strings, each text string comprising at least one character, wherein the at least one character has a representation comprising a first part and a second part; receiving a request to sort the plurality of text strings; and sorting the plurality of text strings based on first parts of the characters of the text strings. In another embodiment, a computer-readable medium comprises program code for causing a processor to execute such a method.

Abstract: Disclosed is a shift register (200, 400) comprising an input (205), an output (230) and a plurality of register cells (210) serially connected between the input and the output, each register cell being connected to a neighboring cell via a node, wherein at least some of said nodes comprise a multiplexer (220) having an output coupled to the downstream register cell and a plurality of inputs, each of said plurality of inputs being coupled to a different upstream register cell such that different length sections of the shift register can be selectively bypassed, the shift register further comprising a set of parallel IO channels (230, 410) facilitating conversion between interleaved and de-interleaved data, each of said channels being coupled to a different one of said nodes, the number of parallel IO channels being smaller than the total number of register cells in the shift register.

Abstract: Embodiments of the present invention provide a rate matching method and apparatus. The method includes: receiving bit data of a first, a second, and a third input subblock, inserting dummy data into bit data in each subblock to respectively form even-numbered rows and odd-numbered rows of a matrix to be buffered for each subblock; inputting bit data of the even-numbered rows in the even-numbered row buffer and bit data of the odd-numbered rows in the odd-numbered row buffer of each subblock to a second buffer, and forming a matrix by using the bit data of the even-numbered rows and the bit data of the odd-numbered rows; controlling the second buffer to send data at the specified address; selecting data sent by the second buffer; and deleting the dummy data from the selected data to obtain valid output data.

Abstract: The present document relates to the transmission of data in a digital cellular telecommunications network. In particular, the present document relates to the secure transmission of data over Global System for Mobile Communications (GSM) networks. A method for encoding a SACCH information block in a wireless network is described. The method comprises randomizing a plurality of randomization unit input bits derived from at least some of a plurality of payload bits of the SACCH information block using a pseudo-random bit block, thereby yielding a plurality of randomized bits; and ciphering a plurality of ciphering unit input bits derived from at least some of the plurality of randomized bits, thereby yielding an encoded data burst of a SACCH frame; wherein ciphering is based on a ciphering algorithm using a ciphering key Kc and a frame number COUNT of the SACCH frame; wherein the pseudo-random bit block is determined based on the ciphering key Kc.

Abstract: An encoding module comprises an inverse interleaving module arranged to: determine an initial location index within an interleaving matrix for a data bit; and perform bit reverse ordering (BRO) on a column index value for the initial location index for the data bit to obtain a BRO column index value for the data bit. The inverse interleaving module is further arranged to calculate a number of valid interleaving matrix addresses preceding a location index for the data bit following bit reverse ordering; and determine a position of the data bit within the interleaved data stream based on the calculated number of valid addresses.

Abstract: A method is provided for encoding data to be sent to at least one receiver, including at least two identical encoding steps and at least one permutation step. Each encoding step associates a block of encoded data with a block of data to be encoded, using at least two basic codes, each code processing a subset of the data block to be encoded. The permutation step is inserted between two encoding steps, i.e. a current encoding step and a previous encoding step, such that the order of the data in a data block to be encoded by the current encoding step is different from the order of the data encoded by the previous encoding step. The permutation step implements, for a data block, a rotation applied to the data of the data block and a reversal of the order of the data of the data block. The operations can be implemented by an interleaving matrix.

Abstract: A technique for rate matching a bit stream (c(0-2)(k)) output from a channel encoder (102) to a data transmission rate on a physical transmission channel is described. A method embodiment of the technique comprises the steps of determining, at a beginning of a transmission time interval for a transmission of one or more code blocks on the transmission channel, bit positions of interleaver padding bits (dummy and/or filler bits) in an output buffer for buffering the output bits before transmission on the physical transmission channel; storing the determined padding bit positions (114); and determining, based on the stored padding bit positions, positions (d(0-2)(k)) of the output bits from the channel encoding stage (102) in the output buffer, wherein the stored padding bit positions are re-used for each of the one or more code blocks.

Abstract: Systems and methodologies are described that facilitate automatically generating interleaved addresses during turbo decoding. An efficient recursive technique can be employed in which layers of nested loops enable the computation of a polynomial and a modular function given interleaved parameters “a” and “b” from a look up table. With the recursive technique, interleaved addresses can be generated, one interleaved address per clock cycle which can maintain turbo decoding performance.

Abstract: Digital communications interleavers re-order the bits of a data coding block in a way that can be described by a table of indices that map the original order to the interleaved order. Conventional interleavers include index table interleavers, which store an index table ahead of operation and algorithmic Interleavers, which generate the indices during operation. Described herein are a new class of interleavers: Subset Transform Interleavers. A subset of generator outputs is selected and processed to create the interleaver indices. The selection is determined apriori and the selection results are stored in a Subset Usage Table. During operation, the generator is operated again and the Subset Usage Table entries determine which generator outputs are used. The generator may be a pseudo-random number generator. Implementations can use an Indexes Remaining Table, which can additionally be manipulated during operation such that it returns to an initialized state after each block interleaving process.

Abstract: Digital communications interleavers re-order the bits of a data coding block in a way that can be described by a table of indices that map the original order to the interleaved order. Conventional interleavers include index table interleavers, which store an index table ahead of operation and algorithmic Interleavers, which generate the indices during operation. Described herein are a new class of interleavers: Subset Transform Interleavers. A subset of generator outputs is selected and processed to create the interleaver indices. The selection is determined apriori and the selection results are stored in a Subset Usage Table. During operation, the generator is operated again and the Subset Usage Table entries determine which generator outputs are used. The generator may be a pseudo-random number generator. Implementations can use an Indexes Remaining Table, which can additionally be manipulated during operation such that it returns to an initialized state after each block interleaving process.

Abstract: A method and an apparatus of symbol interleaving are provided. A sequence S(i) is transformed to generate a symbol interleaving sequence. A numerical value of the sequence S(i) is corresponding to a serial number of a channel element (CE). The symbol interleaving sequence may also be obtained based on a Costas sequence. Therefore, the number of symbol groups in one CE that are mapped to the same physical resource position by different cells is effectively reduced, so that the effect of interference randomization between the cells is improved, the influence of the interference between the cells on the system performance is lowered, and the generation of the symbol interleaving sequence is simplified.

Abstract: A method and a device (4) for block interleaving of size K with N iterations of index j, N being greater than or equal to 1, of input digital data items indexed by a variable k={0, . . . , K?1}. The interleaving method uses a turbo structure that has two inputs and one output. At the end of each iteration j, the interleaving law I(j)(k) at the output of the interleaver (4) is modified in accordance with an input sequence formed by the position indices of the data items before interleaving (typically a ramp) and in accordance with an interleaved sequence (which provides the position of the data items after interleaving) resulting from the previous iteration of the same interleaving algorithm.

Abstract: The invention provides a method and system for reducing redundant data blocks. The method includes reducing redundant data blocks by decoding a first data block from a first plurality of data blocks and a bitstream.

Abstract: A trellis encoding device includes a plurality of trellis encoders to perform trellis-encoding of a transport stream into which a supplementary reference signal (SRS) has been inserted, and performs a memory reset in a region that precedes an SRS; and a parity compensation unit to compensate for parities of the transport stream in accordance with values stored in memories included in the trellis encoders. The plurality of trellis encoders may be implemented in diverse types. The trellis encoding device can perform a memory reset selectively using the stored value of the memory and the inverted value thereof, or selectively using the stored value of the memory and a fixed value. By properly resetting the memory in processing the transport stream into which the SRS has been inserted, DC offset can be reduced.

Abstract: This document describes various techniques for efficiently sequencing structured data in a particular order to provide a sequence of data elements suitable for storage or communication. The sequence may contain values representing a number of default-value structured data elements omitted from the sequence and/or a byte length of the sequence.

Abstract: A plurality of “local” interleavers replaces a single global interleaver for processing encoded data. If the encoded data may be represented as a matrix of data blocks, or “circulants,” each local interleaver can be the size of one or a small number of circulants. Thus, for example, if the matrix has a certain number of rows and columns, the number of local interleavers may be equal to the number of columns. Each local interleaver is small so latency is low.

Abstract: Methods and apparatus are provided for programmable decoding of a plurality of code types. A method is provided for decoding data encoded using one of a plurality of code types, where each of the code types correspond to a communication standard. The code type associated with the data is identified and the data is allocated to a plurality of programmable parallel decoders. The programmable parallel decoders can be reconfigured to decode data encoded using each of the plurality of code types. A method is also provided for interleaving data among M parallel decoders using a communications network. An interleaver table is employed, wherein each entry in the interleaver table identifies one of the M parallel decoders as a target decoder and a target address of a communications network for interleaved data. Data is interleaved by writing the data to the target address of the communications network.

Abstract: A reading unit for reading data from a digital data carrier, the reading unit comprising: a reading head including a sensor for sensing data from the data carrier and generating a sensor signal indicative for the sensed data; head positioning apparatus for positioning the head relative to the data carrier in response to a head positioning control signal; a head positioning controller for receiving the sensed data and being operable in accordance with a stored instruction set to process the sensed data to generate the head positioning control signal; and a data decoder for decoding the sensed data to form a digital output signal.

Abstract: A plurality of “local” interleavers replaces a single global interleaver for processing encoded data. If the encoded data may be represented as a matrix of data blocks, or “circulants,” each local interleaver can be the size of one or a small number of circulants. Thus, for example, if the matrix has a certain number of rows and columns, the number of local interleavers may be equal to the number of columns. Each local interleaver is small so latency is low.

Abstract: A method for decoding includes receiving a message at a decoding device, where the message includes a code corresponding to a sequence of data symbols. Based on the code, a first data symbol of the sequence of data symbols is determined. The first data symbol is determined based at least in part on a first radix used to generate the code. Based on the code, a second data symbol of the sequence of data symbols is also determined. The second data symbol is determined based at least in part on a second radix and at least in part on the first data symbol.

Abstract: A demodulating apparatus includes a deinterleave processing unit applying deinterleave processing to supplied data for each of parameters necessary in executing deinterleave processing in a time direction, an acquiring unit acquiring parameters with which the data should be processed, and a selecting unit selecting, from the deinterleave processing unit, the data subjected to the deinterleave processing with the parameters acquired by the acquiring unit.

Abstract: A first grouping of memory space addresses is generated for systematic bits of a received codeword; a second grouping of memory space addresses is generated for a first set of coding bits of the received codeword, wherein the first set of coding bits comprises an ascending order; and a third grouping of memory space addresses is generated for a second set of coding bits of the received codeword, wherein the second set of coding bits comprises an interleaved order. A sub-codeword of the received codeword is decoded in parallel by accessing the first set of coding bits using the addresses in the second grouping of memory spaces. In turn, another sub-codeword of the received codeword is decoded in parallel by accessing the second set of coding bits using the addresses in the third grouping of memory spaces. Apparatus and a memory storing a computer program are also detailed.

Abstract: Interleaving improves noise rejection in digital communication and storage systems. According a known scheme, the interleaving/deinterleaving is achieved by storing symbols in a temporary memory table of R rows×C columns in a row by row order, and reading them in a column by column order, or vice versa, so obtaining a rearranged order. Methods and devices for interleaving and deinterleaving are proposed which accomplish the same interleaving/deinterleaving operation with a reduced size of the temporary memory table. The rearrangement of the symbols according to the rearranged order is accomplished by using a table with a reduced memory size, in combination with the order with which the symbols are fetched from or stored in a further memory. The invention further relates to ICs and apparatuses for interleaving and/or deinterleaving.

Abstract: Systems and methods are provided to process wireless data packets. A method includes determining a subset of data bits to be processed at a wireless transmitter and employing a clock edge to store the data. The clock edge allows parallel mapping of at least two bits from the subset of data bits into an interleaver memory per a given clock edge. From the memory, other encoding and scrambling processes are applied before transmitting the data packets across a wireless network.

Abstract: A method for encoding and decoding codes of constant weight that is based on conjugate dissections, which progressively modifies element values of an input vector to satisfy the constraint that each encoded symbol is to comprise integer component elements even when the encoded symbol is generated through processing that involved permuting.

Abstract: Methods and apparatus are provided for modulation coding a stream of binary input data. A 4-ary enumerative encoding algorithm is applied to the input bit-stream to produce a succession of 4-ary output symbols. The 4-ary algorithm is operative to simultaneously encode respective generalized Fibonacci codes in the odd and even interleaves of the input bit-stream. The bits of each successive 4-ary output symbol are then interleaved, producing an output bit-stream which has global and interleaved run-length constraints. Inverting the bits of the 4-ary output symbols produces an output bit-stream with (G, I)-constraints as in the PRML (G, I) codes used in reverse-concatenation modulation systems. Corresponding decoding systems are also provided.

Abstract: A first grouping of memory space addresses is generated for systematic bits of a received codeword; a second grouping of memory space addresses is generated for a first set of coding bits of the received codeword, wherein the first set of coding bits comprises an ascending order; and a third grouping of memory space addresses is generated for a second set of coding bits of the received codeword, wherein the second set of coding bits comprises an interleaved order. A sub-codeword of the received codeword is decoded in parallel by accessing the first set of coding bits using the addresses in the second grouping of memory spaces. In turn, another sub-codeword of the received codeword is decoded in parallel by accessing the second set of coding bits using the addresses in the third grouping of memory spaces. Apparatus and a memory storing a computer program are also detailed.

Abstract: A method for generating an interleaved output during a decoding of a data block, the method includes: (i) selecting, in response to a row indicator, a row register and a multiplication factor to provide a selected row register and a selected multiplication factor; wherein the selected multiplication factor is responsive to a size of the data block; (ii) multiplying a value stored in the selected row register by the selected multiplication factor to provide an intermediate result; (iii) performing a modulo P operation on the intermediate result to provide a permutated result; wherein the permutated result and the value stored in the selected row register are adjacent elements of the same permutation; wherein P is responsive to a size of the data block; (iv) writing the permutated result to the selected row register; and (v) outputting a data block element that is selected in response to the permutated result.

Abstract: An apparatus and method of multi-stage network for iterative network are disclosed. The apparatus has M stages, and each stage uses N multiplexers to transmit N codeword partitions simultaneously. Every starting terminal, either the output port of memories, soft-in soft-out decoders, or multiplexers, has two paths to couple with two different multiplexers at next stage. One path connects the source to the first data port of one multiplexer; the other connects the source to the second data port of another multiplexer. The two multiplexers will be controlled with the same 1-bit signal, so each source has only one valid path to next stage. The invention can guarantee that the transmission of N data blocks is free from contention.

Abstract: Interleaver for scrambling an information word, the information word having a multitude of digits, for obtaining a permuted information word. The interleaver includes a first interleaver stage for a row-by-row arranging of the digits of the information word in a plurality of first rows and first columns, and a second interleaver stage for scrambling the digits of one of the first rows by interchanging at least two digits of the one first row in order to obtain a first scrambled row, and for replacing the one of the first rows by the first scrambled row. The first interleaver stage is configured for reading the first row, which is replaced based on the first scrambled row, in a column-by-column manner in order to obtain the permuted information word.

Abstract: The method allows to obtain, starting from an initial S-random interleaver permutation stored in memory devices and having a size N, i.e. formed of N elements, a final S-random permutation having a smaller size K<N, i.e. formed of K elements, by successive pruning operations or steps which, starting from the initial permutation, yield the final permutation, through an iterative process which is performed by means of electronic processing devices, and in which in successive steps selected elements are eliminated from the initial permutation in accordance with predetermined criteria. The final permutation is generated using a reference vector having a dimension or size equal to that of the initial permutation and comprising thus N elements.

Abstract: A decoder comprising a decoding element arranged to operate in a first mode for decoding a turbo encoded data stream and in a second mode for decoding a viterbi encoded data stream, wherein the decoding element is responsive to a first control signal for switching from the first mode to the second mode during decoding of a turbo code block and responsive to a second control signal for switching from the second mode to the first mode to allow continued decoding of the turbo code block.