Abstract: A first and a second data value are co-compressed by generating a sequence of symbols having a most significant symbol that is the most significant symbol of a compressed representation of the first data value and a least significant symbol that is the most significant symbol of a compressed representation of the second data value. The compressed representation of the first data value corresponds to at least a portion of the symbols of the sequence of symbols starting from the most significant symbol and extending towards the least significant symbol in a first reading direction. The compressed representation of the second data value also corresponds to at least a portion of the symbols of the sequence of symbols, however, starting from the least significant symbol and extending in an opposite reading direction towards the most significant symbol.

Abstract: An improved transmission protocol is used to transmit a signal between two components of an electronic device. The improved transmission protocol is configured to reduce the number of simultaneous channel transitions that occur when multiple signal channels are transmitted in parallel. Reducing the number of simultaneous channel transitions is beneficial because a signal that is subject to skew, distortion, or electromagnetic interference during transmission may have a shorter settling time when fewer channels undergo a transition simultaneously. When the protocol is used to transmit a signal from a controller to an optical pickup unit in an optical data storage system, the reduced settling times allow for a higher data transmission rate.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for identifying misrepresented characters in strings of text. A computer system receives text that includes characters identified as being encoded in UTF-8. The characters are represented as code point values, each code point value representing one character in the text. The computer system makes a determination that the text likely includes characters incorrectly converted from Win-1252 to UTF-8 by comparing the code point values that represent the text with test values. Based on the comparison, the computer system identifies sequences of characters in the text that was likely incorrectly converted.

Abstract: Method and system for representing a strong of alpha characters, numeral characters and/or delimiters that allows uniform searching procedures, whether or not numerals and/or delimiters are present in the string. Numerical sub strings, containing only numerals and delimiters, are re characterized in binary format and are separated from, and later recombined with, sub strings containing only alpha characters and delimiters, to provide a modified searchable string in binary format Floating point numbers are easily handled in this approach. Delimiters may be any subset of ASCII characters, as distinguished from numerals and from alpha characters. A numeral character, to be transmitted as a sequence of bits, is optimized by expression in a base (power of 2) requiring the smallest bit count.

Abstract: A decoder comprising a decoding element arranged to operate in a first mode for decoding a turbo encoded data stream and in a second mode for decoding a viterbi encoded data stream, wherein the decoding element is responsive to a first control signal for switching from the first mode to the second mode during decoding of a turbo code block and responsive to a second control signal for switching from the second mode to the first mode to allow continued decoding of the turbo code block.

Abstract: A method, a component, a system, and a computer program for changing an encoding mode of an encoded data stream from a first encoding mode to a second encoding mode are disclosed. The encoded data stream at the first encoding mode is represented by first encoding parameters. For the encoding mode change the steps of selecting (20) a first set of the first encoding parameters to be used unchanged at the second encoding mode, selecting (30) a second set of the first encoding parameters, changing (40) the second set according to an algorithm being adapted to change the second set to match to the second encoding mode when combined with the first set, and combining (50) the first set and the changed second set for representing the encoded data stream by second encoding parameters at the second encoding mode are performed.

Abstract: A method for communication between a sender and a receiver, including receiving data in the form of an M-of-N code, where the M-of-N code includes a first component of length n1 and a second component of length n2; decoding data in which the first component is an m1-of-n1 code and the second component is an m2-of-n2 code; and decoding data in which the first component is an m3-of-n1 code where m1?m3 and the second component is an m4-of-n2 code where m2?m4.

Abstract: A watermark message embedded in a cover work can be made robust to various types of post-embedding operations, while simultaneously minimizing perceptual impact on the cover work. This is accomplished by the informed coding of the watermark message to be embedded. This is also accomplished by the informed embedding of the watermark message code in the cover work. Finally, the watermark message code may be perceptually shaped to minimize impact on the fidelity of the watermarked work. Further, these techniques may be combined for maximum effect.

Abstract: In a watermarking system, an embedder embeds one of several alternative watermark patterns that represent the source message using side information to improve robustness. A detector uses normalized correlation to test all of the patterns, indicating that the source message is present if any one of the patterns is detected. The detection process results in a detection region that is the union of several disjoint cones, or a cone-forest, in media space.

Abstract: In an image coding method of the present invention, after a process such as DCT is performed to digital image data, quantization process is performed, and then, to resultant quantized transform coefficients, variable length coding process is performed with reference to a variable length code table showing how variable length codes are allocated, and in a comparison process between an event derived from the quantized transform coefficients and a reference event included in the variable length code table, transformation process is performed to increase a possibility of performing variable length coding with satisfactory coding efficiency.

Abstract: A receiver unit for use in a CDMA system and including a channel processor, a buffer, and a data processor. The channel processor processes samples for one or more physical channels for each time interval to provide symbols. The buffer is operated as a number of memory banks. Each memory bank is associated with a respective time interval and stores symbols associated with that time interval. The data processor retrieves symbols for a particular “traffic” from one or more memory banks and processes the retrieved symbols. For the W-CDMA system, each traffic includes one or more radio frames for a particular transmission time interval. The receiver unit typically further includes a controller that directs the storage and retrieval of symbols to and from the memory banks and a decoder that decodes symbols processed by the data processor.

Abstract: In an image coding method of the present invention, after a process such as DCT is performed to digital image data, quantization process is performed, and then, to resultant quantized transform coefficients, variable length coding process is performed with reference to a variable length code table showing how variable length codes are allocated, and in a comparison process between an event derived from the quantized transform coefficients and a reference event included in the variable length code table, transformation process is performed to increase a possibility of performing variable length coding with satisfactory coding efficiency.

Abstract: In an image coding method of the present invention, after a process such as DCT is performed to digital image data, quantization process is performed, and then, to resultant quantized transform coefficients, variable length coding process is performed with reference to a variable length code table showing how variable length codes are allocated, and in a comparison process between an event derived from the quantized transform coefficients and a reference event included in the variable length code table, transformation process is performed to increase a possibility of performing variable length coding with satisfactory coding efficiency.

Abstract: In a data transmitter having a data encoder, an encoder mode is detected. Thereafter, an excluded codeword output by the encoder operating in the encoder mode is identified. Next, a selected bit in the excluded codeword caused to have a predetermined value to produce a non-excluded codeword. Finally, the excluded codeword is substituted with the non-excluded codeword, wherein the non-excluded codeword is selected to mitigate effects of a decoding error in a receiver associated with the excluded codeword.

Abstract: In an image coding method of the present invention, after a process such as DCT is performed to digital image data, quantization process is performed, and then, to resultant quantized transform coefficients, variable length coding process is performed with reference to a variable length code table showing how variable length codes are allocated, and in a comparison process between an event derived from the quantized transform coefficients and a reference event included in the variable length code table, transformation process is performed to increase a possibility of performing variable length coding with satisfactory coding efficiency.

Abstract: An apparatus and method provide an apparatus and method for reducing noise production and power consumption in a logic device that uses monotonic logic encoded signals. In particular, the apparatus is accomplished by a recode circuitry that receives and recodes a monotonic logic encoded signal received from a first logic circuit in the logic device, into a reduced switching signal. The recode circuitry sends the reduced switching signal to a second logic circuit. A decode circuitry receives and decodes the reduced switching signal back into a monotonic logic encoded signal. The decode circuitry then sends the monotonic logic encoded signal to a second logic circuit in the logic device. The method is accomplished by receiving a monotonic logic encoded signal from a first logic circuit. The monotonic logic encoded signal is converted into a reduced switching signal and transmitted. The reduced switching signal is received and converted back into the monotonic logic encoded signal.

Abstract: In an image coding method of the present invention, after a process such as DCT is performed to digital image data, quantization process is performed, and then, to resultant quantized transform coefficients, variable length coding process is performed with reference to a variable length code table showing how variable length codes are allocated, and in a comparison process between an event derived from the quantized transform coefficients and a reference event included in the variable length code table, transformation process is performed to increase a possibility of performing variable length coding with satisfactory coding efficiency.

Abstract: In an image coding method of the present invention, after a process such as DCT is performed to digital image data, quantization process is performed, and then, to resultant quantized transform coefficients, variable length coding process is performed with reference to a variable length code table showing how variable length codes are allocated, and in a comparison process between an event derived from the quantized transform coefficients and a reference event included in the variable length code table, transformation process is performed to increase a possibility of performing variable length coding with satisfactory coding efficiency.

Abstract: The present invention offers a method and a circuit for generating codes enabling transmission of long-codes to start on a reverse channel in a shorter waiting time. The method involves corresponding a shift quantity between the beginning of a sequence M or long-codes cycle, and each timing to a combination of a plurality of masking data; determining a combination of masking data for timing to start generation of long-codes in response to a transmission request at a point of time as soon as possible; and shifting of an initial value of a vector according to the masking data.

Abstract: In an image coding method of the present invention, after a process such as DCT is performed to digital image data, quantization process is performed, and then, to resultant quantized transform coefficients, variable length coding process is performed with reference to a variable length code table showing how variable length codes are allocated, and in a comparison process between an event derived from the quantized transform coefficients and a reference event included in the variable length code table, transformation process is performed to increase a possibility of performing variable length coding with satisfactory coding efficiency.

Abstract: An apparatus and method provide an apparatus and method for reducing noise production and power consumption in a logic device that uses monotonic logic encoded signals. In particular, the apparatus is accomplished by a recode circuitry that receives and recodes a monotonic logic encoded signal received from a first logic circuit in the logic device, into a reduced switching signal. The recode circuitry sends the reduced switching signal to a second logic circuit. A decode circuitry receives and decodes the reduced switching signal back into a monotonic logic encoded signal. The decode circuitry then sends the monotonic logic encoded signal to a second logic circuit in the logic device. The method is accomplished by receiving a monotonic logic encoded signal from a first logic circuit. The monotonic logic encoded signal is converted into a reduced switching signal and transmitted. The reduced switching signal is received and converted back into the monotonic logic encoded signal.

Abstract: A coding and/or decoding system includes: a code-word table for storing therein a plurality of code words, which are capable of being decoded both in forward and backward directions and which are formed so that delimiters of the code words are capable of being identified by a predetermined weight of the code words, so that the code words correspond to different source symbols; an encoder for selecting code words corresponding to inputted source symbols from the code-word table; and a synchronization interval setting part for preparing coded data every predetermined interval using the code words selected by the encoder and for inserting stuffing codes capable of being decoded in the backward direction. Thus, it is possible to decrease useless bit patterns to enhance the coding efficiency by smaller amounts of calculation and storage, and to decode variable length codes both in the forward and backward directions even if the synchronization interval is set every interval using the stuffing bits.

Abstract: An apparatus and method provide an apparatus and method for reducing noise production and power consumption in a logic device that uses traditional domino encoded signals. In particular, the apparatus is accomplished by a recode circuitry that receives and recodes a traditional domino encoded signal received from a first logic circuit in the logic device, into a reduced switching signal. The recode circuitry sends the reduced switching signal to a second logic circuit. A decode circuitry receives and decodes the reduced switching signal back into a traditional domino encoded signal. The decode circuitry then sends the traditional domino encoded signal to a second logic circuit in the logic device. The method is accomplished by receiving a traditional domino encoded signal from a first logic circuit. The traditional domino encoded signal is converted into a reduced switching signal and transmitted. The reduced switching signal is received and converted back into the traditional domino encoded signal.

Abstract: In an image coding method of the present invention, after a process such as DCT is performed to digital image data, quantization process is performed, and then, to resultant quantized transform coefficients, variable length coding process is performed with reference to a variable length code table showing how variable length codes are allocated, and in a comparison process between an event derived from the quantized transform coefficients and a reference event included in the variable length code table, transformation process is performed to increase a possibility of performing variable length coding with satisfactory coding efficiency.

Abstract: A bitstream decoding apparatus for decoding a video signal compressed according to the Moving Picture Experts Group (MPEG) standard within a single clock cycle to convert the compressed video signal into the form of symbols such as video parameters and discrete cosine transform (DCT) coefficients. The bitstream decoding apparatus for performing the decoding operation within a single clock cycle includes a shifter, a variable length decoder, a fixed length decoder, a zero-run & AC decoder, a first multiplexer, a second multiplexer, and a first comparator. In the bitstream decoding apparatus, the compressed video data can be decoded within a single clock cycle to perform transmission of a high-resolution picture signal such as that used in a digital television in an efficient way.

Abstract: A moving picture coding and/or decoding system includes a encoder for coding input image data, a divider for dividing a code string supplied from the encoder, into a plurality of code string, a reorderer for arranging at least one of the plurality of code string in the forward direction from the head to the end, and at least one of the other code string in the backward direction from the head to the end. A variable-length coding system includes a code-word table for storing a plurality of code words so that the code words correspond to source symbols, and an encoder for selecting a code word corresponding to the source symbol inputted from the code-word table and for outputting the selected code word as coded data. The plurality of code words can be decoded in either of the forward and backward directions.

Abstract: The invention provides a method for solving, for an interim period of up to seven years, what is commonly known as the year 2000 computer date problem. The method is based on utilizing the presently unused capacity of a two-digit computer month field, which is a constituent part of a six-digit computer date field, in the following manner. Each month in the years 2000 through 2006 is sequentially assigned one unique two-digit number greater than twelve while the year number is kept unchanged, as the dates are encoded and stored into the computer date fields on the computer media and in the computer memory during the years 2000 up through 2006. That ensures that during said period of up to seven years, the date as number keeps increasing with the passage of time and that each date is as number greater than any date in the years 1999 and the previous years, which are the essential requirements for computer's capability to do the manipulation (sort, retrieval, insertion, deletion, archival, etc.

Abstract: Multiple resonant tunneling devices offer significant advantages for realizing ultra-dense, ultra-high performance multivalued logic arithmetic integrated circuits. A multivalued logic adder is disclosed, wherein two numbers represented by positive digit base-M range-N words are added by two-input summation circuits 40 which sum corresponding digits, then the digit sums are decomposed into a binary representation by range-7 multivalued to binary converter circuits 42, then three-input summation circuits 44 sum appropriate bits of the binary representations to calculate the digits of a positive digit base-2 range-4 word whose value is the sum of the two numbers. Preferably, the decomposition to binary representation is performed by multi-valued folding circuits 56 which are connected by voltage divider circuitry. Preferably, the multi-valued folding circuits contain multiple-peak resonant tunneling transistors 54. Ripple carries are eliminated and the speed of the adder is independent of input word width.

Abstract: A variable length decoder which is particularly suitable for decoding digital video data for HDTV. The variable length decoder operates to decode in parallel qualifying code words, such as payload data in an MPEG data stream, during a single clock cycle, and operates to decode singular non-qualifying code words, such as setup data in the MPEG data stream, during a single clock cycle. Since the payload data constitutes approximately 95% of the MPEG data stream, the throughput of the VLD of the present invention is significantly higher than that of the presently available VLDs, at a clock rate that is significantly lower than that of the presently available VLDs.

Abstract: A database record compression system compresses data with frequency priority. The system has a formal dictionary for storing compressed strings and entry numbers corresponding to the compressed strings. A temporary dictionary compresses and stores strings of the plurality of strings input from an input file which are not stored in the formal dictionary. The system initializes all entries of the temporary dictionary when a number of registrations in the temporary dictionary reaches a predetermined number of initializations. In the system, an occurred string is registered in the formal dictionary when a frequency of occurrence of the string at the temporary dictionary reaches a predetermined number of times.

Abstract: A decoding device is provided including a code FIFO memory unit for sequentially storing a bit stream, a barrel shifter for shifting and then outputting codes properly, an accumulator for computing the shift amount of the barrel shifter and issuing a request to read data to the code FIFO memory unit, a DCT coefficient decoder for decoding DCT coefficients, a variable-length code decoder for decoding variable-length codes other than DCT coefficients, a fixed-length code decoder for decoding fixed-length codes, a register unit for storing decoded data, a decoding controller for controlling the decoders in accordance with the decoded data stored in the register unit and decoded data output by the decoders and a memory controller for controlling operations to store DCT coefficients in a memory unit A.

Abstract: A method and related input/output devices for using biased 2 digit "hybrid radix" numeric fields for inputting, generating, storing, processing, and outputting year numbers ranging from 1900 to 2059 in a data processing system. In a hybrid radix 2 digit year number, the higher digit is treated as hexadecimal, but displayed in a decimal-like style with font patterns such as 0-9 and '0-'5, while the lower digit is treated as ordinary decimal, so that the year 1900 is represented and processed as 00 while the year 2000 as '00. For applications written with high level languages such as COBOL and SQL, the method can be embodied solely in the system side (compiler, other system software and/or hardware), and so that no change other than a re-compilation with a new compiler is needed for existing application software. Compatibility with existing data files and databases is automatically maintained.

Abstract: A variable length code system which is instantaneously decodable in both forward direction and backward direction is generated either in asymmetrical form or symmetrical form. The code thus generated has high transmission efficiency, and capable of backward reconstruction of video signals even when some bits are lost during transmission. The symbols to be encoded are prepared (1) with occurrence probability, and they are provisionally encoded to a non-reversible variable length code (2). Then, the provisional code is transformed to an asymmetrical reversible code (4) through equivalent transform process (9), reverse symbol tree process (10), and bit supplement process (12) when suffix condition is not satisfied. The provisional code is also transformed to a symmetrical reversible code (3) by assigning a symmetrical code word to each symbol on a symbol tree (FIG. 5). At least one of symmetrical code or a asymmetrical code is selected (5), and is provided as a final resultant code.

Abstract: A code conversion system including a table (EIT) for converting an ISO code and an EIA code into an internal code. Characters and numerals which make common use of the ISO code and EIA code are converted into the same internal code, and characters and numerals which do not make common use of the ISO code and EIA code are converted into respective separate internal codes and stored. The code conversion system also includes a first internal code into the EIA code and a second internal code conversion table (ICT) for converting the internal code into the ISO code. At the time of output, one of the ISO code and EIA code is designated as an output code system, the internal code is output upon being the internal code conversion table corresponding to the designated output code system, and undefined codes are not output in the designated output code system.