Abstract: A reconfigurable compute fabric of a system can include multiple nodes, and each node can include multiple, communicatively coupled tiles with respective processing and storage elements. In an example, a tile-based processor can be configured to perform operations comprising receiving a first stencil that defines input data for a first operation. The stencil can have a height corresponding to N rows in a main memory and a stencil width corresponding to M columns in the main memory. The processor can perform operations comprising establishing N buffers in a tile memory, each buffer having M buffer elements, and populating the M buffer elements of the N buffers using respective information, defined by the first stencil, from the main memory. Tile-based stencil operations can use information from the N buffers and provide compute results in an output array.

Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU or CPU. The apparatus may configure a BVH structure including a plurality of nodes, the BVH structure being associated with geometry data for a plurality of primitives in a scene. The apparatus may also detect a set of hit child nodes for a current node of the plurality of nodes. Further, the apparatus may sort the set of hit child nodes based on the parametric distance value of each of the set of hit child nodes. The apparatus may also compress the node ID and the parametric distance value for each of an updated set of hit child nodes based on the sorted set of hit child nodes. The apparatus may also store the compressed node ID and the compressed parametric distance value for each of the updated set of hit child nodes.

Abstract: In one embodiment, a computing system may determine a view position, a view direction, and a time with respect to a scene. The system may access a spatiotemporal representation of the scene generated based on (1) a monocular video including images each capturing at least a portion of the scene at a corresponding time and (2) depth values of the portion of the scene captured by each image. The system may generate an image based on the view position, the view direction, the time, and the spatiotemporal representation. A pixel value of the image corresponding to the view position may be determined based on volume densities and color values at sampling locations along the view direction and at the time in the spatiotemporal representation. The system may output the image to the display, representing the scene at the time as viewed from the view position and in the view direction.

Abstract: A lossless pixel compressor may include technology to detect a format of a pixel memory region, and compress the pixel memory region together with embedded control information which indicates the detected format of the pixel memory region. Other embodiments are disclosed and claimed.

Abstract: A learning device is configured to perform learning of a decision tree, and includes: a plurality of learning units each corresponding to a data memory of a plurality of data memories, and being configured to perform learning at a first node using learning data acquired by using first addresses related to a storage destination of the learning data corresponding to the first node of the decision tree in the data memory, and output a second address related to a storage destination of each piece of the learning data branched from the first node; and a plurality of managers each corresponding to a learning unit of the plurality of learning units, and being configured to calculate third addresses related to storage destinations of learning data corresponding to second nodes being next nodes of the first node using the first addresses and the second address output from the learning unit.

Abstract: The present disclosure relates to methods and apparatus for display processing. For example, disclosed techniques facilitate speculative page fault handling in a GPU. Aspects of the present disclosure can perform a graphics operation associated with using a set of constants within a flow control. Aspects of the present disclosure can also query a first memory to determine whether memory addresses associated with the set of constants are allocated at a constant buffer of the first memory. Further, aspects of the present disclosure can set a page fault indicator to a true value when the query indicates that at least one memory address associated with the set of constants is unallocated at the constant buffer, and set the page fault indicator to a false value otherwise.

Abstract: In a data processing system comprising a cache system configured to transfer data stored in a memory system to a processor and vice-versa, a processing unit operable to read data from a cache of the cache system can send a read request for data to the cache. The cache system, in response to the read request, determines whether the requested data is present in the cache. When the requested data is present in the cache, the cache system returns the data from the cache to the processing unit and invalidates the entry for the data in the cache. When the requested data is not present in the cache, the cache system returns an indication of that to the processing unit, without the cache system sending a request for the data towards the memory system.

Abstract: Systems, methods, and devices implement line-based rendering of graphics. Methods include receiving a command associated with graphical data, the command identifying a plurality of pixel mapping operations to be implemented on a plurality of data objects included in the graphical data. Methods also include determining a plurality of rendering parameters, the plurality of rendering parameters identifying a partitioning of the graphical data into a plurality of portions, and further identifying a pixel mapping operation for each of the plurality of portions. Methods further include generating a plurality of sub-commands based, at least in part, on the plurality of rendering parameters and the command, the plurality of sub-commands identifying a processing operation for each data object included in each of the plurality of portions of the graphical data. Methods also include implementing a processing operation for at least one portion based on at least some of the plurality of sub-commands.

Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may configure a BVH structure including a plurality of levels and a plurality of nodes, the BVH structure being associated with geometry data for a plurality of primitives in a scene. The apparatus may also identify an amount of storage in a GMEM that is available for storing at least some of the plurality of nodes in the BVH structure. Further, the apparatus may allocate the BVH structure into a first BVH section including a plurality of first nodes and a second BVH section including a plurality of second nodes. The apparatus may also store first data associated with the plurality of first nodes in the GMEM and second data associated with the plurality of first nodes and the plurality of second nodes in a system memory.

Abstract: The present disclosure is directed to methods and apparatus for evaluating resources that would be used by machine learning model(s) for purposes of implementing the machine learning model(s) on resource-constrained devices. For example, in one aspect, a plurality of layers in a machine learning model may be identified. A plurality of respective output sizes corresponding to the plurality of layers may be calculated. Based on the plurality of output sizes, a maximum amount of volatile memory used for application of the machine learning model may be estimated and compared to a volatile memory constraint of a resource-constrained computing device. Output indicative of a result of the comparing may be provided at one or more output components.

Abstract: Methods are provided for creating objects in a way that permits an API client to explicitly participate in memory management for an object created using the API. Methods for managing data object memory include requesting memory requirements for an object using an API and expressly allocating a memory location for the object based on the memory requirements. Methods are also provided for cloning objects such that a state of the object remains unchanged from the original object to the cloned object or can be explicitly specified.

Abstract: An application sends primitives to a graphics processing system so that an image of a 3D scene can be rendered. The primitives are placed into primitive blocks for storage and retrieval from a parameter memory. Rather than simply placing the first primitives into a primitive block until the primitive block is full and then placing further primitives into the next primitive block, multiple primitive blocks can be “open” such that a primitive block allocation module can allocate primitives to one of the open primitive blocks to thereby sort the primitives into primitive blocks according to their spatial positions. By grouping primitives together into primitive blocks in accordance with their spatial positions, the performance of a rasterization module can be improved. For example, in a tile-based rendering system this may mean that fewer primitive blocks need to be fetched by a hidden surface removal module in order to process a tile.

Abstract: A processing unit is configured to access a first memory that supports atomic operations and a second memory via an interface. The second memory or the interface does not support atomicity of the atomic operations. A trap handler is configured to trap atomic operations and enforce atomicity of the trapped atomic operations. The processing unit selectively provides atomic operations to the trap handler in response to detecting that memory access requests in the atomic operations are directed to the second memory via the interface. In some cases, the processing unit detects a frequency of traps that result from atomic operations that include memory access requests to a page stored in the second memory. The processing unit transfers the page from the second memory to the first memory in response to the trap frequency exceeding a threshold.

Abstract: A memory device includes a memory bank including a plurality of banks, each including a memory cell array; a calculation logic including a plurality of processor-in-memory (PIM) circuits arranged in correspondence to the banks, each of the plurality of PIM circuits performing calculation processing using at least one selected from data provided from a host and information read from a corresponding bank among the banks; and a control logic configured to control a memory operation on the memory bank in response to a command and/or an address, each received from the host, or to control the calculation logic to perform the calculation processing, wherein reading operations are respectively performed in parallel on the banks for the calculation processing, offsets having different values are respectively configured for the banks, and information is read from different positions in respective memory cell arrays of the banks and provided to the PIM circuits.

Abstract: Methods, systems, apparatuses, and computer program products are described herein that enable execution of a large AI model on a memory-constrained target device that is communicatively connected to a parameter server, which stores a master copy of the AI model. The AI model may be dissected into smaller portions (e.g., layers or sub-layers), and each portion may be executed as efficiently as possible on the target device. After execution of one portion of the AI model is finished, another portion of the AI model may be downloaded and executed at the target device. This paradigm of executing one portion of the AI model at a time allows for dynamic execution of the large AI model.

Abstract: A server accesses a previous frame of an image in a video and obtains hash values for each pixel in the previous frame and creates a hash map that stores each of the hash values. The server receives a current frame of the image and separates the current frame into a plurality of current blocks of pixels. The server calculates, using a hash function, a hash value for each of the current blocks of pixels. The server compares the hash values in the hash map with the hash values associated with the current frame and identifies a hash value in the hash map that matches a hash value in the current frame. The server compresses the current frame for transmission to a client using the identified matching hash values and pre-calculates a new hash map based on the current frame for use in compressing a next frame of the video.

Abstract: In a computer-implemented method and system of augmenting a video stream of an environment, a processing device receives a first video stream including a plurality of image frames provided from at least one camera, processes the plurality of image frames of the first video stream to define a spatial scope of image data within a respective one of the image frames, modifies the plurality of image frames with frame-based modification information configured to obfuscate or delete or restrict at least one portion of a respective one of the image frames which is outside of the spatial scope of image data within the respective one of the image frames, and outputs a second video stream based on the modified plurality of image frames with the frame-based modification information for transmission to a receiving device, such as a display device.

Abstract: Some embodiments provide a novel method for configuring managed forwarding elements (MFEs) to handle data messages for multiple logical networks that are implemented in a data center at the MFEs and to provide gateway service processing (e.g., firewall, DNS, etc.). A controller, in some embodiments, identifies logical networks implemented in the datacenter and MFEs available to provide gateway service processing and assigns gateway service processing for each logical network to a particular MFE. The MFEs, in some embodiments, receive data messages from endpoints in the logical networks that are destined for an external network. In some embodiments, the MFEs identify that the data messages require gateway service processing before being sent to the external network. The MFEs, in some embodiments, identify a particular MFE that is assigned to provide the gateway service processing for logical networks associated with the data messages.

Abstract: Methods, systems, and devices for graphic processing are described. The methods, systems, and devices may include or be associated with identifying a graphics instruction, determining that the graphics instruction is alias enabled for the device, partitioning an alias lookup table into one or more slots, allocating a slot of the alias lookup table based on the partitioning and determining that the graphics instruction is alias enabled, generating an alias instruction based on allocating the slot of the alias lookup table and determining that the graphics instruction is alias enabled, and processing the alias instruction.

Abstract: Methods and devices for managing first-in first-out (FIFO) queues in graphics processing are described. A dispatcher thread can receive a value of a write done pointer indicating a next memory location following one or more memory locations to which data has been written by a write thread of a graphics processing unit (GPU). The dispatcher thread can accordingly launch, based at least in part on the value of the write done pointer, multiple read threads on the GPU to read, in parallel and based on the write done pointer, the data from the FIFO queue.

Abstract: A hybrid approach to rendering transparent or translucent objects combines object-space ray tracing with texture-space parametrization and integration. Transparent or translucent objects are first parameterized using two textures: (1) a texture that stores the surface normal at each location on the transparent or translucent object, and (2) a texture that stores the world space coordinates at each location on the transparent or translucent object. Ray tracing can then be used to streamline and unify the computation of light transport inside thick mediums, such as transparent or translucent objects, with the rest of the scene. For each valid (e.g., visible) location on the surface of a transparent or translucent object, one or more rays are traced through such objects and the resulting lighting is computed in an order-independent fashion. The results are stored in a texture, which is then applied during the final lighting stage.

Abstract: An application sends primitives to a graphics processing system so that an image of a 3D scene can be rendered. The primitives are placed into primitive blocks for storage and retrieval from a parameter memory. Rather than simply placing the first primitives into a primitive block until the primitive block is full and then placing further primitives into the next primitive block, multiple primitive blocks can be “open” such that a primitive block allocation module can allocate primitives to one of the open primitive blocks to thereby sort the primitives into primitive blocks according to their spatial positions. By grouping primitives together into primitive blocks in accordance with their spatial positions, the performance of a rasterization module can be improved. For example, in a tile-based rendering system this may mean that fewer primitive blocks need to be fetched by a hidden surface removal module in order to process a tile.

Abstract: An embodiment of the present invention is directed to low-maintenance conversion of an advance function presentation (AFP) format to a portable document format. According to an embodiment of the present invention, hidden text may be inserted as locators in the AFP files. For example, the hidden text may be inserted in a small font size (e.g., approximately 1 point) in a color that matches the background, e.g., text in white. A benefit of this hidden text is that it does not need to change with the maintenance of the statement template. Accordingly, the transformation software template may be built, or trained, to look for these hidden text locators to identify the beginning and end of sections. This leads to a robust transformation software template that does not need to be maintained or changed with text changes in the statements.

Abstract: An apparatus and method are described for allocating local memories to virtual machines. For example, one embodiment of an apparatus comprises: a command streamer to queue commands from a plurality of virtual machines (VMs) or applications, the commands to be distributed from the command streamer and executed by graphics processing resources of a graphics processing unit (GPU); a tile cache to store graphics data associated with the plurality of VMs or applications as the commands are executed by the graphics processing resources; and tile cache allocation hardware logic to allocate a first portion of the tile cache to a first VM or application and a second portion of the tile cache to a second VM or application; the tile cache allocation hardware logic to further allocate a first region in system memory to store spill-over data when the first portion of the tile cache and/or the second portion of the file cache becomes full.

Abstract: A device may include a plurality of data processing engines. Each of the data processing engines may include a core and a memory module. The plurality of data processing engines may be organized in a plurality of rows. Each core may be configured to communicate with other neighboring data processing engines of the plurality of data processing engines by shared access to the memory modules of the neighboring data processing engines.

Abstract: Systems and methods are presented by which a contractor can initiate a proposed variation to a project contract and request payments against the proposed variation even before the variation is approved by the other party to the project contract. A data structure representative of proposed variation is generated and maintained as the proposed variation is reviewed, approved, and elevated to become part of the actual budget for the project. Because the same data structure is maintained throughout the process and after the proposed variation is approved, payment requests, payments, and any other actions taken against the data structure before the proposed variation is approved are automatically linked to the actual budget after approval and, thereby, are recognized and processed by external accounting systems as though the variations were created by the other party to the contract.

Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S?1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.

Abstract: A method for page based data persistence can include storing data associated with a state machine at a computing node. The data can be stored by at least allocating a first data page for storing the data. In response to the allocation of the first data page, a first page reference to the first data page can be added to a first page list in an in-memory buffer at the computing node. When the in-memory buffer reaches maximum capacity, a second data page can be allocated for storing the first page list. A second page reference to the second data page can be added to a second page list in the in-memory buffer. Related systems and articles of manufacture, including computer program products, are also provided.

Abstract: A system and method is provided for a predictive connectivity layer. In the disclosed embodiments, resources, such as bandwidth, processing, and memory, at a network node are dynamically allocated based on one or more predicted user behaviors. A predicted user behavior may be determined based on one or more previous actions of a user or a group of users at the network node. For example, if a user accesses the network node to download a particular web site at the same time every morning, the predictive technique may determine that the user will attempt to download the same web site the next morning, and therefore cache a copy of the web site before the user's next attempt to access the network through the network node. Similarly, the network node may predict an amount of bandwidth or other resources to allocate based on previous behavior of one or more users.

Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.

Abstract: A computing device may allocate a plurality of blocks in the memory, wherein each of the plurality of blocks is of a uniform fixed size in the memory. The computing device may further store a plurality of bandwidth-compressed graphics data into the respective plurality of blocks in the memory, wherein one or more of the plurality of bandwidth-compressed graphics data each has a size that is smaller than the fixed size. The computing device may further store data associated with the plurality of bandwidth-compressed graphics data into unused space of one or more of the plurality of blocks that contains the respective one or more of the plurality of bandwidth-compressed graphics data.

Abstract: A data storage method, a memory storage device and a memory control circuit unit are provided. The method includes: determining a first space in a first physical unit of a rewritable non-volatile memory module; and storing at least part of data stored in at least one physical unit of the rewritable non-volatile memory module to a second space in the first physical unit, and the second space is not belonging to the first space, and the first space is for ensuring that valid data stored in at least one second physical unit among the at least one physical unit can be stored to the first physical unit. Therefore, it is ensured that at least one spare physical unit of the memory storage device can be released by a data merging operation of multiple source nodes.

Abstract: An imaging camera and a depth camera are configured to perform a 3D scan of an interior space. A processor is configured to generate voxels in a three-dimensional (3D) grid based on the 3D scan. The voxels represent portions of the volume of the interior space. The processor is also configured to project the voxels onto tiles in a two-dimensional (2D) floor plan of the interior space. The processor is further configured to generate, based on the tiles, a 2D distance grid that represents features in the interior space. In some cases, the 2D distance grid is generated in real-time concurrently with performing the 3D scan of the interior space. The processor is further configured to generate, based on a 2D distance grid, a set of polygons representing elements of the floor plan in real-time. The processor is further configured to generate a simplified set of primitives representing the floor plan.

Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S?1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.

Abstract: Based on natural language processing of a passage of a first electronic document, a determination is made that the passage indicates an action to be undertaken. In response to this determination and based on an analysis of a second electronic document, the second electronic document is identified as incorporating content preconfigured to allow completion of the action. In response to this identification, the passage is linked to the second electronic document.

Abstract: A logic circuit in a processor including a plurality of input registers, each for storing a vector containing data elements, a coefficient register for storing a vector containing N coefficients, an output register for storing a result vector, and an arithmetic unit configured to: obtain a pattern for selecting N data elements from the plurality of input registers, select a plurality of groups of N data elements from the plurality of input registers in parallel, wherein each group is selected in accordance with the pattern, and wherein each group is shifted with respect to a previous selected group, perform an arithmetic operation between each of the selected groups and the coefficients in parallel, and store results of the arithmetic operations in the output register.

Abstract: An image processing apparatus comprises: a first processing circuit which carries out image processing on a first image signal obtained from image signals forming a single image; a second processing circuit which carries out the image processing on a second image signal obtained from the image signals forming the image; and a control circuit which controls communication of image signals between the first processing circuit and the second processing circuit, wherein the first image signal and the second image signal do not have overlap region; and wherein the control circuit controls the communication for transferring an image signal of a region of the image additionally required when the first processing circuit carries out the image processing on the first image signal from the second processing circuit to the first processing circuit.

Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S?1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.

Abstract: An example device in accordance with an aspect of the present disclosure includes a plurality of memory segments corresponding to at least one memory channel of a computing system that is to receive a memory module. A performance attribute of an Advanced Configuration and Power Interface (ACPI) table is set to indicate performance of at least one of the plurality of memory segments, and is usable for memory allocation by an operating system memory manager.

Abstract: An image processing system includes an image processing module, a frame buffer encoding module and a frame buffer. Each image block includes multiple first-type coding blocks and at least one second-type coding block. The image processing module generates a first image processed result according to multiple first-type coding blocks of a target image block. The frame buffer encoding module generates a first frame buffer encoded result according to the first image processed result. The frame buffer, for the target image block, provides a buffer region including at least one first random access point and a second buffer region including at least one second random access point. The first frame buffer encoded result is stored to the first buffer region. At least one second-type coding block of the target image block is stored to the second buffer region.

Abstract: The image recording apparatus according to the present invention is provided with a conversion device that converts an optical image of a subject to an electrical signal, a recording circuit that records the electrical signal achieved through the conversion device in a storage device as image data and a display control circuit that detects an available capacity at the storage device and the length of time that power supply by a source is possible and displays them on a display as available capacity information and remaining power supply time information. The available capacity information indicates the length of available recording time remaining at the available capacity that has been detected.

Abstract: A data processing system 30 includes a CPU 33, a GPU 34, a video processing engine (video engine) 35, a display controller 36 (or an image processing engine) and a memory controller 313 all having access to off-chip memory 314. A frame to be displayed is generated by, for example, being appropriately rendered by the GPU 34 or video engine 35. The display controller 36 (or the image processing engine) then performs display modifications, such as luminance compensation, on the frame to provide an output frame for display. The display controller 36 (or the image processing engine) also provides display modification information (such as determined luminance compensation parameters) to the GPU 33 and video engine 34. The display modification information is then used to modify the data that is generated for a frame to be displayed.

Abstract: One embodiment of the present invention sets forth a method for transmitting data rendered on a primary computer to a secondary computer. The method includes transmitting to GPU graphics processing commands received from a graphics application, where the graphics processing commands are configured to cause the GPU to render a first set of graphics data, determining that graphics data should be collected for transmission to the secondary computer, conveying to the GPU that the first set of graphics data should be stored in a first buffer within a frame buffer memory, transmitting to the GPU graphics processing commands received from a process application executing on the primary computer, where the graphics processing commands are configured to cause the GPU to perform operations on the first set of graphics data to generate a second set of graphics data, and transmitting the second set of graphics data to the secondary computer.

Abstract: A method and system for creating three dimensional (3D) models from two dimensional (2D) data for building information modeling (BIM). The method and system allow new, 2D, 3D and higher dimensional models to be created for existing 3D modeling programs (e.g., AUTODESK REVIT, AUTOCAD, VECTORWORKS, MICROSTATION, ARCHICAD, etc.). The new models are used to enhance and extend existing 3D modeling programs. The new models can also be used to directly create physical objects (e.g., windows, doors, etc.) represented by the new models with robots, 3D printers and manufacturing machines.

Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.

Abstract: A method and associated apparatus for processing video data are provided. The video data includes a first frame formed by a plurality of macroblocks. The method includes providing a memory, deblocking a first macroblock in the first frame, and writing the deblocked macroblock into the memory. The step of writing the deblocked macroblock lets a plurality of pixel data of the deblocked macroblock to be stored to a first storage space at consecutive addresses in the memory.

Abstract: A flag memory is provided which stores a flag indicating whether or not a corresponding pixel is in the initial state. When writing has been performed on an image memory by a drawing unit, a value of the flag of a corresponding pixel is changed from a first value indicating that the pixel is in the initial state to a second value indicating that the pixel is not in the initial state. When a display unit reads a pixel value from the image memory, a flag corresponding to the pixel is read from the flag memory, and if the flag still has the first value, an initial pixel value is supplied to the display unit, and otherwise, a pixel value read from the image memory is supplied to the display unit.

Abstract: An order of calling sub-functions called from a main function for drawing a vector image is obtained, a group of all of sub-functions having a common combination of call sources and being called in succession, is extracted as a group, and a cache function for caching a vector part image drawn with the sub-functions included in the group, as a raster image, is added to the main function to newly generate an improved main function.

Abstract: Compression transforming video into a compressed representation (which typically can be delivered at a capped pixel rate compatible with conventional video systems), including by generating spatially blended pixels and temporally blended pixels (e.g., temporally and spatially blended pixels) of the video, and determining a subset of the blended pixels for inclusion in the compressed representation including by assessing quality of reconstructed video determined from candidate sets of the blended pixels. Trade-offs may be made between temporal resolution and spatial resolution of regions of reconstructed video determined by the compressed representation to optimize perceived video quality while reducing the data rate. The compressed data may be packed into frames. A reconstruction method generates video from a compressed representation using metadata indicative of at least one reconstruction parameter for spatial regions of the reconstructed video.

Abstract: A memory system is provided, which includes a real memory space and a virtual memory space. The memory system includes a memory device having a first memory space which is accessed using a first memory address and a second memory space which is accessed using a second memory address, and a memory controller configured to control access to the memory device; wherein the memory controller is configured to translate the first memory address into the second memory address mapped thereto in response to a request for access to the first memory space, access the second memory space using the translated second memory address, and access the second memory space using the non-translated second memory address, in response to a request for access to the second memory space.