Abstract: In one embodiment, a computing system accesses contextual data associated with a vehicle operated by a human driver. The contextual data is captured using one or more sensors associated with the vehicle. The system determines one or more predicted vehicle operations by processing the contextual data based at least on information associated with pre-recorded contextual data associated with a number of vehicles. The system detects one or more vehicle operations made by the human driver. The system determines that an event of interest is associated with the contextual data based on a comparison of the one or more vehicle operations made by the human driver and the one or more predicted vehicle operations. The system causes high-resolution contextual data associated with the event of interest to be stored.

Abstract: A three-dimensional model distribution method includes generating a depth image from a three-dimensional model; and distributing the depth image and information for restoring the three-dimensional model from the depth image.

Abstract: A method for constructing an image includes: defining a foreground area associated with an object in an original image; identifying a plurality of contour points defining a contour of the object; for each of the contour points, obtaining a reference contour point set that includes at least one reference contour point on each of two sides of the contour point; obtaining a plurality of characteristic lines, each associated with the reference contour point set and defined by an end point obtained from the contour points; and aligning the end points on one side to form a straight edge and making the characteristic lines adjoin each other side by side, so as to construct a reconstructed image.

Abstract: An image processing apparatus for execution of image processing on an input image is provided. The image processing apparatus includes a memory, and a processor coupled to the memory and configured to replace a partial image of a predetermined region within the input image with a test image, retain the partial image, detect presence or absence of a failure of the image processing apparatus based on the test image that has been subjected to the image processing, and replace the test image that has been subjected to the image processing with the retained partial image, after detecting the presence or absence of the failure.

Abstract: A method of generating a high-resolution image frame for a state of a video game within a 2D or 3D environment is disclosed. A low-resolution data map of a virtual camera frustum view of the 2D or 3D environment for the state is determined. The data map is of a data type. A high-resolution output data map of the data type is generated from the low-resolution data map. The generating of the high-resolution output data map includes training a neural network. The training includes associating a low-resolution data map of the data type with a high-resolution data map of the data type within the 2D or 3D environment. A high-resolution image of the frustum view is generated from the high-resolution output data map. The generated high-resolution image is displayed on a display device.

Abstract: A method and apparatus for erasing real object in augmented reality can be disclosed. The apparatus can receive an erasing area in the 3D augmented reality from a user, generate a 2D mask and a 3D mask corresponding to the erasing area, and generate a hole in the 3D augmented reality by using the 2D mask and the 3D mask. The apparatus can synthesize a first texture image for an hole area corresponding the hole by using a second texture image corresponding to an area excluding the 2D mask, calculate a first vertex value for the hole area by using a second vertex value corresponding to an area excluding the 3D mask, and perform inpainting on the hole are by using the first texture image and the first vertex value.

Abstract: In some embodiments, a given frame or picture may have different shading rates. In one embodiment in some areas of the frame or picture the shading rate may be less than once per pixel and in other places it may be once per pixel. Examples where the shading rate may be reduced include areas where there is motion and camera defocus, areas of peripheral blur, and in general, any case where the visibility is reduced anyway. The shading rate may be changed in a region, such as a shading quad, by changing the size of the region.

Abstract: This disclosure relates to a system configured to generate and provide timely vehicle event information for a fleet of vehicles including at least a first vehicle. Individual vehicles detect vehicle events and transmit related information to a remote computing server. The remote computing server determines whether the detected vehicles events are relevant to add to a set of vehicle events scenarios. For example, if a particular vehicle event is duplicative of a previous vehicle event, if may not need to be added. The newest vehicles events may be reported at certain intervals, in particular if they are indicative of a trend.

Abstract: An apparatus to facilitate cache partitioning is disclosed. The apparatus includes a set associative cache to receive access requests from a plurality of agents and partitioning logic to partition the set associative cache by assigning sub-components of a set address to each of the plurality of agents.

Abstract: Aspects of managing Translation Lookaside Buffer (TLB) units are described herein. The aspects may include a memory management unit (MMU) that includes one or more TLB units and a control unit. The control unit may be configured to identify one from the one or more TLB units based on a stream identification (ID) included in a received virtual address and, further, to identify a frame number in the identified TLB unit. A physical address may be generated by the control unit based on the frame number and an offset included in the virtual address.

Abstract: A method for operating an infotainment system of a motor vehicle in which at least one data set stored on at least one mobile terminal is transmitted wirelessly to the infotainment system and received by the infotainment system as soon as a swipe gesture has been detected on the mobile terminal wherein the at least one data set is stored first in a buffer memory of the infotainment system and only then transmitted to a further memory of the infotainment system and then processed by means of the infotainment system when a predetermined confirmation action has been detected on-board. The invention also relates to an infotainment system for a motor vehicle.

Abstract: An illumination assembly includes a light source, which is configured to emit optical radiation. A transparency containing a plurality of micro-lenses, which are arranged in a non-uniform pattern and are configured to focus the optical radiation to form, at a focal plane, respective focal spots in the non-uniform pattern. Optics are configured to project the non-uniform pattern of the focal spots from the focal plane onto an object.

Abstract: The present application discloses monitoring a plurality of time inputs to detect a defined time event and providing a report of the plurality of time inputs for analysis in response to detecting the defined time event. To create the report, an event monitor records data relating to the plurality of time inputs in a temporary memory for a defined window of time. In response to detecting the defined time event, the event monitor transfers the data recorded in the temporary memory to a persistent memory and continues to record data relating to the plurality of time inputs to the persistent memory for a second defined window of time. The event monitor provides a report of the data relating to the plurality of time inputs stored in the persistent memory for analysis.

Abstract: A method and apparatus are described for processing video data. In one embodiment, a processor is provided with a video compression engine (VCE) that has a memory having a plurality of rows and a plurality of columns of addresses. Video data, (luma data or chroma data), is written in row (i.e., raster) order into the addresses of the memory, and then the data is read out of the addresses in column order. Data is written into the addresses of the columns of the memory as they are read out, which is subsequently read out in row order. This process of switching back and forth between reading and writing data in row and column order continues as the data is read and processed by an encoder to generate a compressed video stream.

Abstract: A drawing processing apparatus is disclosed. A graphic index of a graphic included in a display screen or graphic description information which includes a setting parameter to be applied to the graphic is determined for each of regions dividing the display screen. A data size of the graphic description information is aggregated for the regions. A start address in a memory is determined to store the graphic description information into a successive storage area in the memory, based on the aggregated data size. The data size of an area of an overflow occurrence target is stored when the overflow occurs. The graphic description information of the regions is successively written from the start address when the overflow does not occur. A write process is stopped, and resumed from the area of the overflow occurrence target by using the data size when the overflow occurs.

Abstract: A new hardware architecture defines an indexing and encoding method for accelerating incoherent ray traversal. Accelerating multiple ray traversal may be accomplished by organizing the rays for minimal movement of data, hiding latency due to external memory access, and performing adaptive binning. Rays may be binned into coarse grain and fine grain spatial bins, independent of direction.

Abstract: A memory access address translating apparatus and method may each classify pixels included in an input image into a plurality of tiles, and may generate a new memory for each of the successive tiles to enable the successive tiles, among a plurality of tiles, to be stored in different banks.

Abstract: A mobile communication terminal call history displays call distinguishing icons representing the types of calls performed with counterparts. The call types include sent and received voice calls, video calls, and messages. If a user selects one call distinguishing icon displayed on a mobile communication terminal's display unit, a voice call or a video call is sent to the counterpart or a screen on which a message can be written to the counterpart is displayed, according to the call type of the selected call distinguishing icon. The user can directly select a counterpart and the call type to be sent to the counterpart by selecting one of the call distinguishing icons displayed on the display unit. A desired call distinguishing icon can be selected by entering a command on a touch screen, a keypad, or by voice command.

Abstract: An aspect of the present invention clips a sequence of data values within a known range (defined by a set of integer values) by a ceiling value and a floor value. In an embodiment, such a feature is obtained by first storing in each of a sequence of memory locations a respective value corresponding to each integer value, with a stored value in a memory location equaling the floor value if the memory location corresponds to an integer having a value less than the floor value, equaling the ceiling value if the memory location corresponds to an integer having a value greater than the ceiling value, and equaling the value of the corresponding integer otherwise. When a sequence of data values are thereafter received for clipping, the clipped value for each data value is obtained by merely retrieving a corresponding stored value from the corresponding location.

Abstract: A display system comprises a mapping memory comprising a plurality of memory banks configured to store a plurality of image tiles corresponding to an image, and an image mapping component configured to assign each of the plurality of tiles to one of the plurality of memory banks according to a first mapping or a second mapping, wherein the image mapping component determines whether to use the first or second mapping based on a bank interleaving metric of the first and second mappings.

Abstract: An image projection apparatus includes an input part that inputs image data, a frame memory that stores the image data, a laser oscillator that radiates a laser to a screen, a deflection part including a reflective optical element and configured to oscillate the reflective optical element with respect to two perpendicularly intersecting axes, a storage part that stores coefficient data of a polynomial expression, an irradiation position calculating part that calculates an irradiation position based on a coefficient obtained by using the coefficient data and an oscillation angle of the reflective optical element, an address calculating part that calculates an address in the frame memory corresponding to the irradiation position, a memory control part that reads out pixel data of the address, and a laser drive part that oscillates the laser oscillator in accordance with a luminance that corresponds to the pixel data.

Abstract: An embodiment of the present invention is a technique to control memory access. An address pre-swizzle circuit conditions address bits provided by a processor according to access control signals. A data steering circuit connects to N sub-channels of memory to dynamically steer data for a memory access type including tiled and untiled memory accesses according to the access control signals, the conditioned address bits, and sub-channel identifiers associated with the N sub-channels. The tiled memory access includes horizontally and vertically tiled memory accesses. An address post-swizzle circuit generates sub-channel address bits to the N sub-channels using the conditioned address bits and according to the access control signals and the sub-channel identifiers.

Abstract: Systems, methods, and apparatus for performing queries in a graphics processing system are disclosed. These systems, methods, and apparatus may be configured to read a running counter at the start of the query to determine a start value, wherein the running counter counts discrete graphical entities, read the running counter at the end of the query to determine an end value, and subtract the start value from the end value to determine a result.

Abstract: A method and apparatus for hardware-based anamorphic video scaling. In one embodiment, the method includes the fetch of zero or more new input pixels according to an entry of an input control memory corresponding to a current output pixel. Once fetched, the zero or more new input pixels replace at least one stored input pixel of N, input pixels. Using the updated N, input pixels and an N, coefficient set selected according to an entry of a coefficient memory corresponding to the current output pixel, a pixel computation, such as, for example, an anamorphic scaling computation, is performed. In one embodiment, the anamorphic scaling is performed by subdividing an X×Y pixel frame into X/M M×Y pixel subframes. Other embodiments are described and claimed.

Abstract: This disclosure presents techniques and structures for determining a rendering mode (e.g., a binning rendering mode and a direct rendering mode) as well as techniques and structures for switching between such rendering modes. Rendering mode may be determined by analyzing rendering characteristics. Rendering mode may also be determined by tracking overdraw in a bin. The rendering mode may be switched from a binning rendering mode to a direct rendering mode by patching commands that use graphics memory addresses to use system memory addresses. Patching may be handled by a CPU or by a second write command buffer executable by a GPU.

Abstract: A display system comprises a mapping memory comprising a plurality of memory banks configured to store a plurality of image tiles corresponding to an image, and an image mapping component configured to assign each of the plurality of tiles to one of the plurality of memory banks according to a first mapping or a second mapping, wherein the image mapping component determines whether to use the first or second mapping based on a bank interleaving metric of the first and second mappings.

Abstract: One embodiment of the present invention sets forth a technique for providing primitives and vertex attributes to the graphics pipeline. A primitive distribution unit constructs the batches of primitives and writes inline attributes and constants to a vertex attribute buffer (VAB) rather than passing the inline attributes directly to the graphics pipeline. A batch includes indices to attributes, where the attributes for each vertex are stored in a different VAB. The same VAB may be referenced by all of the vertices in a batch or different VABs may be referenced by different vertices in one or more batches. The batches are routed to the different processing engines in the graphics pipeline and each of the processing engines reads the VABs as needed to process the primitives. The number of parallel processing engines may be changed without changing the width or speed of the interconnect used to write the VABs.

Abstract: A measuring device for the efficient storage of test values and associated addresses provides a first storage region (30) and a second storage region (33). The first storage region (30) comprises a first number of memory cells (32) of a first cell size (31). The second storage region (33) comprises a second number of memory cells (35) of a second cell size (34). The measuring device further provides a third storage region (36) made from a second number of memory cells (38). A memory cell (38) of the third storage region (36) is rigidly assigned to each memory cell (35) of the second storage region (33).

Abstract: An access control device, which increases memory access efficiency to data stored in a memory, includes a plurality of groups of the memory, and divides and stores the data in different memory areas of the plurality of groups of the memory, distinguished based on predetermined bits of an access address. The access control device accesses the data stored in the different memory areas simultaneously in the same clock cycle of access to the memory. The predetermined bits of the access address are controlled independently for each of the groups of the memory. The part of the access address other than the predetermined bits controlled independently for each of the groups is common for the plurality of groups. Modes can be selected to access two horizontally or vertically consecutive unit data or data on vertically alternate lines at a time. The data may be image data or pixel data.

Abstract: An apparatus for use in helping to track a pointing device is disclosed herein. An example of the apparatus includes an orientation member coupled to the pointing device that includes a plurality of points at least some of which define a plane. The apparatus also includes a sensor to detect the plurality of points of the orientation member and a processor to determine a location in a workspace of each of the points of the orientation member detected by the sensor. The processor also determines a geometric property of the plane defined by at least some of the points of the orientation member and locates a position of an end of the pointing device along a line segment associated with the geometric property. A method for use in helping to track a pointing device in a workspace and a non-volatile storage medium are also disclosed herein.

Abstract: A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format register having a programmable format flag. The status of the format flag indicates the memory address allocation format in which the memory addresses for each of the memory arrays are allocated. An address decoder is coupled to the format register to obtain the status of the format flag in order to determine the address allocation method for an array being accessed. The address decoder is further coupled to receive a requested address for a memory location in one of the memory arrays and then provide a requested memory address to the memory arrays to access. The requested address is translated by the address decoder to the requested memory address according to the memory address allocation format indicated by the format flag status for the memory array.

Abstract: An information processing apparatus comprising: a reception unit adapted to receive a packet containing first data to be stored in a storage unit, a first address indicating an address of second data held in the storage unit, and a second address indicating an address at which the first data is to be written in the storage unit; an access unit adapted to read out the second data from the storage unit based on the first address, and write the first data in the storage unit based on the second address; and a transmission unit adapted to replace the first data of the packet received by the reception unit with the second data read out by the access unit, and transmit the packet.

Abstract: The present invention relates to a method for processing data entities by a data processing system, wherein: a first and a second set of data entities are stored in a main memory and associated with a respective first and second set of points of a domain; the first set of data entities is loaded into a local storage; one or more first calculations are performed using the first set of data entities to generate first calculated data; the second set of data entities is determined according to at least some of the first calculated data; the determined second set of data entities is loaded into the local storage; and one or more second calculations are performed using the second set of data entities resulting in second calculated data.

Abstract: The present invention provides a method and apparatus for storing image data for successive frames in a frame buffer. Specifically, the method and apparatus allow for a display-sized frame buffer to be utilized where a host system provides image data in a format different from that which the display requires to be written to it while retaining the beneficial aspects of concurrent read and write operations from and to the frame buffer. Using this method a buffer controller receives image data from a host system in a first format (e.g. row-by-row) and writes it to the frame buffer in the first format. When the buffer is completely filled with the first frame, it is read out in a second format (e.g. column-by-column) by the buffer controller and provided to a display driver that writes the data to the display.

Abstract: A data transfer circuit that transfers a first kind of data stored in an external memory circuit includes: an internal memory circuit that is capable of, by an external circuit, writing and/or rewriting a second kind of data including information for one region as a transfer source in the external memory circuit and another region as a transfer destination in the external memory circuit; a transfer circuit that transfer the first kind of data; and a control circuit that makes the transfer circuit transfer the first kind of data stored in the one region to the other region based on the second kind of data.

Abstract: A method for association based identification. The method includes providing at least one identifier and communicating identification information based on the at least one identifier. The method further includes receiving and processing identification information. Each of the at least one identifier can be associated with a color code. Identification information can be processed in a manner so as to produce association data. The association data can be associated with at least a characteristic data from a set of library data. The set of library data can correspond to a library of color codes and a characteristic data from the set of library data can correspond to a color code from the library of color codes. The association data is based upon to produce output signals. The output signals can be based on characteristic data associable with the association data.

Abstract: A DMA controller reads image information recorded on a ROM by address unit from a front reading start position. A shift operator shifts a first data sequence of one row of the reading by only a designated number of bits, and generates a second data sequence. A DMA controller reads a third data sequence already stored in a VRAM writing start position. A controller performs a prescribed operation on the second data sequence and the third data sequence, and generates a fourth data sequence. The controller writes the generated fourth data sequence successively in a horizontal direction by address unit from the VRAM writing start position.

Abstract: A drawing device includes a distinguish unit for distinguishing figure description information in scene data of each figure in a display screen, for tiles included in the display screen; an aggregation unit for aggregating a data size of the figure description information corresponding to the tiles; an address determination unit for determining a leading address in a memory area for storing the figure description information corresponding to each of the tiles, based on an aggregation result of each tile; and a memory write unit for sequentially writing, in the memory area, the figure description information distinguished as corresponding to the tiles, starting from the leading address determined for each corresponding tile, wherein the address determination unit determines the leading addresses so that the memory areas for storing the figure description information corresponding to the tiles are arranged in a physical address space in an order of drawing the tiles.

Abstract: A method including storing a data structure that defines at least part of a surface within a volume, including a non-overlapping set of sub-volumes, by specifying, for different first positions of a first straight line, a distance along the first straight line of a sub-volume of a sub-set of sub-volumes that defines the at least part of the surface; and using the data structure to control a first scanner, configured to address sub-volumes that lie along a first straight line at different positions of the first straight line, and to control a second scanner, configured to address sub-volumes that lie along a second straight line for different positions of the second straight line, to address co-operatively the sub-set of sub-volumes that defines the at least part of the surface.

Abstract: A display interface buffer includes a general purpose memory to store data capable of being displayed on a panel, a plurality of display drivers to receive data from the general purpose memory, each of the display drivers to drive a different portion of the panel with the data, and processor or a direct memory access controller to access data in the general purpose memory and to provide the data to the display drivers for presentation on the panel.

Abstract: An image processing method applied to an image processing device is capable of implementing bitstream stitching technique after interrupting image processing process. The image processing method includes steps of processing the i-th slice of N slices in an image to generate a plurality of first processed data; storing the first processed data in a memory unit; once an interrupting request is generated according to a requested process, storing stitching information associated with the last first processed data after processing the i-th slice; stopping processing the image and executing the requested process according to the interrupting request; continuing to process the (i+1)-th slice of the N slices to generate a plurality of second processed data after the requested process is finished; and storing the second processed data after the last first processed data in the memory unit according to the stitching information.

Abstract: In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed.

Abstract: A CPU divides a moving image file at a divided frame position, thereby generating a first divided moving image file including a first frame and another divided moving image file. The CPU detects a frame position where an object appears for the first time in the reproduction order from the other divided moving image file, and generates a file that describes the detected position as a new face information management file. The CPU controls a recording/reproduction control circuit to store the generated new face information management file in a recording medium in association with the other divided moving image file.

Abstract: Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.

Abstract: Intercepting a requested memory operation corresponding to a conventional memory is disclosed. The requested memory operation is translated to be applied to a structured memory.

Abstract: Disclosed is an image processing apparatus for inputting a plurality of rectangular images each composed of n×n pixels and outputting line-by-line image data in which one line is composed of n×n×m pixels. A line buffer stores n lines of image data, each line is composed n×n×m pixels. The apparatus generate a write address for writing a rectangular image to the line buffer memory and a read-out address for reading line-by-line image data out of the line buffer memory, and changes over a method of generating the write address between a first write-address generating method and a second write-address generating method whenever m rectangular images are written to the line buffer, and changes over the read-out address between a first read-out-address generating method and a second read-out-address generating method whenever n lines of image data are read out of the line buffer.

Abstract: A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size of the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.

Abstract: A system comprises a memory storing data at addresses associated with pixels in images, each address being linked by a function to coordinates of a pixel in an ordered image reference frame, a device for processing the data associated with the pixels, where a pixel being processed is referenced by an associated vector relative to a reference pixel, and an interface device providing data to the processing device. A data request indicates a vector associated with a pixel being processed. The coordinates of the reference pixel are determined by applying the function to an address associated with the reference pixel. The coordinates of the pixel being processed are obtained based on the coordinates of the reference pixel and the vector. Then the address of the data associated with the pixel being processed is determined by applying the inverse function of the function to the coordinates of the pixel being processed.

Abstract: A display controller is provided that includes a processing unit configured to process input data, a memory unit configured to store some of the processed input data before a transition signal is enabled, a memory management unit configured to map consecutive virtual addresses of an image displayed on a display panel to physical addresses of data stored in the memory unit, and a control unit configured to control the processing unit and the memory management unit in response to a control signal and configured to provide a range of virtual addresses designated by the transition signal in response to enablement of the transition signal such that the image is displayed on the display panel.

Abstract: A flat display device has a circuit configuration in which a division-driving system and an aspect conversion are integrated with each other, and performs driving appropriate to achieve higher resolution even in driving a display unit. The device comprises a memory circuit which includes n unit memories each storing unit data, a display unit of which the horizontal driver is supplied signals read from the memory circuit and of which the regions divided into a plurality of portions in a horizontal direction is division-driven, and a memory control circuit which divides a digital video signal of one line into n, supplies n pieces of the unit data to the n unit memories, selects each direction of write or read addresses of the n unit memories, and outputs the read addresses so that the arrangement order of the unit data for the adjacent regions is set in an inversion horizontal direction.