Abstract: Audio data and video data are processed to determine one or more audible events and visual events, respectively. Contemporaneous presentation of the video data with audio data may be synchronized based at least in part on the audible events and the visual events. Audio processing functions, such as filtering, may be initiated for audio data based at least in part on the visual events.

Abstract: According to one embodiment, an information processing apparatus includes a receiver configured to receive content, an acquiring unit configured to acquire a time required for reproducing the content, a counter configured to count a first time including at least the required time, and a display controller configured to display the content on the display unit and terminate display of a video on the display unit after expiration of the first time.

Abstract: A data processing device includes a clock converter, a data converter, and an error detector. The clock converter is configured to receive a first clock signal, convert the first clock signal into a second clock signal, and output the second clock signal. The data converter is configured to receive first data, convert the first data into second data using the second clock signal, and output the second data. The error detector is configured to check whether the first clock signal is in a first clock state or a second clock state upon the first data transitioning to a first data state, and output an enable signal to the clock converter upon determining that the first clock signal has transitioned to the first clock state from the second clock state.

Abstract: Digital television channels are preemptively cached based on a modeling of a user to reduce delays while switching channels. A current television channel is selected using a first tuner. A future television channel selection of the user is then predicted based on a modeling of the user. The recorded content of the predicted future television channel is preemptively cached using a second tuner. A buffer of the recorded content of the predicted future television channel is displayed when the user switches from the current television channel to the predicted future television channel. The modeling of the user is updated and stored in storage.

Abstract: There is provided a video processing device capable of reducing the influence of a disturbance of an input vertical synchronization signal. When the synchronization signal detecting unit detects an input of the input-side vertical synchronization signal at a predetermined cycle, the synchronization signal control unit outputs the input-side vertical synchronization signal, which has been input, as an output-side vertical synchronization signal, and, when the synchronization signal detecting unit detects an input of a next input-side vertical synchronization signal before the predetermined cycle elapses after the output of the output-side vertical synchronization signal, a next input-side vertical synchronization signal input before the predetermined cycle elapses is not output as a next output-side vertical synchronization signal, and an input-side vertical synchronization signal input further next is output as the next output-side vertical synchronization signal.

Abstract: An electronic device having a clock portion for counting time and having the time on the clock portion set based on time information acquired from outside has a notification portion that communicates information of the time counted by the clock portion to an external device via a physical line. Alternatively, an electronic device has a first clock portion counting time and an acquisition portion that acquires, from an external device having a second clock portion for counting time and having the time on the second clock portion set based on time information acquired from outside, information of the time counted by the second clock portion via a physical line, and the time on the first clock portion is set based on the information acquired by the acquisition portion.

Abstract: A synchronization signal control circuit according to embodiments includes a phase difference detecting section and a vertical synchronization correction control section. When a vertical synchronization period of an input video signal is within a compensation period range between a minimum vertical synchronization period and a maximum vertical synchronization period, the synchronization signal control circuit outputs a display vertical synchronization signal used for displaying the input video signal to a display section capable of providing a display based on the input video signal. The phase difference detecting section detects a phase difference between an input vertical synchronization signal based on the input video signal and the display vertical synchronization signal. The vertical synchronization correction control section corrects the cycle period of the display vertical synchronization signal within the compensation period range so as to reduce the phase difference.

Abstract: The present document describes a CPU platform interface method and device for synchronizing a stream of motion codes with a video stream. The method and device use the video stream time stamps and movie identity information from the software movie player along with the CPU time clock to fill a queue of motion code frames and determine when the frames will be sent as a motion stream to one or more actuators of a motion platform.

Abstract: A video apparatus for processing an input video signal in synchronization with an external reference signal is provided. The video apparatus includes a phase compensation FIFO memory and a measuring device. The phase compensation FIFO memory is configured such that the input video signal is written in synchronization with a clock demodulated from the input video signal and the video signal is read in synchronization with an internal reference clock of the apparatus generated from the external reference signal. The measuring device is configured to measure an amount of jitter/wander of the input video signal based on a calculation of a difference between data volume of the video signal obtained in the FIFO memory and a predetermined reference volume.

Abstract: Apparatus and methods disclosed herein operate to monitor times of receipt of start-of-frame indications associated with frames received from multiple image sensors at a video controller. Time differences between the times of receipt of the frames are calculated. Embodiments herein alter one or more frame period determining parameter values associated with the image sensors if the time differences equal or exceed frame synchronization hysteresis threshold values. Parameter values are adjusted positively and/or negatively to decrease the time differences. The parameter values may be reset at each image sensor when the time differences become less than the frame synchronization hysteresis threshold value as additional frames are received at the video controller.

Abstract: The present document describes a CPU platform interface method and device for synchronizing a stream of motion codes with a video stream. The method and device use the video stream time stamps and movie identity information from the software movie player along with the CPU time clock to fill a queue of motion code frames and determine when the frames will be sent as a motion stream to one or more actuators of a motion platform.

Abstract: A method and an apparatus for synchronizing a data stream are disclosed. The method comprises: decoding the data stream to generate a decoded data stream and program clock references; generating a local clock reference; generating a simulated clock reference according to the program clock references and the local clock reference; comparing the local clock reference with the simulated clock reference; adjusting a processing timing of the decoded data stream according to the comparison result; and processing the decoded data stream according to the processing timing.

Abstract: A synchronization signal control circuit according to embodiments includes a phase difference detecting section and a vertical synchronization correction control section. When a vertical synchronization period of an input video signal is within a compensation period range between a minimum vertical synchronization period and a maximum vertical synchronization period, the synchronization signal control circuit outputs a display vertical synchronization signal used for displaying the input video signal to a display section capable of providing a display based on the input video signal. The phase difference detecting section detects a phase difference between an input vertical synchronization signal based on the input video signal and the display vertical synchronization signal. The vertical synchronization correction control section corrects the cycle period of the display vertical synchronization signal within the compensation period range so as to reduce the phase difference.

Abstract: A method and an apparatus for synchronizing a data stream are disclosed. The method includes: decoding the data stream to generate a decoded data stream and program clock references; generating a local clock reference; generating a simulated clock reference according to the program clock references and the local clock reference; comparing the local clock reference with the simulated clock reference to generate a comparison result; adjusting a processing timing of the decoded data stream according to the comparison result; and processing the decoded data stream according to the processing timing.

Abstract: There is provided a system and method for accommodating submissions of invalid system time table information. More specifically, in one embodiment, there is provided a method comprising receiving a first video-based time signal from a video source, determining a first CPU-based time signal, receiving a second video-based time signal from the video source, determining a second CPU-based time signal, subtracting the first video-based time signal from the second video-based time signal to produce a first time difference, subtracting the first CPU-based time signal from the second CPU-based time signal to produce a second time difference, and accepting the video source as a valid time source if the first time difference substantially matches the second time difference.

Abstract: A system for overlaying a motion video signal onto an analog signal on a display. The system includes a motion video processing unit for receiving and processing the motion video signal into a signal having an analog video format, a video format analyzer and synchronizer device for receiving the analog signal and for determining video timing parameters and a corresponding original pixel clock of the analog signal and for controlling video timing parameters of the motion video signal to match the video timing parameters of the analog signal determined by the video format analyzer and synchronizer device so as to provide an output motion video signal which is synchronized with the analog signal and a display determining device for determining the display of the analog output signal or the synchronized output motion video signal on the display.

Abstract: An architecture is presented that synchronizes digital television content with IP network content. A content management system is provided that comprises a computing system that includes an input component and an application component. The input component of the computing system receives digital television content of a broadcast network. The application component receives IP network content of an IP network. The application component then synchronizes the IP network content and the digital television content via DSM-CC stream events. The DSM-CC stream events are markers that comprise an event identifier and a time reference. Based on the event identifier and the time reference, the broadcasted digital television content can be synchronized with the IP network content to deliver additional content media and commercials tailored to specific groups of viewers based on demographics, geography and/or individual profiles.

Abstract: An image processing apparatus is provided that is capable of performing combining processing of image from image processing sections without the intermediation of a frame buffer, and can reduce the delay between image input and display and improve real-time capability. An image processing main chip 110 of a three-input image processing system 100 reads image data stored in frame buffers of storage apparatuses 117 through 119 in accordance with the line frequency of a display section 114, collects, in line units, image data processed by image processing subchips 111 and 112, performs combining processing in line units of the collected image data and image data it has processed itself, and outputs the combined data to display section 114, and image processing subchips 111 and 112 transfer processed image data to image processing main chip 110 in line units.

Abstract: Method and system for fine tuning frequency and phase of a sampling clock of analog signals (R, G, B) having digital information, for sampling the analog signals within an optimal sampling period, enabling optimal display by a digital display device (92). Small amount of information from input signals is required for rapidly and accurately determining values of frequency and phase of the sampling clock. After measuring using a measurement system (96) and obtaining pixel values while sweeping phase values of signals using a phase locked loop (PLL) mechanism (48), there is determining values of two parameters, (i) error of an initial frequency value of the sampling clock (Rx clock), proportional to error of an initial phase locked loop (PLL) division factor value, and (ii) phase of the sampling clock, without need for making additional measurements based on these values, using a control unit (94).

Abstract: A video apparatus for processing an input video signal in synchronization with an external reference signal is provided. The video apparatus includes a phase compensation FIFO memory and a measuring device. The phase compensation FIFO memory is configured such that the input video signal is written in synchronization with a clock demodulated from the input video signal and the video signal is read in synchronization with an internal reference clock of the apparatus generated from the external reference signal. The measuring device is configured to measure an amount of jitter/wander of the input video signal based on a calculation of a difference between data volume of the video signal obtained in the FIFO memory and a predetermined reference volume.

Abstract: A false DE rejection system is described. DEs are ignored during a programmable vertical lockout period. Internal timing is used during the vertical lockout period to count the number of vertical lines to ignore. The first DE received after the vertical lockout period signifies the start of the next graphics frame. Default video is output during the vertical lockout period. The TCON is synchronized to the start of the graphics frame. A horizontal line length timer measures the timing for the horizontal line length. The horizontal line length timer may also keep a moving average of all of the lines that it has measured. This helps to ensure that the TCON does not get out-of-sync with the input stream during the vertical blanking periods. The DE rejection system includes automatic blanking detection that ignores DEs that occur after the end of a predetermined graphics frame. The vertical lockout does not occur until there has been no DE for an entire line.

Abstract: A mask circuit masks a digital video signal so that a video signal of an analog video signal is not outputted for a predetermined period after the start of output of a horizontal synchronizing signal of the analog video signal. A period of masking the digital video signal by the mask circuit is set in a control register, and the control register transmits the masking period to the mask circuit. A digital video signal to analog video signal converting unit converts the digital video signal masked and outputted from the mask circuit into an analog video signal. Thus, by setting in the control register the period of masking the digital video signal until the video signal of the analog video signal is stabilized, a digital video encoder can output a stable video signal.

Abstract: A method, apparatus, and computer-readable media for recovering a symbol clock signal from an American Television Standards Committee (ATSC) digital television (DTV) signal comprises coherently downconverting the ATSC DTV signal to a baseband signal; delaying the baseband signal; multiplying the baseband signal and the delayed baseband signal; band-pass filtering the symbol clock signal; and generating the symbol clock signal based on the filtered baseband signal.

Abstract: A system for overlaying a motion video signal onto an analog signal on a display. The system includes a motion video processing unit for receiving and processing the motion video signal into a signal having an analog video format, a video format analyzer and synchronizer device for receiving the analog signal and for determining video timing parameters and a corresponding original pixel clock of the analog signal and for controlling video timing parameters of the motion video signal to match the video timing parameters of the analog signal determined by the video format analyzer and synchronizer device so as to provide an output motion video signal which is synchronized with the analog signal and a display determining device for determining the display of the analog output signal or the synchronized output motion video signal on the display.

Abstract: A video timing system and method. The method typically includes receiving from an input video stream an input video field in a video buffer, transmitting an output video field from the video buffer to an output video stream, measuring a time interval between a predetermined point on the input video field and a predetermined point on the output video field, and altering timing of the output video stream where the time interval is outside a predetermined range.

Abstract: A web television includes a display, a tuner, an internet module, and a PIP module. The tuner is arranged to select television video for display on the display and to select television audio for display by a speaker of the web television. The internet module is arranged to supply internet video for display on the display and to supply internet audio for display by the speaker of the web television, and the internet video and audio are derived from internet communications between the web television and internet content providers. The PIP module is arranged to provide a PIP area within a main area of the display. The internet video and the television video may be swapped between the PIP area and the main area of the display, and the speaker of the web television may be swapped between the internet audio and the television audio.

Abstract: The present invention relates to a method of playing a set of multimedia applications (A), each multimedia application including a list of tasks (TTD). The method includes the steps of creating a common scheduler (SCH) at a start time, in order to provide a target time, registering the tasks into the scheduler, and controlling the execution of the tasks as a function of the target time. The method also includes a step of giving a priority level to the task and the scheduler is adapted to control the execution of the tasks as a function of the target time and the priority level. The method further includes a step of computing a local time for a task from the target time provided by the scheduler and timing information associated with said task. With such a mechanism, each task has its own time reference, thus ensuring a correct operation of the overall application, while a global notion of schedule is maintained.

Abstract: A method and apparatus for retiming video. Vertical synchronization information (VSI) is detected in an incoming video stream. A VSI is also detected in both as output video stream and a reference video stream. Based on the difference between the VSI of the reference and output video stream reads or writes to a FIFO are suppressed until the VSI's are coincident.

Abstract: The system for updating a clock in an electronic device, such as a personal computer, has a receiver system having an input for receiving a real time signal and having an output on which is provided digital information representative of the real time signal. An extraction module is operatively coupled to the receiver system, the extraction module extracting at least a current time value from the display data. An update module is operatively coupled to the extraction module, the update module updating the clock in the computer when the current time value of the digital information differs from a current value of the clock in the computer. In one embodiment a validating unit is operatively coupled between the extraction module and the update module. The validating unit compares channel identification data derived from the display data to time zone data in the computer, the time zone data being indicative of a time zone in which the computer is currently located.

Abstract: A computer system includes a graphics controller with a first refresh rate and a first horizontal synchronization signal; a secondary source of video data having a second refresh rate and a second horizontal synchronization signal; and a genlock unit for reconciling the first refresh rate of the graphics controller with the second refresh rate of the secondary source. The genlock unit outputs a clock signal with a frequency modulated to reconcile the first refresh rate and the second refresh rate by monitoring the phase differences of the first horizontal synchronization signal and the second horizontal synchronization signal in response to a first control signal and outputs a clock signal at a frequency corresponding to a selected clock frequency in response to a second control signal.

Abstract: An apparatus and method for converting pixel data from a computer video format to a television-compatible composite video waveform. A color space converter converts RGB or YCrCb pixel data into YUV pixel data. The YUV pixel data is supplied to an encoder which encodes the data into a composite video waveform. A clock generator generates an encoder clock frequency based on the horizontal resolution of the incoming computer pixel data. The encoder clock frequency is sufficient to allow encoding of all incoming pixels in the active video portion of the waveform without physically scaling or altering the pixel data. Sync and burst processors in the encoder encode sync pulses and burst waveforms at proper timing intervals despite the variable encoder clock frequency by accessing sync pulse and burst waveform values and timing parameters appropriate to ranges of clock frequencies that are stored in a ROM.

Abstract: In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an AID converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of White-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum.

Abstract: The present invention provides a method and apparatus for providing video output phase control in a decoder. In particular, the present invention provides a decoder that precisely aligns output of video display data with a time stamp associated with the video display data and thereby allows for efficient usage of compressed video buffer memory in the decoder. In one embodiment, the decoder includes a video output processor for displaying video data and a timer connected to the video output processor for providing video output phase control. A method is also provided for providing video output phase control in the decoder.

Abstract: A method and apparatus for phase-locking a plurality of display devices and multi-level driver for use therewith. Each of the display devices displays an image under the control of a distinct clock having a distinct clock rate. Each of the images contains a predetermined periodic indexing event. One of the clocks is designated as a master clock. The times of occurrence of the indexing events are compared, and the times of occurrence are caused to fall within a predetermined amount of time of one another so that each of the other clocks is phase-locked with the master clock.

Abstract: This invention is directed to a method and apparatus for producing video signal timing for a display device that has a display format different from the input video format. It also provides a method and apparatus for producing video signal timing in cases where the input video line rate and display output line rates are not the same. Furthermore, a method and apparatus are provided for synchronizing the display output line rate to the input line rate so that the source video line input rate can sustain the rate at which the input lines are processed to generate display video lines using a minimum amount of memory buffer for a variety of display processing methods. Another aspect of the present invention provides a method and apparatus for synchronizing display output timing to input video timing such that both are locked in terms of frame rate, but skewed in terms of frame phase, in order to accommodate latency incurred by processing of source video data to generate the display video data.

Abstract: An image display system reproduces a dot clock on the basis of a horizontal sync signal that is generated from a host computer and displays an image on a display unit such as a ferroelectric liquid crystal display. In the host computer, a graphic card is provided with a transmitting unit for transmitting information necessary for display. The display unit comprises a receiver to receive the information necessary for the display and a change unit to change the display contents on the basis of the information received by the receiver. The information necessary for the display includes a sync signal frequency, a dot clock frequency, and an image information display period.

Abstract: A counter control circuit of a counter for measuring a pulse period of a video synchronization signal includes a main control unit having a synchronization signal input Sync, and a control signal producing unit including a stop signal generator, a latch signal generator, and a start signal generator. The outputs of the stop, latch and start signal generators are supplied to the counter for controlling the counter to count clock pulses fed from a clock generator in response to receipt of a start signal and output a count value in response to receipt of a latch signal. The main control unit produces sequential control signals during the input of the video synchronization signal differentiated by the clock pulses. The counter control circuit allows the counter to measure a pulse period of an input synchronization signal in a stable state that results in an accurate count value, since the count operation is first stopped and the count value is latched by the clock signal.

Abstract: A process and system for synchronizing a video signal to the sampling period of a client system. The synchronization may be suitably implemented by adding or deleting trailing lines from each frame of video data to adjust the frame to match the sampling period of the client system. The synchronization system minimizes the lag between the time a video signal is delivered to the client system and the time the client system responds. The low lag time enhances the responsiveness of the client system to human inputs, and improves the suitability of the overall system to human use. The synchronization system can be achieved using suitable low-cost hardware and is therefore particularly well suited for video game or virtual reality systems designed for home use, increasing the feasibility of employing video inputs in such systems.

Abstract: A sync signal self-test device includes: a pre-amplifier, for pre-amplifying red, green, and blue video signals from a computer system; a microprocessor, for checking the horizontal and vertical sync signal frequencies, and for controlling production of on screen display signals when the horizontal and vertical sync signal frequencies from the computer system are outside the operating range of the monitor, and for generating horizontal and vertical sync signals; an on screen display integrated element, for outputting, under the control of the microprocessor, error message signals in synchronization with control signals from the microprocessor; a buffer, for temporarily storing output signals from the on screen display integrated element; a mixing element, for mixing outputs of the pre-amplifier and the buffer; and a main amplifier, for amplifying the output of the mixing element for the picture tube.

Abstract: A sync signal processing device for a combined video appliance capable of directly processing a personal computer (PC) signal through a television (TV) receiver circuit to achieve the horizontal and vertical driving and deflection. The device can prevent the vertical trembling phenomena of the displayed picture and on-screen display by compensating for the sync frequency difference between the PC signal and the TV signal. According to the devices either a TV sync signal or a PC sync signal is selected in accordance with a selected TV/PC mode after the PC sync signal is frequency-converted and the selected PC sync signal is processed through the TV sync signal processing circuit. Either the horizontal driving pulse signal form the TV sync signal processing circuit or the horizontal driving pulse signal produced from a separate horizontal oscillation circuit is selected and outputted to a horizontal output circuit in accordance with the selected TV/PC mode.

Abstract: A method and apparatus for raster calibration is described. Calibration circuitry operates in the context of a local video subsystem which receives at least one sync signal from a remote video (typically graphics) subsystem. The calibration circuitry calibrates a local raster of the local video subsystem to a remote raster of the remote video subsystem. The calibration circuitry includes measurement circuitry for measuring a first duration of a first phase of the sync signal, and for measuring a second duration of a second phase of the sync signal. Processing logic compares the first and second durations and determines that the phase having the shorter duration is an active phase, the active phase corresponding to the polarity of the sync signal. The processing logic also adds the first and second durations to provide an estimate of the scan line period of the remote raster.

Abstract: A digital motion video processing circuit can capture, playback and manipulate digital motion video information using the system memory of a computer as a data buffer for holding compressed video data from the circuit. The system memory may be accessed by the circuit over a standard bus. A controller in the circuit directs data flow between an input/output port which transfer a stream of pixel data and to the standard bus. The controller directs data to and from either the standard bus or the input/output port through processing circuitry for compression, decompression, scaling and buffering. The standard bus may be a peripheral component interconnect (PCI) bus. The motion video processing circuit has a data path including pixel data and timing data indicative of a size of an image defined by the pixel data. The timing data is used and/or generated by each component which processes the pixel data, thereby enabling each component to process the pixel data without prior knowledge of the image format.

Abstract: A controller for synchronising video signals for displaying on TV screen.

Abstract: Apparatus and method for automatically adjusting a picture size of a video appliance such as a monitor. According to the apparatus and method, since electrical characteristic data of the video appliance employing the apparatus of the present invention is preset therein, regardless of input of any external data, a user's one time input or automatic picture-adjusting mode selection makes external input data and preset characteristic data be compared, and the horizontal and vertical picture size of the video appliance in the video appliance is automatically adjusted. Therefore, the adjusting step is simplified in the manufacturing process of monitor, promoting productivity, and decreasing the cost thereof.

Abstract: In a graphics card of a computer, a circuit is provided for displaying graphic presentations generated by the card on an external TV set. A TV adapter controls a horizontal state machine of a CRT controller so as to delay generation of CRT timing signals by a time period variable with horizontal lines. As a result, a composite video signal is provided with a time-base variable front porch to simulate VTR video signals. In response to the generated composite video signal, the TV set switches into a VTR mode to disable a comb filter used for separating luminance and chrominance components of a broadcast television signal.

Abstract: To interface a video/graphic controller, which produces conventional, ana video output signals, suitable mostly for CRT type displays, to a matrix display, one of the video output signals, for example the horizontal sync signal, is encoded with the clock frequency and phase information used in generating the original video output signals. The encoded information is decoded at the display end, by extracting from it the clock information and synthesizing a clock signal which has the identical frequency and phase as the original clock used at the video/graphic controller. The replicated clock signal is used as a clock input to the matrix display, to assure that the video output signals are displayed at the correct pixel locations of the matrix display, preventing picture jitter and/or loss of video/graphics data.

Abstract: A method and apparatus for raster calibration is described. Calibration circuitry operates in the context of a local video subsystem which receives at least one sync signal from a remote video (typically graphics) subsystem. The calibration circuitry calibrates a local raster of the local video subsystem to a remote raster of the remote video subsystem. The calibration circuitry includes measurement circuitry for measuring a first duration of a first phase of the sync signal, and for measuring a second duration of a second phase of the sync signal. Processing logic compares the first and second durations and determines that the phase having the shorter duration is an active phase, the active phase corresponding to the polarity of the sync signal. The processing logic also adds the first and second durations to provide an estimate of the scan line period of the remote raster.

Abstract: A monolithically integratable display apparatus for receiving a picture signal having frames of video information and horizontal and vertical synchronizing components includes a matrix of display cells arranged in an array of M rows by N columns. Display cells in the matrix are individually addressable by row and column signals so as to receive the video information in the picture signal in response thereto. A first shift circuit coupled to the matrix provides the row signals in response to a first clocking signal and a data signal. A second shift circuit coupled to the matrix provides the column signals in response to a second clocking signal. A first clock circuit, such as a phase locked loop, receives the horizontal synchronizing component of the picture signal and produces the second clocking signal in response thereto. A synchronizing detector circuit receives the vertical synchronizing component of the picture signal and produces the data signal in response thereto.

Abstract: A technique to derive a television color subcarrier frequency signal from a computer video signal is described. A computer generates a computer video signal including a horizontal synchronization signal component. The horizontal synchronization signal component is applied to a subcarrier frequency generator to produce a pixel clock signal and a subcarrier relative phase signal which are applied to a digital encoder. The digital encoder processes the computer video signal, the pixel clock signal, and the subcarrier relative phase signal to generate an analog baseband television signal. The subcarrier frequency generator includes a frequency conversion circuit, a timing source, and a deviation compensator. The conversion circuit receives the horizontal synchronization signal and generates the pixel clock signal. The timing source is used to generate a reference clock signal.

Abstract: The present invention relates to a method of aligning and blending input digital samples, comprised of delaying the input samples by a clock pulse, to provide delayed data samples, subtracting a smaller fractional part from a larger fractional part of either an input sample number and a requested sample number to provide a sample difference number first factor, subtracting the sample difference number from 1 to provide a second factor, multiplying either of the input samples or the delayed samples by the first factor to provide a first result, multiplying the other of the input samples or the delayed samples by the second factor to provide a second result, and adding the results to provide output samples.