Abstract: Provided is a video processing device that generates a display video signal to be supplied to a liquid crystal display having a liquid crystal that is driven by a frame inversion scheme and includes a control microcomputer and a video signal processor. The control microcomputer controls a data enable signal such that a display invalid section having a predetermined number of fields is set for an interlace video signal at a predetermined period based on a vertical synchronization signal included in the interlace video signal input from outside. The video signal processor generates the display video signal by setting the display invalid section for the interlace video signal based on the data enable signal and outputs the display video signal to the liquid crystal display.

Abstract: A deinterlacing apparatus includes a buffer to receive a plurality of consecutive fields of an interlaced video and a field combination module coupled to the buffer to deinterlace the interlaced video in accordance with cadence of the interlaced video. The deinterlacing apparatus also includes a cadence detection module to detect the cadence by (1) causing each of the fields to be combined with its preceding field into a frame and with its subsequent field into another frame to obtain a plurality of combined frames, (2) determining a comb factor of each of the combined frames to obtain a sequence of comb factors of the combined frames, and (3) determining if the sequence of comb factors of the combined frames follows a pre-determined repeating pattern. A cadence detection method is also described.

Abstract: Systems and methods are provided for upscaling a digital image. A digital image to be upscaled is accessed, where the digital image comprises a plurality of pixel values. A first half pixel value is computed for a first point in the digital image based on a plurality of pixel values of the digital image surrounding the first point and an activity level. A second half pixel value is computed for a second point in the digital image, and an interpolated pixel of an upscaled version of the digital image is determined using a plurality of the pixel values, the first half pixel value, and the second half pixel value.

Abstract: A method for de-interlacing interlaced video includes receiving a first video field and a second video field of an interlaced video frame, generating a first video frame from the first video field and a first synthesized video field, where video data of the first synthesized video field is based exclusively on video data of the first and second video fields, generating a second video frame from the second video field and a second synthesized video field, where video data of the second synthesized video field is based exclusively on the video data of the first and second video fields, and outputting two de-interlaced video frames for every received interlaced video frame. The first (second) synthesized video field is generated by combining image data from the second (first) video field with image data from corresponding lines of an up-scaled first (second) field generated by a scaler.

Abstract: A method in a television receiver receiving interlaced analog modulated television signals includes: detecting an inactive video period in the television signal between two successive video display fields; generating a synchronization signal indicative of the detected inactive video period; and in response to the synchronization signal, performing measurement and adjustment operations on analog circuitry of the television receiver. In another embodiment, a method in a television receiver receiving interlaced analog modulated television signals includes: detecting an inactive video period between two successive video display fields using a not-fully-demodulated intermediate frequency (IF) signal; and generating a synchronization signal indicative of the detected inactive video period.

Abstract: The present invention provides an apparatus for interpolation which is able to process input data with multiple video standards without sacrificing chip area. The interpolation unit comprises: a first interpolation unit for interpolating input data; a second interpolation unit for interpolating input data; a filter indicator for providing information to the first interpolation unit and the second interpolation unit; and an output unit for multiplexing and averaging output from the first interpolation unit and the second interpolation unit. The present invention also provides a motion compensation unit and a decoder for processing multiple video standards.

Abstract: A method in a television receiver receiving interlaced analog modulated television signals includes: detecting an inactive video period in the television signal between two successive video display fields; generating a synchronization signal indicative of the detected inactive video period; and in response to the synchronization signal, performing measurement and adjustment operations on analog circuitry of the television receiver. In another embodiment, a method in a television receiver receiving interlaced analog modulated television signals includes: detecting an inactive video period between two successive video display fields using a not-fully-demodulated intermediate frequency (IF) signal; and generating a synchronization signal indicative of the detected inactive video period.

Abstract: An image-data processing apparatus includes a writer which writes image data into a memory according to a non-interlaced-scanning or an interlaced-scanning of each N line. An updater updates a cumulative zoom coefficient by accumulating, for each line, a decimal portion of the cumulative zoom coefficient to a first numerical value corresponding to the zoom coefficient. An accumulator accumulates, for each line, a second numerical value corresponding to an integer portion of the cumulative zoom coefficient. A reader reads out image data in a line corresponding to an accumulated value of the accumulator. A first setter sets N-times the zoom coefficient to the first numerical value in the non-interlaced-scanning, and sets the zoom coefficient to the first numerical value in the interlaced-scanning. A second setter sets an integer portion to the second numerical value in the non-interlaced-scanning, and sets N-times the integer portion to the second numerical value in the interlaced-scanning.

Abstract: A video apparatus for processing an input video signal in synchronization with an external reference signal is provided. The video apparatus includes a phase compensation FIFO memory and a measuring device. The phase compensation FIFO memory is configured such that the input video signal is written in synchronization with a clock demodulated from the input video signal and the video signal is read in synchronization with an internal reference clock of the apparatus generated from the external reference signal. The measuring device is configured to measure an amount of jitter/wander of the input video signal based on a calculation of a difference between data volume of the video signal obtained in the FIFO memory and a predetermined reference volume.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate a first control signal, a second control signal and a third control signal in response to a first interlaced video signal. The second circuit may be configured to generate a second interlaced video signal in response to the first interlaced video signal, the first control signal, the second control signal and the third control signal. The second circuit may be further configured to vertically scale the first interlaced video signal in an extended vertical domain.

Abstract: A microscope image pickup system includes: alight source; an object lens; a display device; a record device; a capture device for performing a preview mode in which an image of the test object obtained by the object lens is repeatedly captured and a plurality of captured images are continuously displayed on the display device, or an image record mode in which the image of the test object is captured and the captured image is recorded on the record device; an illumination light amount control device for controlling the amount of light of the illumination light; and a system control device for controlling an operation of the illumination light amount control device depending on the preview mode or the image record mode performed by the capture device.

Abstract: A decoder receives a field start code for an entry point key frame. The field start code indicates a second coded interlaced video field in the entry point key frame following a first coded interlaced video field in the entry point key frame and indicates a point to begin decoding of the second coded interlaced video field. The first coded interlaced video field is a predicted field, and the second coded interlaced video field is an intra-coded field. The decoder decodes the second field without decoding the first field. The field start code can be followed by a field header. The decoder can receive a frame header for the entry point key frame. The frame header may comprise a syntax element indicating a frame coding mode for the entry point key frame and/or a syntax element indicating field types for the first and second coded interlaced video fields.

Abstract: Techniques and tools for coding/decoding of digital video, and in particular, for determining, signaling and detecting entry points in video streams are described. Techniques and tools described herein are used to embed entry point indicator information in the bitstream that receivers, editing systems, insertion systems, and other systems can use to detect valid entry points in compressed video.

Abstract: A liquid crystal display apparatus includes synchronization signal extracting means for extracting a vertical synchronization signal from a noninterlace signal, first reversal signal generating means for generating a first polarity reversal signal that causes reversal of polarity of a signal voltage every frame for a switching device associated with each of pixels according to the vertical synchronization signal, reversal control signal generating means for generating a reversal control signal according to a result of comparison between frames of the noninterlace signal, second reversal signal generating means for generating a second polarity reversal signal by reversing polarity of the first polarity reversal signal according to the reversal control signal, and switching device driving means for driving each of switching devices according to the second polarity reversal signal.

Abstract: A method and apparatus for displaying characters on a TV screen in an electronic appliance such as a DVD player is disclosed. Vertically compressed character fonts are stored. When it is requested to display a character, the stored character font is read and displayed in a video field and then the character font is displayed again in the next video field, whereby flickering can be effectively eliminated with a reduced-size memory for storing fonts data.

Abstract: An encoder/decoder uses “self-referencing” frames. For example, a second B-field in a current frame references the first B-field from the current frame in motion compensated prediction. Allowing the first B-field in a frame to act as a reference for the second B-field in the frame allows more accurate prediction of the second B-field, while also preserving the temporal scalability benefits of having B-fields in the current frame.

Abstract: A video decoder receives an entry point key frame comprising first and second interlaced video fields and decodes a first syntax element comprising information (e.g., frame coding mode) for the entry point key frame at a first syntax level (e.g., frame level) in a bitstream. The first interlaced video field is a predicted field, and the second interlaced video field is an intra-coded field. The information for the entry point key frame can be a frame coding mode (e.g., field interlace) for the entry point key frame. The decoder can decode a second syntax element at the first syntax level comprising second information (e.g., field type for each of the first and second interlaced video fields) for the entry point key frame.

Abstract: The scan converter comprises first and second memories 3, 7, a frame memory 5; having a write period and a read period, a video data input circuit 2 for writing data at a first transfer rate into the memory 3, a video data output circuit 8 for outputting the data from the memory 7 at a third transfer rate. The transfer rate between the memories 3, 7 and the memory 5 is twice as fast as the first or third transfer rate, whichever is faster, and the memories 3 has data storage capacities greater than an amount of the data to be written into the memory 5 in each write period, and the memories 7 has data storage capacities greater than an amount of the data to be read from the memory 5 in each read period.

Abstract: A method for synthesizing a clock signal with multiple frequency outputs for use in a converter for converting a non-interlacing scan data into an interlacing scan data is disclosed. The converter provides a first reference clock signal with a frequency F1. The method includes the steps of receiving the first reference clock signal with the frequency F1 to generate and output a clock signal with a frequency F1×N, proceeding a divided-by-P1 and a divided-by-P2 operations on the clock signal with a frequency F1×N, respectively, to output a first output clock signal with a frequency F1×N/P1 and a second output clock signal with a frequency F1×N/P2, respectively. The value P2/P1 correlates to a ratio of the pixel number of a horizontal scan line in the non-interlacing scan data to that in the interlacing scan data. In addition, a clock signal synthesizer with multiple frequency outputs is also disclosed.

Abstract: Writing of a second field is started at a time point when writing of a first field has been completed, while information written in the first field is held. Writing of a first field of the next frame is started at a time point when the writing of the second field has been completed, while information written in the second field is held. This driving method can attain high vertical resolution.

Abstract: A method of smoothly displaying field videos in an interlaced display according to the invention. In a currently-exiting interlaced display system, the sequence of a scan timing with a top scan timing, a bottom scan timing, a top scan timing, a bottom scan timing . . . , should be consistent to that of field number with a top field, a bottom field, a top field, a bottom field, . . . In the invention, a top or bottom field can be inserted/skipped right after any one field displayed. During inserting/skipping, a new top field which is created from the bottom field or a new bottom field which is created from the top field, is displayed at a corresponding scan timing, thereby efficiently preventing a TV screen from jitters, resulting in smooth display.

Abstract: The present invention relates to a method for regulating, in the read mode, memory areas of a circuit for decompressing a video data flow compressed according to an MPEG standard, with respect to the writing rate of the compressed data flow into the memory areas, the decompression circuit issuing a flow of image data at the rate of signals for horizontally and vertically synchronizing the images issued by a circuit for coding according to a color television standard, this method including generating a clock signal having a fixed frequency for reading from the memory areas and for generating the horizontal and vertical synchronization signals, and shifting the occurrence of an edge triggering the vertical synchronization signal based on a signal indicative of the state of a buffer memory associated with the memory areas.

Abstract: An image display device for arbitrarily switching a display area includes a drive signal supply device for supplying drive signals for pixels arranged in a matrix-like fashion, in response to the generation of predetermined signals, in signal lines of rows and columns corresponding to the pixels, and sequential signal output devices for sequentially outputting the predetermined signals from a signal line of a predetermined start row or column to the signal lines of rows or columns at least with respect to either the rows or columns. The sequential signal output devices are equipped with a switching device for switching the start row or column.

Abstract: The field-display means of a conventional television set are used, to which the odd lines of a VGA image are transmitted during one field and the even lines during the next field, thereby providing for the use of a television set as a computer monitor.

Abstract: A system and method for optically, serially transmitting data to a remote device using an interlaced display device. The data bits to be transmitted are ordered so that the bits are received in proper temporal order by the remote device. At least one of the data bits can be transmitted using the even-numbered horizontal scan lines of the interlaced display device. If all of the data bits can not be transmitted using the even-numbered horizontal scan lines of a usable transmission area, then at least one of the data bits can be transmitted using the odd-numbered horizontal scan lines of the interlaced display device. The binary data bits can be represented by illuminated and non-illuminated horizontal scan lines. An optical detector in the remote device can be used to receive the pulses of light, representing the data bits to be transmitted, from the horizontal scan lines.

Abstract: Writing of a second field is started at a time point when writing of a first field has been completed, while information written in the first field is held. Writing of a first field of the next frame is started at a time point when the writing of the second field has been completed, while information written in the second field is held. This driving method can attain high vertical resolution.

Abstract: A television receiver is provided which includes a vertical deflection circuit which causes interlacing of an interlaced video signal having two fields each with an integral number of scan lines. The vertical deflection circuit including a jog circuit coupled to a vertical deflection yoke, which jog circuit causes a change in current through the vertical deflection yoke during reception of one of the fields. This change in current causes the fields to interlace with each other when scanned on a picture tube.

Abstract: The invention inputs a single timing clock. Through procedure of mode setting, the invention generates the required timings corresponding to the display mode selected. In the invention, a programmable mode register, a mode decoder, a pixel timing generator, a horizontal timing generator, a vertical timing generator, a composite timing generator, AND gate, EXCLUSIVE NOR gate, and a selector are provided. The invention may generate the required timings for NTSC interlace mode, NTSC non-interlace mode, PAL interlace mode, PAL non-interlace mode, VGA 60 Hz progressive mode and VGA 50 Hz progressive mode.

Abstract: A method for controlling a liquid crystal display (LCD) module to show interlaced picture data thereon includes the step of providing a data field of the interlaced picture data, which data field includes a series of line picture data, to the LCD module. Twin line clock pulses are then provided to the LCD module to control latching of each line picture data thereby. Finally, a frame start pulse is provided to the LCD module whenever a first one of the line picture data is provided to the LCD module. The width of the frame start pulse is varied so that the LCD module can show the first one of the line picture data on a first even line thereof when the data field is an even data field and on a first odd line thereof when the data field is an odd data field. The twin line clock pulses and the frame start pulse ensure that the line picture data of the even and odd data fields are shown alternately and respectively on even and odd lines of the LCD module.