Amorphous (electrical) Patents (Class 365/163)
  • Patent number: 11915752
    Abstract: A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Der Chih, Chung-Cheng Chou, Chun-Yun Wu, Chen-Ming Hung
  • Patent number: 11892928
    Abstract: Aspects of a storage device are provided which delay thermal throttling in response to temperature increases based on different reliable temperatures for different types of cells, such as SLCs, hybrid SLCs and MLCs. Initially, a controller writes first data to a block of MLCs at a first data rate when a temperature of the block meets a first temperature threshold for MLCs. Subsequently, the controller writes second data to the block at a second data rate lower than the first data rate when the temperature of the block meets a second temperature threshold for SLCs. For hybrid SLCs, the MLCs are each configured to store a first number of bits, and the controller writes a second number of bits smaller than the first number of bits in each of one or more of the cells. Storage device performance is thus improved through delayed thermal throttling without compromising data integrity.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: February 6, 2024
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Vinayak Bhat
  • Patent number: 11895851
    Abstract: Methods, systems, and devices for cross point array architecture for multiple decks are described. A memory array may include multiple decks, such as six or eight decks. The memory array may also include sockets for coupling access lines with associated decoders. The sockets may be included in sub-blocks of the array. A sub-block may be configured to include sockets for multiple access lines. A socket may intersect an access line in the middle of the access line, or at an end of the access line. Sub-blocks containing sockets for an access line may be separated by a period based on the access line.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Pirovano, Lorenzo Fratin
  • Patent number: 11889773
    Abstract: A phase change memory (PCM) cell comprises a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, a first phase change layer positioned between the first electrode and the second electrode and being comprised of a first phase change material, and a second phase change layer positioned between the first electrode and the second electrode and being comprised of a second phase change material. The first phase change material has a first resistivity, the second phase change material has a second resistivity, and wherein the first resistivity is at least two times the second resistivity.
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: January 30, 2024
    Assignee: International Business Machines Corporation
    Inventors: Kevin W. Brew, Injo Ok, Jin Ping Han, Timothy Mathew Philip, Matthew Joseph BrightSky, Nicole Saulnier
  • Patent number: 11887661
    Abstract: Methods, systems, and devices for a cross-point pillar architecture for memory arrays are described. Multiple selector devices may be configured to access or activate a pillar within a memory array, where the selector devices may each be or include a chalcogenide material. A pillar access line may be coupled with multiple selector devices, where each selector device may correspond to a pillar associated with the pillar access line. Pillar access lines on top and bottom of the pillars of the memory array may be aligned in a square or rectangle formation, or in a hexagonal formation. Pillars and corresponding selector devices on top and bottom of the pillars may be located at overlapping portions of the pillar access lines, thereby forming a cross point architecture for pillar selection or activation. The selector devices may act in pairs to select or activate a pillar upon application of a respective selection voltage.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: January 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Innocenzo Tortorelli, Fabio Pellizzer, Mattia Robustelli, Alessandro Sebastiani
  • Patent number: 11875847
    Abstract: Memory devices such as phase change memory (PCM) devices utilizing Ovonic Threshold Switching (OTS) selectors may be used to fill the gap between dynamic random-access memory (DRAM) and mass storage and may be incorporated in high-end microcontrollers. Since the programming efficiency and reading phase efficiency of such devices is directly linked to the leakage current of the OTS selector as well as sneak-path management, a sense amplifier disclosed herein generates an auto-reference that takes into account the leakage currents of unselected cells and includes a regulation loop to compensate for voltage drop due to read current sensing. This auto-referenced sense amplifier, built utilizing the principle of charge-sharing, may be designed on a 28 nm fully depleted silicon-on-insulator (FDSOI) technology, provides robust performance for a wide range of sneak-path currents and consequently for a large range of memory array sizes, and is therefore suitable for use in embedded memory in high-end microcontroller.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: January 16, 2024
    Assignees: Universite D'Aix Marseille, Centre National De La Recherche Scientifique, STMicroelectro (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Jean-Michel Portal, Vincenzo Della Marca, Jean-Pierre Walder, Julien Gasquez, Philippe Boivin
  • Patent number: 11877457
    Abstract: The present disclosure provides a memory device and accessing/de-selecting methods thereof. The memory device comprises a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein a memory cell is accessed through a word line and a digit line orthogonal to each other, and the digit line is in a form of conductive pillar extending vertically; a pillar selection layer formed under the memory layer and having thin film transistors (TFTs) formed therein for accessing memory cells; and a peripheral circuit layer formed under the pillar selection layer and having a sense amplifier and a decoding circuitry for word lines and bit lines, wherein a TFT is configured for each pillar.
    Type: Grant
    Filed: May 25, 2020
    Date of Patent: January 16, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Fantini, Corrado Villa, Stefan Frederik Schippers, Efrem Bolandrina
  • Patent number: 11862293
    Abstract: A semiconductor memory device includes memory cell arrays including a first memory cell and a first word line connected to the first memory cell, a first wiring electrically connected to the first word lines corresponding to the memory cell arrays, a driver circuit electrically connected to the first wiring, second wirings electrically connected to the first wiring via the driver circuit, a voltage generation circuit including output terminals disposed corresponding to the second wirings, and first circuits disposed corresponding to the memory cell arrays. The voltage generation circuit is electrically connected to the first word lines via a first current path including the second wirings, the driver circuit, and the first wiring. The voltage generation circuit is electrically connected to the first word lines via a second current path including the second wirings and the first circuits and without including the driver circuit.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: January 2, 2024
    Assignee: KIOXIA CORPORATION
    Inventor: Noriyasu Kumazaki
  • Patent number: 11854615
    Abstract: Methods, a memory device, and a system are disclosed to reduce power consumption in a cross-point memory device, including providing a first portion of a first pulse of a memory operation to a memory cell at a first time using a first capacitive discharge from a first discharge path, and providing a second portion of the first pulse of the memory operation to the memory cell at a second time, later than the first time, using a second discharge path.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: December 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Jeremy M. Hirst, Eric S. Carman
  • Patent number: 11848049
    Abstract: A phase-change memory device and a dynamic resistance drift compensation method thereof are provided. The phase-change memory device includes a plurality of bit lines; a plurality of source lines crossing the plurality of bit lines; a plurality of memory cells at respective intersections between the plurality of bit lines and the plurality of source lines, the plurality of memory cells each including a phase-change layer; a current generator connected to the plurality of bit lines and configured to generate a set current to be supplied to each of the plurality of memory cells; and a control driver configured to control the current generator and the plurality of bit lines to supply the set current to each of the plurality of memory cells.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: December 19, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yunheub Song, Yoonseong Choi
  • Patent number: 11849655
    Abstract: A semiconductor device includes a memory structure over a substrate, wherein the memory structure includes a first word line; a first bit line over the first word line; a second bit line over the first bit line; a memory material over sidewalls of the first bit line and the second bit line; a first control word line along a first side of the memory material, wherein the first control word line is electrically connected to the first word line; a second control word line along a second side of the memory material that is opposite the first side; and a second word line over the second bit line, the first control word line, and the second control word line, wherein the second word line is electrically connected to the second control word line.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Shao-Ming Yu, Kai-Tai Chang
  • Patent number: 11817171
    Abstract: The present disclosure generally relates to circuit architectures for programming and accessing resistive change elements. The circuit architectures can program and access resistive change elements using neutral voltage conditions. The present disclosure also relates to methods for programming and accessing resistive change elements using neutral voltage conditions. The present disclosure additionally relates to sense amplifiers configurable into initializing configurations for initializing the sense amplifiers and comparing configurations for comparing voltages received by the sense amplifiers. The sense amplifiers can be included in the circuit architectures of the present disclosure.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: November 14, 2023
    Assignee: Nantero, Inc.
    Inventors: Takao Akaogi, Jia Luo, Nancy See Loiu Leong
  • Patent number: 11810617
    Abstract: Examples may include techniques to implement a SET write operation to a selected memory cell include in a memory array. Examples include selecting the memory cell that includes phase change material and applying various currents over various periods of time during a nucleation stage and a crystal growth stage to cause the memory cell to be in a SET logical state.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: November 7, 2023
    Assignee: Intel Corporation
    Inventors: Hemant P. Rao, Shylesh Umapathy, Sanjay Rangan
  • Patent number: 11800816
    Abstract: Methods and devices based on the use of dopant-modulated etching are described. During fabrication, a memory storage element of a memory cell may be non-uniformly doped with a dopant that affects a subsequent etching rate of the memory storage element. After etching, the memory storage element may have an asymmetric geometry or taper profile corresponding to the non-uniform doping concentration. A multi-deck memory device may also be formed using dopant-modulated etching. Memory storage elements on different memory decks may have different taper profiles and different doping gradients.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: October 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Innocenzo Tortorelli, Mattia Robustelli
  • Patent number: 11769551
    Abstract: Methods, systems, and devices related to a multi-level self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more durations during which a fixed level of voltage or fixed level of current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: September 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Redaelli, Innocenzo Tortorelli, Agostino Pirovano, Fabio Pellizzer
  • Patent number: 11765916
    Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: September 19, 2023
    Assignee: Kioxia Corporation
    Inventors: Takahiko Iizuka, Daisaburo Takashima, Ryu Ogiwara, Rieko Funatsuki, Yoshiki Kamata, Misako Morota, Yoshiaki Asao, Yukihiro Nomura
  • Patent number: 11763886
    Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Innocenzo Tortorelli, Andrea Redaelli, Agostino Pirovano, Fabio Pellizzer, Mario Allegra, Paolo Fantini
  • Patent number: 11756616
    Abstract: A computer includes: a memristor array including memristors arranged at intersections between word lines and a first bit line in the memristor array and at intersections between the word lines and second bit lines in the memristor array; an adder circuit configured to obtain sum voltages for the second bit lines by adding first voltages generated according to currents that flow in the second bit lines when a first pattern is supplied to the word lines to difference voltages between a reference voltage generated according to a current that flows in the first bit line when a second pattern is supplied to the word lines and second voltages generated according to currents that flow in the second bit lines when a second pattern is supplied to the word lines; and a detection circuit that detects a second bit line that corresponds to a maximum value of the sum voltages.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: September 12, 2023
    Assignee: FUJITSU LIMITED
    Inventors: Hiroshi Nakao, Masayuki Hiromoto, Hisanao Akima, Teruo Ishihara, Takuji Yamamoto
  • Patent number: 11751379
    Abstract: A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: September 5, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Hoon Kim, Kwang-Ho Park, Yong-Hoon Son, Hyunji Song, Gyeonghee Lee, Seungjae Jung
  • Patent number: 11751487
    Abstract: A semiconductor device includes a storage element layer and a selector. The selector is electrically coupled to the storage element layer, and includes a first insulating layer, a second insulating layer, a third insulating layer, a first conductive layer and a second conductive layer. The first insulating layer, the second insulating layer and the third insulating layer are stacked up in sequence, wherein the second insulating layer is sandwiched in between the first insulating layer and the third insulating layer, and the first insulating layer and the third insulating layer include materials with higher band gap as compared with a material of the second insulating layer. The first conductive layer is connected to the first insulting layer, and the second conductive layer is connected to the third insulating layer.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Georgios Vellianitis, Gerben Doornbos, Marcus Johannes Henricus Van Dal, Mauricio Manfrini
  • Patent number: 11742021
    Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: August 29, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Hiroki Noguchi, Yu-Der Chih, Yih Wang
  • Patent number: 11744165
    Abstract: Memory devices and methods of forming the same are provided. A memory device includes a substrate, a first conductive layer, a phase change layer, a selector layer and a second conductive layer. The first conductive layer is disposed over the substrate. The phase change layer is disposed over the first conductive layer. The selector layer is disposed between the phase change layer and the first conductive layer. The second conductive layer is disposed over the phase change layer. In some embodiments, at least one of the phase change layer and the selector layer has a narrow-middle profile.
    Type: Grant
    Filed: April 17, 2022
    Date of Patent: August 29, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chao-I Wu
  • Patent number: 11735260
    Abstract: A semiconductor memory device capable of satisfying multiple reliability conditions and multiple performance requirements is provided. A variable resistance memory of the disclosure makes it possible to write data in a memory array by changing a write condition according to the type of a write command from the outside. If the write command is an endurance-related command, an endurance algorithm is selected and data is written in an endurance storage area. If the write command is a retention-related command, a retention algorithm is selected and data is written in a retention storage area.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: August 22, 2023
    Assignee: Winbond Electronics Corp.
    Inventor: Yasuhiro Tomita
  • Patent number: 11726690
    Abstract: A memory device includes a memory array comprising a first number of planes, a second number of independent plane driver circuits, wherein the second number is less than the first number, and a plane selection circuit to couple the second number of independent plane driver circuits to the first number of planes of the memory array. The memory device further includes control logic, to perform receive a first read command and identify, among the first number of planes, a first plane to which the first read command is directed. The control logic further configures the plane selection circuit to couple a first independent plane driver of the second number of independent plane drivers to the first plane and causes the first independent plane driver to perform a first read operation corresponding to the first read command on the first plane.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: August 15, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Theodore T. Pekny
  • Patent number: 11723293
    Abstract: Aspects of the present invention provide a semiconductor structure for a phase change memory device that includes a heater element on a bottom electrode that is surrounded by a dielectric material. The phase change memory device includes a metal nitride liner over the heater element, where the metal liner is oxide-free with a desired electrical resistance. The phase change memory device includes a phase change material is over the heater element and the dielectric material and a top electrode is over the phase change material.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: August 8, 2023
    Assignee: International Business Machines Corporation
    Inventors: Robert L. Bruce, Cheng-Wei Cheng, Matthew Joseph BrightSky
  • Patent number: 11715517
    Abstract: A phase change (PCM) memory device that includes a PCM and a resistance-capacitance (RC) circuit. The PCM has one or more PCM properties, each PCM property has a plurality of PCM property states. As the PCM property states of a given property are Set or Reset, the PCM property states each produce an incremental change to a property level of the respective/associated PCM property, e.g., PCM conductance. The incremental changes to property level of the PCM memory device are in response to application of one or more of a pulse number of voltage pulses. The RC circuit produces a configuring current that flows through the PCM in response to one or more of the voltage pulses. The configuring current modifies one or more of the incremental changes to one or more of the property levels so that the property level changes lineally with respect to the pulse number. The PCM memory device has use in a synapse connector, e.g., in a memory array.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: August 1, 2023
    Assignee: International Business Machines Corporation
    Inventors: Ning Li, Wanki Kim, Devendra K Sadana
  • Patent number: 11710519
    Abstract: A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: July 25, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Teng-Hao Yeh, Hang-Ting Lue, Cheng-Lin Sung, Yung-Feng Lin
  • Patent number: 11711926
    Abstract: A memory array and structure are provided. The array includes driving elements arranged in array; memory cells arranged in array and respectively corresponding to the driving elements, where one end of each memory cell is coupled to a first end of the corresponding driving element; word lines and bit lines arranged to intersect with each other, where each word lines is coupled to control ends of the driving elements in the same word line, and each bit line is respectively coupled to the other ends of the memory cells. For each word line, the first end of one driving element is connected to the first end of at least one other driving element in the same word line by a metal line, so as to form share driving elements.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: July 25, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hsin-Yi Ho
  • Patent number: 11705199
    Abstract: The present disclosure includes apparatuses and methods for programming memory cells using asymmetric current pulses. An embodiment includes a memory having a plurality of self-selecting memory cells, and circuitry configured to program a self-selecting memory cell of the memory by applying a first current pulse or a second current pulse to the self-selecting memory cell, wherein the first current pulse is applied for a longer amount of time than the second current pulse and the first current pulse has a lower amplitude than the second current pulse.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: July 18, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Mattia Robustelli, Innocenzo Tortorelli, Richard K. Dodge
  • Patent number: 11705196
    Abstract: Aspects of the present disclosure provide a method for calibrating crossbar-based apparatuses. The method includes obtaining output data of a crossbar-based apparatus may include a plurality of cross-point devices with tunable conductance, where the output data of the crossbar-based apparatus represents computing results of at least one operation performed by the crossbar-based apparatus, and where the output data corresponding to a plurality of settings of a plurality of analog components of the crossbar-based apparatus. The method also includes obtaining, by a processing device, one or more calibration parameters based on the output data of the crossbar-based apparatus, where the one or more calibration parameters correspond to one or more errors associated with one or more of the analog components of the crossbar-based apparatus. The method further includes calibrating the crossbar-based apparatus using the one or more calibration parameters.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: July 18, 2023
    Assignee: TetraMem Inc.
    Inventors: Miao Hu, Ning Ge
  • Patent number: 11699479
    Abstract: A nonvolatile memory apparatus may include a control circuit, a sense amplifier, and a reference generator. The control circuit may apply a read voltage across a target memory cell through a selected global bit line and a selected global word line. The sense amplifier may generate an output signal by comparing voltage levels of the selected global word line and a reference line. The reference generator may change the voltage level of the reference line by charging and discharging a capacitor that is coupled to the reference line.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: July 11, 2023
    Assignee: SK hynix Inc.
    Inventor: Moo Hui Park
  • Patent number: 11688460
    Abstract: As described, an apparatus may include a memory cell corresponding to a memory address and an access line forming at least a portion of the memory cell. The apparatus may include a first decoder associated with a first delivery driver coupled to a first end of the access line and a second decoder associated with a second delivery driver coupled to another end of the access line.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: June 27, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Nevil N. Gajera, John Frederic Schreck
  • Patent number: 11665985
    Abstract: A memory device enabling a reduced minimal conductance state may be provided. The device comprises a first electrode, a second electrode and phase-change material between the first electrode and the second electrode, wherein the phase-change material enables a plurality of conductivity states depending on the ratio between a crystalline and an amorphous phase of the phase-change material. The memory device comprises additionally a projection layer portion in a region between the first electrode and the second electrode. Thereby, an area directly covered by the phase-change material in the amorphous phase in a reset state of the memory device is larger than an area of the projection layer portion oriented to the phase-change material, such that a discontinuity in the conductance states of the memory device is created and a reduced minimal conductance state of the memory device in a reset state is enabled.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: May 30, 2023
    Assignee: International Business Machines Corporation
    Inventors: Benedikt Kersting, Ghazi Sarwat Syed, Vara Sudananda Prasad Jonnalagadda, Manuel Le Gallo-Bourdeau, Abu Sebastian, Timothy Mathew Philip
  • Patent number: 11647684
    Abstract: In an approach for forming a nonvolatile tunable capacitor device, a first electrode layer is formed distally opposed from a second electrode layer, the first electrode layer configured to make a first electrical connection and the second electrode layer configured to make a second electrical connection. A dielectric layer is posited between the first electrode layer and adjacent to the second electrode layer. A phase change material (PCM) layer is posited between the first electrode layer and the second electrode layer adjacent to the dielectric layer. An energizing component is provided to heat the PCM layer to change a phase of the PCM layer. The energizing component may include a heating element or electrical probe in direct contact with the PCM layer, that when energized is configured to apply heat to the PCM layer. The phase of the PCM layer is changeable between an amorphous phase and a crystalline phase.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: May 9, 2023
    Assignee: International Business Machines Corporation
    Inventors: Guy M. Cohen, Takashi Ando, Nanbo Gong, Yulong Li
  • Patent number: 11640838
    Abstract: A memory is provided that is configured to practice two different modes of read operation, such as both a normal read operation and a burst-mode read operation. In one example, the memory is a pseudo-dual-port memory. The memory may include an address comparator to perform a time-division multiplexing to first compare a read address to a stored address and then to compare a write address to the stored address.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: May 2, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Arun Babu Pallerla, Changho Jung, Chulmin Jung
  • Patent number: 11637145
    Abstract: Methods, systems, and devices for multi-component cell architectures for a memory device are described. A memory device may include self-selecting memory cells that include multiple self-selecting memory components (e.g., multiple layers or other segments of a self-selecting memory material, separated by electrodes). The multiple self-selecting memory components may be configured to collectively store one logic state based on the polarity of a programming pulse applied to the memory cell. The multiple memory component layers may be collectively (concurrently) programmed and read. The multiple self-selecting memory components may increase the size of a read window of the memory cell when compared to a memory cell with a single self-selecting memory component. The read window for the memory cell may correspond to the sum of the read windows of each self-selecting memory component.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: April 25, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Innocenzo Tortorelli
  • Patent number: 11631458
    Abstract: A memory device includes a cell area in which a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to the plurality of word lines and the plurality of bit lines are disposed, each of the plurality of memory cells including an Ovonic threshold switch element and a memory element connected to each other in series, and a peripheral circuit area including at least one peripheral circuit, configured to input a first refresh voltage turning on the Ovonic threshold switch element to each of at least some refresh cells among the plurality of memory cells to execute a refresh operation, determine each of the refresh cells as a first refresh cell in a first state or a second refresh cell in a second state while the Ovonic threshold switch element is turned on, and input a second refresh voltage, different to the first refresh voltage, to the second refresh cell.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: April 18, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sungkyu Jo
  • Patent number: 11631718
    Abstract: A vertical nonvolatile memory device including memory cell strings using a resistance change material is provided. Each of the memory cell strings of the nonvolatile memory device includes a semiconductor layer extending in a first direction; a plurality of gates and a plurality of insulators alternately arranged in the first direction; a gate insulating layer extending in the first direction between the plurality of gates and the semiconductor layer and between the plurality of insulators and the semiconductor layer; and a resistance change layer extending in the first direction on a surface of the semiconductor layer. The resistance change layer includes a metal-semiconductor oxide including a mixture of a semiconductor material of the semiconductor layer and a transition metal oxide.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: April 18, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinhong Kim, Seyun Kim, Youngjin Cho
  • Patent number: 11626161
    Abstract: A selection scheme for crosspoint memory is described. In one example, the selection voltage applied across the memory cell is slowly ramped up. Once the memory cell thresholds, the voltage is reduced to a level for performing the read or write operation. Reducing the voltage once the specific cell has been selected (e.g., thresholds) minimizes the additional transient current which might be generated by further increasing the selection bias applied during read or write operation. The reduction in transient current can lead to an improvement in read disturb and write endurance issues. The selection ramp-rate and bias post-selection can be set differently depending on the cell location inside the memory array to further improve cell performance.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: April 11, 2023
    Assignee: Intel Corporation
    Inventors: Davide Mantegazza, Kyung Jean Yoon, John Gorman, Dany-Sebastien Ly-Gagnon
  • Patent number: 11621394
    Abstract: A phase change memory (PCM) cell comprises a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, a first phase change layer positioned between the first electrode and the second electrode and being comprised of a first phase change material, and a second phase change layer positioned between the first electrode and the second electrode and being comprised of a second phase change material. The first phase change material has a first resistivity, the second phase change material has a second resistivity, and wherein the first resistivity is at least two times the second resistivity.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: April 4, 2023
    Assignee: International Business Machines Corporation
    Inventors: Kevin W. Brew, Injo Ok, Jin Ping Han, Timothy Mathew Philip, Matthew Joseph BrightSky, Nicole Saulnier
  • Patent number: 11615841
    Abstract: A memory device includes a plurality of memory cells, each including a switching device and an information storage device connected to the switching device and having a phase change material, the plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a decoder circuit determining at least one of the plurality of memory cells to be a selected memory cell, and a program circuit configured to input a programming current to the selected memory cell to perform a programming operation and configured to detect a resistance of the selected memory cell to adjust a magnitude of the programming current.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: March 28, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bilal Ahmad Janjua, Jongryul Kim, Venkataramana Gangasani, Jungyu Lee
  • Patent number: 11609443
    Abstract: Disclosed in the present invention are a chalcogenide phase change material based all-optical switch and a manufacturing method therefor, relating to the field of optical communications. The all-optical switch comprises: stacked in sequence, a cover layer film, a chalcogenide phase change material film, an isolation layer film, a silicon photonic crystal, and a substrate. The silicon photonic crystal comprises a nano-porous structure such that the silicon photonic crystal has a Fano resonance effect. When the all-optical switch is used, the state of the chalcogenide phase change material film is controlled by means of laser, and the resonance state of the silicon photonic crystal is modulated to implement modulation of signal light transmissivity; the modulation range is within a communication band from 1500 nm to 1600 nm, thereby implementing an optical switch. The all-optical switch of the present invention has the characteristics of high contrast ratio, high rate and low loss.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: March 21, 2023
    Assignee: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Xiangshui Miao, Yitao Lu, Hao Tong, Yi Wang
  • Patent number: 11605418
    Abstract: The application relates to an architecture that allows for less precision of demarcation read voltages by combining two physical memory cells into a single logical bit. Reciprocal binary values may be written into the two memory cells that make up a memory pair. When activated using bias circuitry and address decoders the memory cell pair creates current paths having currents that may be compared to detect a differential signal. The application is also directed to writing and reading memory cell pairs.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: March 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Joseph Michael McCrate, Robert John Gleixner, Hari Giduturi, Ramin Ghodsi
  • Patent number: 11581041
    Abstract: A nonvolatile memory apparatus includes a memory cell array and a memory control circuit. The memory cell array includes a plurality of sub arrays each including a plurality of memory cells coupled to a plurality of bit lines. The memory control circuit sequentially couples thereto, based on a single read command signal, at least a single bit line disposed on the respective sub arrays to sequentially access a memory cell coupled to the at least single bit line.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: February 14, 2023
    Assignee: SK hynix Inc.
    Inventor: Min Chul Shin
  • Patent number: 11574956
    Abstract: A semiconductor device includes a substrate; first conductive lines extending in a first direction; second conductive lines extending in a second direction; memory cell structures between the first conductive lines and the second conductive lines; and dummy cell structures that are electrically isolated and between the first conductive lines and the second conductive lines. The memory cell structures include a data storage material pattern including a phase change material layer; and a selector material pattern overlapping the data storage material pattern in a vertical direction. The dummy cell structures include a dummy pattern including a phase change material layer. The phase change material layer of the dummy pattern includes a crystalline phase portion and an amorphous phase portion. At a cross section of the phase change material layer of the dummy pattern, an area of the crystalline phase portion is larger than an area of the amorphous phase portion.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: February 7, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jiho Park, Kwangmin Park, Wonjun Park, Jeonghee Park, Changyup Park, Hwasung Chae
  • Patent number: 11568952
    Abstract: Methods, systems, and devices for adjustable programming pulses for a multi-level cell are described. A memory device may modify a characteristic of a programming pulse for an intermediate logic state based on a metric of reliability of associated memory cells. The modified characteristic may increase a read window and reverse a movement of a shifted threshold voltage distribution (e.g., by moving the threshold voltage distribution farther from one or more other voltage distributions). The metric of reliability may be determined by performing test writes may be a quantity of cycles of use for the memory cells, a bit error rate, and/or a quantity of reads of the first state. The information associated with the modified second pulse may be stored in fuses or memory cells, or may be implemented by a memory device controller or circuitry of the memory device.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: January 31, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Xuan-Anh Tran, Nevil N. Gajera, Karthik Sarpatwari, Amitava Majumdar
  • Patent number: 11557342
    Abstract: A multi-level cell (MLC) one-selector-one-resistor (1S1R) three-dimensional (3D) cross-point memory system includes at least one MLC 1S1R structure including a stacked arrangement of a phase change memory (PCM) cell and a threshold switch selector. An electrically conductive bit line is in electrical communication with the OTS selector, and an electrically conductive word line is in electrical communication with the PCM cell. A controller is in electrical communication with the bit line and the word line. The controller is configured to select at least one voltage pulse from a group of different voltage pulses comprising a read pulse, a partial set pulse, a set pulse, a partial reset pulse, and a reset pulse, and configured to deliver the selected at least one voltage pulse to the at least one MLC 1S1R structure.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: January 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: Nanbo Gong, Wei-Chih Chien, Matthew Joseph BrightSky, Christopher P. Miller, Hsiang-Lan Lung
  • Patent number: 11557343
    Abstract: According to one embodiment, a method, computer system, and computer program product for increasing linearity of a weight update of a phase change memory (PCM) cell is provided. The present invention may include applying a RESET pulse to amorphize the phase change material of the PCM cell; responsive to applying the RESET pulse, applying an incubation pulse to the PCM cell; and applying a plurality of partial SET pulses to incrementally increase the conductance of the PCM cell.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: January 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: Fabio Carta, Matthew Joseph BrightSky, Wanki Kim, Maxence Bouvier, SangBum Kim
  • Patent number: 11545201
    Abstract: Various embodiments of the present application are directed towards a memory cell, an integrated chip comprising a memory cell, and a method of operating a memory device. In some embodiments, the memory cell comprises a data-storage element having a variable resistance and a unipolar selector electrically coupled in series with the data-storage element. The memory cell is configured to be written by a writing voltage with a single polarity applying across the data-storage element and the unipolar selector.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: January 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Sheng-Chih Lai
  • Patent number: 11538521
    Abstract: A method is disclosed that includes causing a first set of a plurality of voltage pulses to be applied to memory cells of a memory device, a voltage pulse of the first set of the voltage pulses placing the memory cells of the memory device at a voltage level associated with a defined voltage state. The method also includes determining a set of bit error rates associated with the memory cells of the memory device in view of a data mapping pattern for the memory cells of the memory device, wherein the data mapping pattern assigns a voltage level associated with a reset state to at least a portion of the memory cells of the memory device. The method further includes determining whether to apply one or more second sets of the voltage pulses to the memory cells of the memory device in view of a comparison between the set of bit error rates for the memory cells and a previously measured set of bit error rates for the memory cells.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: December 27, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Murong Lang, Tingjun Xie, Zhenming Zhou