Abstract: The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant.

Abstract: A column in a memory array includes one bit cell circuit in each row for storing information about the row. The bit cell circuits store data in a data node and a complement data node in a cross-coupled inverter circuit. Toggling the nodes in a cross-coupled inverter includes discharging a charged node in contention with a charge current provided in the cross-coupled inverter circuit. The column circuit includes a first voltage supply circuit to decouple the cross-coupled inverter circuits from a first voltage rail to cut off charging current in response to a column set signal in a column set operation. The cross-coupled inverters of the bit cell circuits in the column circuit are coupled to a first voltage supply line. The column set input controls the first voltage supply circuit to decouple the first voltage supply line from a first voltage rail.

Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.

Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

Abstract: A Resistive random access memory (ReRAM) comprising: an array (M1) of cells (Cij) each connected to a first supply line (SL) set at a first supply potential, each cell being provided with a resistive element (1, 2) and a selection transistor (Ms1, Ms2), a read circuit (400) associated with a given row of cells and comprising a sense amplifier (440) of the latch type connected to a second supply line (45) set at a second supply potential, the device further comprising: a circuit for controlling read operations configured to during a reading: apply to said first bit line (BL0) a potential equal to said first supply potential (GND, VDD) while isolating the first bit line (BL0) from said sense amplifier (440), then, couple the first bit line (BL0) to said sense amplifier (440).

Abstract: Embodiments of the present disclosure provide an apparatus including: a sense amplifier coupled to a memory array and having a set of output terminals, a latch coupled to a first output terminal of the sense amplifier, and a comparator coupled to the latch and a second output terminal of the sense amplifier.

Abstract: Methods, systems, and devices for memory clock management and estimation procedures are described. A host device may determine a quantity of clock cycles associated with a duration for accessing a memory cell of a memory array based on truncating a value of a first parameter associated with another duration for a clock to perform a clock cycle. The host device may estimate a value of a second parameter related to (e.g., inversely proportional) to the truncated value of the first parameter and related to (e.g., directly proportional) to a correction factor, and may adjust (e.g., truncate) a third parameter to determine the quantity of clock cycles. Additionally or alternatively, the host device may adjust (e.g., perform a ceiling operation on) the second parameter to determine the quantity of clock cycles. The host device may access the memory cell based on the quantity of clock cycles.

Abstract: Various implementations described herein are related to a device having memory architecture having multiple bitcell arrays. The device may include column multiplexer circuitry coupled to the memory architecture via multiple bitlines for read access operations. The column multiplexer circuitry may perform read access operations in the multiple bitcell arrays via the bitlines based on a sense amplifier enable signal and a read multiplexer signal. The device may include control circuitry that provides the read multiplexer signal to the column multiplexer circuitry based on a clock signal and the sense amplifier enable signal so that the column multiplexer circuitry is able to perform the read access operations.

Abstract: A search pattern is generated based on an input search word comprising a first sequence of bits. The search pattern comprises a first set of signals representing the input search word and a second set of signals representing a second sequence of bits comprising an inverse of the first sequence of bits. The search pattern is provided as input to search lines of a content addressable memory (CAM) block. The search pattern causes at least one string in the CAM block to be conductive and provide a signal to a page buffer connected to the string in response to the input search word matching a data entry stored on the string. A location of the data entry is determined based on data read from the page buffer and the location is output.

Abstract: A memory device includes a memory array and a memory controller. The memory array includes a first memory bank, a second memory bank, and a third memory bank. The first memory bank includes a first sub memory bank. The second memory bank includes a second sub memory bank. The memory controller, according to a write command from a host, writes first data from the host to the first memory bank and second data to the second memory bank at the same time, and writes a first Hamming weight of the first data to the third memory bank. The second data is the inverse of the first data.

Abstract: A four-input lookup table (“LUT4”) is modified to operate in a first mode as an ordinary LUT4 and in a second mode as a 1-bit adder providing a sum output and a carry output. A six-input lookup table (“LUT6”) is modified to operate in a first mode as an ordinary LUT6 with a single output and in a second mode as a 2-bit adder providing a sum output and a carry output. Both possible results for the two different possible carry inputs can be determined and selected between when the carry input is available, implementing a 2-bit carry-select adder when in the second mode and retaining the ability to operate as an ordinary LUT6 in the first mode. Using the novel LUT6 design in a circuit chip fabric allows a 2-bit adder slice to be built that efficiently makes use of the LUT6 without requiring additional logic blocks.

Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.

Abstract: A data storage method, apparatus, and device, and a readable storage medium. The method includes: after a random access memory is powered on, obtaining target data to be stored in a fixed storage address of the random access memory; determining a target transmission mode from a bit value change transmission mode and a bit value fixed transmission mode, wherein the target transmission mode is different from a historical transmission mode determined after the random access memory is powered on last time; and transmitting the target data from and to the random access memory according to the target transmission mode. The method can prevent data from being stolen after power-down of the target data, and guarantees the data security.

Abstract: A word line control method, a word line control circuit device, and a semiconductor memory are provided. The method includes: acquiring a row address input signal; acquiring a test mode signal; performing logical and decoding operations on the row address input signal and the test mode signal to generate a row address control signal, wherein the row address control signal includes at least two valid activation signals; and simultaneously activating at least two non-adjacent word lines based on the at least two valid activation signals. The row address control signal obtained allows simultaneous activation of at least two non-adjacent word lines. Since none of any two non-adjacent word lines share a common contact area, a test will not be affected by the disconnection of a contact area or the presence of high impedance, thus improving test accuracy.

Abstract: Embodiments of the present disclosure utilizes the natural properties of RFI noise on a wireline link. Since differential RFI noise in the system has some correlation with the common mode noise on the cable, a replica of RFI noise can be regenerated by an adaptive filter based on information about the common mode noise. The replica RFI is subtracted from the equalizer output prior to the data decision circuitry or slicer. In this method, the system does not require expensive cable, nor does the equalizer suffer additional loss due to an RFI notch filter. Since RFI can be detected and mitigated, this information can also be coupled to safety systems to increase functional safety under high EMI conditions.

Abstract: According to an embodiment, a synapse circuit includes: a buffer that changes an output signal to a second logical value at a timing when an input signal exceeds a first threshold level, in a case where the output signal has a first logical value in a first mode, and changes the output signal to the second logical value at a timing when the input signal exceeds a reference level lower than the first threshold level, in a case where the output signal has the first logical value in a second mode; an adjusting unit that adjusts the first threshold level depending on a stored coefficient; and a mode switching unit that operates the buffer in the first mode during a period in which an acquired spike is not generated, and operates the buffer in the second mode during a period in which the spike is generated.

Abstract: A memory device includes a path state check circuit configured to check states of signal transmission paths, each signal transmission path including a data transmission path and a clock transmission path of the memory device. The path state check circuit includes a sampling circuit configured to perform a sampling operation by using pattern data that has passed through the data transmission path and a clock signal that has passed through the clock transmission path, and generate sample data, and a management circuit configured to generate a comparison of the sample data with the pattern data and manage check result information indicating whether a re-training operation for the memory device is to be performed, based on a result of the comparison.

Abstract: A memory device includes a data storage circuit configured to access a cell array having first data stored therein when an arithmetic active operation is performed, output the first data when a first read operation is performed, access a cell array having second data stored therein when an active operation is performed, and output the second data when a second read operation is performed. The memory device also includes an arithmetic circuit configured to receive latch data generated through the first read operation and read data generated through the second read operation, and perform an arithmetic operation on the latch data and the read data.

Abstract: The invention relates to a method for operating a self-propelled motor vehicle having a plurality of control units and a plurality of program codes for controlling the function of autonomous driving and possibly other functions of the self-propelled vehicle, wherein a plurality of program codes used for an autonomous driving mode are redundantly applied to at least two different control units. In doing so, the self-propelled motor vehicle is operated in an at least partially autonomous driving mode. In this mode, the functions directly needed to satisfy the passenger's wishes are ascertained and weighted corresponding to their relevance for satisfying the passenger's wishes. In so doing, the functions, or the scope of functions, are released depending on the achievement of a target achievement level.

Abstract: A processing system includes a content addressable memory (CAM) in an input/output path to selectively modify register writes on a per-pipeline basis. The CAM compares an address of a register write to an address field of each entry of the CAM. If a match is found, the CAM modifies the register write data as defined by a function for the matching entry of the CAM. In some embodiments, each entry of the CAM includes a data mask defining subfields of the register write data, wherein each subfield includes subfield data including one or more bits.

Abstract: According to one implementation of the present disclosure, an integrated circuit comprises a memory macro unit that includes an input/output (I/O) circuit block, where read/write circuitry of the I/O circuit block is apportioned on at least first and second tiers of the memory macro unit. In a particular implementation, read circuitry of the read/write circuitry is arranged on the first tier and write circuitry of the read/write circuitry is arranged on the second tier.

Abstract: Some embodiments include an integrated assembly having a memory region with memory cells and sense/access lines configured for addressing the memory cells, and having a reference-voltage-generator proximate to the memory region. The reference-voltage-generator includes resistive units configured substantially identically to the sense/access lines. Some embodiments include an integrated assembly having a memory region with memory cells, digit lines and wordlines. Each of the memory cells is uniquely addressed with one of the wordlines in combination with one of the digit lines. The wordlines are coupled with driver circuitry and the digit lines are coupled with sensing circuitry. A reference-voltage-generator is proximate to the memory region. The reference-voltage-generator includes resistive units configured substantially identically to the wordlines and/or includes resistive units configured substantially identically to the digit lines.

Abstract: Bit line equalization driver circuits and related apparatuses, methods, and computing systems are disclosed. An apparatus includes an output inverter including a pull-up transistor and a pull-down transistor electrically connected in series between a pull-up node and a pull-down node. An output node is electrically connected between the pull-up transistor and the pull-down transistor. The pull-down transistor includes a short length transistor having a degradation voltage potential across the pull-down transistor below which the pull-down transistor is configured to operate to avoid degradation of the pull-down transistor. The apparatus also includes biasing circuitry configured to control voltage potentials at the pull-up node and the pull-down node to enable the output inverter to assert, at the output node, an output voltage potential that is greater than the degradation voltage potential higher than a low power supply voltage potential at the low power supply node.

Abstract: A memory device includes a plurality of memory banks and a sensing delay circuit. Each of the memory banks is activated by a row active command and is configured to perform a sensing operation based on a sensing enable signal. The sensing delay circuit, that includes a shared delay circuit and a delay path control circuitry, may delay a start of the sensing enable signal by a sensing delay period from an assertion of the row active command. The shared delay circuit is shared to the memory banks and may generate a plurality of delay signals based on the assertion of the row active command. The delay path control circuitry configured to control an electrical path between the shared delay circuit and the memory banks based on the row active command and the plurality of delay signals to output the sensing enable signal to the memory bank.

Abstract: A redundant array of independent disks (RAID) management method includes, when detecting that a component in a storage medium fails, recovering, based on a RAID policy, data stored in the failed component, saving the recovered data into a pre-defined redundant space of the RAID, and mapping an address of the failed component with the address of the redundant space, converting, according to the mapping, an address of to-be-accessed data comprised in an accessing request into an address within the redundant space, and accessing the to-be-accessed data from the redundant space according to the address within the redundant space.

Abstract: A memory system includes a non-volatile memory and a controller that includes a toggle encoder configured to encode first data having a first bit length and a first number of toggles, into second data having a second bit length longer than the first bit length and a second number of toggles smaller than the first number of toggles, and transmit the second data to the non-volatile memory. The memory system may further include a toggle decoder configured to decode third data received from the non-volatile memory into fourth data, the third data having the second bit length and the second number of toggles and the fourth data having the first bit length and the first number of toggles.

Abstract: Executable code is part of an over-the-air (OTA) update received by, for example, a computing device in a vehicle. In one example, the update is a secure over-the-air (SOTA) update of software that is stored in firmware of a vehicle component (e.g., firmware stored in memory of a storage device or a boot device that are mounted in a vehicle).

Abstract: An integrated circuit die element comprises one or more field-programmable gate arrays (FPGAs) elements; a reconfigurable dual function memory array, the reconfigurable dual function memory array including a plurality of reconfigurable memory array blocks, each reconfigurable memory array block being capable of configuration and reconfiguration as a storage memory array block or as a control logic array block for controlling at least a portion of the one or more FPGA elements; and a control logic circuit functioning to configure each reconfigurable memory array block as the respective memory array block or as the respective logic array block for controlling the one or more FPGA elements.

Abstract: Systems, methods, and apparatus to transition a display device between operating modes using a single dedicated pin of a circuit connected to the display device. The dedicated pin can receive a packet signal corresponding to an operating mode for the display device, and the circuit can thereafter cause the display device to transition into the desired operating mode in response to receiving the packet signal. The operating mode can be a low power on mode where an interface connected to the circuit is deactivated and at least some circuitry of the display device is throttled or powered off. The display device can be driven in an all black state while in the low power on mode, thereby allowing the display device to more quickly transition out of the low power on mode compared to when the display device is completely off.

Abstract: A device includes a circuit cell, a first switching unit, and a second switching unit. The first switching unit is configured to output an auxiliary signal. The second switching unit is coupled between the first switching unit and the circuit cell, and configured to transmit a write voltage and an auxiliary signal to the circuit cell.

Abstract: An integrated circuit die element comprises one or more field-programmable gate arrays (FPGAs) elements; a reconfigurable dual function memory array, the reconfigurable dual function memory array including a plurality of reconfigurable memory array blocks, each reconfigurable memory array block being capable of configuration and reconfiguration as a storage memory array block or as a control logic array block for controlling at least a portion of the one or more FPGA elements; and a control logic circuit functioning to configure each reconfigurable memory array block as the respective memory array block or as the respective logic array block for controlling the one or more FPGA elements.

Abstract: An integrated circuit comprising a field programmable gate array (FPGA) including a plurality of logic tiles wherein each logic tile includes circuitry including (i) logic circuitry and (ii) an interconnect network including a plurality of multiplexers. The FPGA further includes a robust memory cell including: three or more storage elements that are more than one time programmable to store a data state, majority detection circuitry to detect a majority data state stored in the three or more storage elements; and an output, coupled to the majority detection circuitry, to output mode select data which is representative of the majority data state stored in the storage elements. The FPGA also includes mode/function select circuitry to configure a mode of operation of at least a portion of the circuitry in one or more of the plurality of logic tiles based on the mode select data.

Abstract: A control circuit configured to supply a control voltage to a control terminal (G) of a solid state solid state switching device of a solid state power controller. The control circuit comprises: a primary controller operative to supply a primary control voltage to the control terminal (G) of the solid state switching device; and an auxiliary circuit configured to supply an auxiliary control voltage to the control terminal (G) of the solid state switching device in case the primary controller falls into an inoperative condition.

Abstract: A memory-testing method is adapted in a memory circuit including a first block and a second block including a plurality of row addresses and column addresses. The memory-testing method includes: selecting one of the row addresses and one of the column addresses as a testing row and a testing column according to selection logic; selecting sampled column addresses of the testing row and sampled row addresses of the testing column according to a sampling process; executing the read operation on the sampled column addresses of the testing row and the sampled row addresses of the testing column in the first block; determining whether the read fail rate of the first block exceeds a predetermined ratio; and marking the first block as an input/output fail when the read fail rate exceeds the predetermined ratio.

Abstract: Word-line drivers, memories, and methods of operating word-line drivers are provided. A word-line driver coupled to an array of memory cells includes a decoder powered by a first power supply. The decoder is configured to decode an address to provide a plurality of word-line signals. The word-line driver also includes a plurality of output stages powered by a second power supply that is different than the first power supply. Each of the output stages includes a first transistor having a gate controlled by a first control signal and an inverter. The inverter is coupled between the first transistor and a ground and has an input coupled to the decoder to receive one of the word-line signals. The word-line driver also includes pull-down circuitry coupled between the gates of the first transistors and the ground and activated by a second control signal.

Abstract: Described is memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.

Abstract: Systems, apparatuses, and methods related to subrow addressing for electronic memory and/or storage are described. Independent subrow addressing may enable energy consumed by performance of an operation on a particular subset of data values stored by a row to more closely correspond to the size of the particular subset of data values relative to energy consumed by addressing and activating the complete row. For instance, one such apparatus includes a plurality of subrows within a row of memory cells and a controller configured to selectably address and manage an activation state of each subrow of the plurality of subrows. The apparatus further includes subrow driver circuitry coupled to the controller. The subrow driver circuitry is configured to maintain one or more subrows of the plurality in the activation state based at least in part on signaling from the controller.

Abstract: Some embodiments include an apparatus which has a wordline coupled with a transistor gate, and which has a compensator line extending along the wordline and spaced from the wordline by a dielectric region. A driver is coupled with the wordline, and a controller is coupled with the compensator line. The wordline is coupled with access transistors, and is operated at a first voltage while the access transistors are in an OFF state. The compensator line is operated at a second voltage while the wordline is at the first voltage; with the second voltage being greater than the first voltage. The wordline is operated at a third voltage while the access transistors are in an ON state, and the compensator line is operated at a fourth voltage while the wordline is at the third voltage. The third voltage may or may not be greater than the fourth voltage.

Abstract: Provided is memory device and a memory bank, comprising a global data bus, and a local data bus split into two parts, wherein the local data bus is configurable to direct signals to the global data bus. Provided also is a method in which signals are received in a local data bus that is split into two parts, and the signals are directed from the local data bus to the global data bus. Provided also is a computational device comprised of a processor and the memory device.

Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.

Abstract: A system and method is disclosed for an electronic device, such as a non-volatile memory associated with a host, to determine a current sourcing capability of the host and to adjust performance characteristics of the electronic device based on the determined current sourcing capability. The system may include an input current source testing circuit, device function circuitry and a controller configured to determine a current sourcing capability of a host with the input current source testing circuit, select a device performance parameter associated with the determined current sourcing capability and operate the device function circuitry according to the device performance parameter until detecting a power-off event. The method may include the electronic device reducing a resistance presented to the host to a plurality of predetermined resistance levels to determine the current sourcing capability of the host and utilizing the results of the determination to select associated device performance parameters.

Abstract: Various arrangements are presented for reducing channel change times. A first tuner of a television receiver may tune to a decryption key transponder stream. The decryption key transponder stream may include a plurality of decryption keys for a plurality of television channels that are transmitted to the television receiver via a plurality of transponder streams. A second tuner of the television receiver may be tuned to a media transponder stream to receive a television channel. Data obtained from the decryption key transponder stream may be used for decoding the television channel.

Abstract: A control device includes: a dummy memory cell group; a transistor having a first terminal, a grounded second terminal and a control terminal; an adjustor providing a resistance between the dummy memory cell group and the first terminal of the transistor; an inverter generating, based on a voltage at the first terminal of the transistor, a sense start signal that is associated with switching of a sense amplifier circuit of a semiconductor memory device from a disabled state to an enabled state; and a controller generating, based on the sense start signal, a control signal for controlling the transistor such that switching of the transistor from conduction into non-conduction is associated with the sense start signal.

Abstract: A semiconductor integrated circuit device includes a control unit which causes a column selection circuit to separate bit line pairs from a common bit line pair and causes a sense amplifier circuit to amplify a potential difference between the common bit line pair precharged by a precharge circuit, in response to a unique ID generation instruction.

Abstract: Provided is memory device and a memory bank, comprising a global data bus, and a local data bus split into two parts, wherein the local data bus is configurable to direct signals to the global data bus. Provided also is a method in which signals are received in a local data bus that is split into two parts, and the signals are directed from the local data bus to the global data bus. Provided also is a computational device comprised of a processor and the memory device.

Abstract: Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used. Described is a dual input level-shifter with integrated latch. Described is an apparatus which comprises: a write assist pulse generator operating on a first power supply; one or more pull-up devices coupled to the write assist pulse generator, the one or more pull-up devices operating on a second power supply different from the first power supply; and an output node to provide power supply to a memory cell.

Abstract: A method and system for suppressing power signature in a memory device during read operations. A memory array stores data in an even number of cells per bit, such as 2 cells per bit, where complementary data states are stored in each pair of cells. Differential read out of the memory array via the bitlines suppresses power signature because the same power consumption occurs regardless of the data being accessed from the memory array. Data output buffers that provide complementary data to a downstream circuit system are reset to the same logic state prior to every read operation such that only one output buffer (in the complementary output buffer pair) is ever driven to the opposite logic state in each read cycle. Hence the power consumption remains the same regardless of the data states being read out from the memory array and provided by the output buffers.

Abstract: Multiple integrated circuits (ICs) die, from different wafers, can be picked-and-placed, front-side planarized using a vacuum applied to a planarizing disk, and attached to each other or a substrate. The streets between the IC die can be filled, and certain techniques or fixtures allow application of monolithic semiconductor wafer processing for interconnecting different die. High density I/O connections between different IC die can be obtained using structures and techniques for aligning vias to I/O structures, and programmably routing IC I/O lines to appropriate vias. Existing IC die can be retrofitted for such interconnection to other IC die, such as by using similar techniques or tools.

Abstract: There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.

Abstract: A system and method are provided for managing mobile user access to enterprise network resources from a wireless mobile device, such as a smart phone or mobile computer, with improved security and access control. Access rules determining accessible resources and associated permitted operations are determined based on membership of an authenticated user to each of one or more groups, each group being associated with a set of permitted accessible resources and operations. For each user, based on membership of a group, or a Boolean evaluation of memberships of two or more groups, a list of accessible resources and permitted operations is generated, and the list is made available for subsequent processes, e.g. presentation to the user on an interface of the mobile device. Access rules may also be defined dependent on other information received from the system, or from the mobile device, such as time or location.