Including Reference Or Bias Voltage Generator Patents (Class 365/189.09)
  • Patent number: 11908539
    Abstract: A voltage regulator for providing a word line voltage is provided. The voltage regulator includes a voltage divider, a comparator, a boost circuit and a bypass transistor. The voltage divider is coupled between the word line voltage and a low reference voltage. The voltage divider includes resistive elements connected in series at intermediate nodes. The comparator provides an enable signal according to a divided voltage value on a divided intermediate node among the intermediate nodes. The boost circuit boosts the word line voltage in response to the enable signal. A source terminal of the bypass transistor is connected to a first intermediate node among the intermediate nodes. A drain terminal of the bypass transistor is connected to a second intermediate node among the intermediate nodes. The bypass transistor is turned-off in response to the control signal having an intermediate voltage value on the first intermediate node.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: February 20, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Jen Chen
  • Patent number: 11894101
    Abstract: Sense amplifier, memory and control method are provided. The sense amplifier includes: amplify module configured to amplify voltage difference between bit line and reference bit line when the sense amplifier is in amplifying stage; write module connected to the bit line and the reference bit line, and configured to pull the voltage difference between the bit line and the reference bit line according to data to be written when the sense amplifier is in write stage; controllable power module connected to the amplify module, configured to provide first voltage to the amplify module when the sense amplifier is in non-write stage, and to provide second voltage to the amplify module when the sense amplifier in write stage. Herein, the second voltage is less than the first voltage, and the second voltage is in positive correlation with the drive capability of the write module.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: February 6, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Hsin-Cheng Su
  • Patent number: 11875867
    Abstract: A memory device can include multiple memory cells and a processing device operatively coupled with the memory device to perform operations including grouping the memory cells into a groups based on a metric reflecting an electrical distance of a memory cell from a voltage source, and determining, for each group, a respective share of write operations, wherein the share of write operations is related to an aggregate value of the metric for memory cells of the group. The operations can also include distributing the write operations to each group according to the share of write operations determined for the group.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: January 16, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Zhongyuan Lu, Karthik Sarpatwari, Nevil N. Gajera
  • Patent number: 11862075
    Abstract: The present disclosure relates to a drive circuit, including: a first module, generating display data based on image information; a second module, generating a display signal based on the display data and a plurality of clock signals; a third module, outputting a constant current based on the display signal; and a fourth module, configured to provide a reference current to the third module, wherein the fourth module includes: a reference voltage generation module, a bias module, a current generation module, and a pre-charging module. Any two adjacent clock signals of the plurality of clock signals differ by M complete clock cycles, where 0?M<1. This circuit can realize relatively high image display accuracy with relatively low system power consumption and chip cost, and meanwhile realize effective low grayscale compensation for image.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: January 2, 2024
    Assignee: CHENGDU LIPPXIN MICROELECTRONICS CO., LTD
    Inventors: Yongsheng Tang, Li Huang, Shixiong Lu
  • Patent number: 11862227
    Abstract: A driver circuit for operating a memory cell, adapted to be coupled to at least one memory cell through a respective output node, said driver circuit including: a first circuit for supplying the memory cell with a first read reference voltage through the output node; a second circuit for supplying the memory cell with a second read reference voltage through the output node; and a third circuit for controlling an operation of the second circuit, wherein a range of the second read reference voltage at the output node is wider than a range of the first read reference voltage at the output node during a read operation on the memory cell.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: January 2, 2024
    Assignee: SEMIBRAIN INC.
    Inventor: Seung-Hwan Song
  • Patent number: 11842759
    Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: December 12, 2023
    Assignee: Kioxia Corporation
    Inventors: Toshifumi Watanabe, Naofumi Abiko
  • Patent number: 11835978
    Abstract: Methods and devices to reduce or remove slumps in power supplies are disclosed. The disclosed teachings can serve various applications, such as applications implementing RF switches. Using such teachings, an integrated method can benefit from two different modes of operation where either an external or an internal charge pump can be used to provide a desired negative voltage to various components within the integrated circuit. This can be done by disposing a larger load capacitor outside the integrated circuit and without compromising any die space requirement.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: December 5, 2023
    Assignee: pSemi Corporation
    Inventors: Ravindranath D. Shrivastava, Payman Shanjani
  • Patent number: 11817175
    Abstract: A semiconductor apparatus includes a command decoding circuit and an enable signal generation circuit. The command decoding circuit generates an operation code and a strobe pulse based on a command signal and a clock signal. The enable signal generation circuit generates a seed signal based on the operation code and the strobe pulse and generates an enable signal by shifting the seed signal. The enable signal generation circuit generates a plurality of guard keys based on a plurality of operation codes and the strobe pulse and prevents the generation of the enable signal for a predetermined time when the plurality of guard keys are not sequentially enabled.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: November 14, 2023
    Assignee: SK hynix Inc.
    Inventors: Mino Kim, Hyeong Soo Jeong
  • Patent number: 11798636
    Abstract: Methods, systems, and devices for an improved power supply for a memory device are described. An apparatus may include a memory device, one or more voltage detectors, and one or more voltage converters. A voltage detector may generate an output indicating whether a voltage at a first pin of the apparatus satisfies a threshold. A voltage converter may be coupled with the voltage detector and may be configured to selectively output a second voltage depending on the output of the voltage detector. Circuitry within the memory device may be coupled with one or more voltage detectors and one or more voltage converters and configured to select a supply voltage for another component of the memory device from among the first voltage (e.g., received from the first pin) and the second voltage (e.g., selectively generated and output by the voltage converter) based on the output from the voltage detector.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: October 24, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Minjian Wu
  • Patent number: 11798637
    Abstract: Methods, systems, and devices for current budget adaption are described. A controller may be coupled with a set of memory devices. The controller may receive current consumption information from the set of memory devices and update a current consumption budget for the set of memory devices based on the current consumption information.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: October 24, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Giuseppe Cariello
  • Patent number: 11776644
    Abstract: A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: October 3, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Minho Choi, Jaeseong Lim, Kyungryun Kim, Daehyun Kim, Wonil Bae, Hohyun Shin, Sanghoon Jung, Hyongryol Hwang
  • Patent number: 11735264
    Abstract: A NAND flash memory according to an embodiment includes a memory array, a detection circuit, and a drive circuit. The drive circuit is a circuit for driving a plurality of linearly arranged memory cells through a linear word line connected to the plurality of memory cells. The drive circuit has a function of generating a drive voltage in which a pre-pulse having a predetermined amplitude value is set at a timing corresponding to rising of a voltage signal, which rises stepwise by a voltage value, and applying the drive voltage to the word line and a function of detecting a voltage value at a predetermined position of the word line and setting a time width of the pre-pulse according to the detected voltage value.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: August 22, 2023
    Inventors: Toru Tanzawa, Kazuki Matsuyama
  • Patent number: 11735253
    Abstract: Methods of operating a memory, and memory configured to perform similar methods, may include determining a memory cell age of a plurality of memory cells, determining a desired programming step voltage for programming memory cells having the determined memory cell age, and performing a programming operation on the plurality of memory cells using the desired programming step voltage corresponding to the determined memory cell age. Methods may further include configuring a memory, including characterizing a read window budget for a programming operation of the memory as a function of a programming step voltage for a plurality of memory cell ages.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: August 22, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Pin-Chou Chiang
  • Patent number: 11715540
    Abstract: The disclosure provides an anti-fuse device including an anti-fuse unit and a sensing circuit. The anti-fuse unit includes a first anti-fuse and a second anti-fuse serially connected between a first terminal of the anti-fuse unit and a second terminal of the anti-fuse unit. The sensing circuit is coupled to the first terminal and the second terminal of the anti-fuse unit for sensing a blown state of the anti-fuse unit.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: August 1, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wu-Der Yang
  • Patent number: 11687468
    Abstract: A memory system for storing data that includes providing a memory module having one or more memory devices and a voltage regulator for controlling voltage levels supplied to the one or more memory devices, wherein the voltage regulator has a first state that permits write and read operations with the one or more memory devices, and a second state where the voltage regulator prevents at least read operations with the one or more memory devices the system configured to store an encryption key in ROM on the voltage regulator; copy the encryption key value from the ROM to a voltage regulator register; set a voltage regulator encryption timer for a period of time; and transition the voltage regulator to the second state in response to the voltage regulator encryption timer expiring.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: June 27, 2023
    Assignee: International Business Machines Corporation
    Inventors: Brian J. Connolly, Kyu-hyoun Kim
  • Patent number: 11675505
    Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum voltage signal from among the multiple voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum voltage signal from among the multiple voltage signals to minimize power consumption.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: June 13, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hao Hsu, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Hung-Jen Liao, Jung-Ping Yang, Jonathan Tsung-Yung Chang, Wei Min Chan, Yen-Huei Chen, Yangsyu Lin, Chien-Chen Lin
  • Patent number: 11636901
    Abstract: A memory device includes a charge pump connected to a power supply voltage and including a plurality of stages to output an output voltage, a stage counter configured to output a count value that incrementally increases to a number of the stages, and a regulator configured to compare the output voltage with a reference output voltage of the charge pump that is generated using the incrementally increasing count value obtained by the stage counter, and to output a pump operation signal at a time when the reference output voltage becomes greater than or equal to the output voltage, wherein the charge pump operates in response to the pump operation signal.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: April 25, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bilal Ahmad Janjua, Sung Whan Seo
  • Patent number: 11626160
    Abstract: Technology for sensing non-volatile memory cells in which one or more sense nodes are charged to a sense voltage having a magnitude that improves sensing accuracy. One sense node may be charged to different sense voltages when sensing different memory cells at different times. Multiple sense nodes may be charged to a corresponding multiple different sense voltages when sensing different memory cells at the same time. The one or more sense nodes are allowed to discharge based on respective currents of memory cells for a pre-determined time while applying a reference voltage to the memory cells. The Vts of the selected memory cells are assessed based on respective voltages on the one or more of sense nodes after the pre-determined time. Different sensing voltages may be used based on bit line voltage, bit line resistance, distance of memory cells from the sense node, or other factors.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: April 11, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Huiwen Xu, Bo Lei, Jun Wan
  • Patent number: 11616068
    Abstract: Methods, systems, and devices for deck selection layouts in a memory device are described. In some implementations, a tile of a memory array may be associated with a level above a substrate, and may include a set of memory cells, a set of digit lines, and a set of word lines. Selection transistors associated with a tile of memory cells may be operable for coupling digit lines of the tile with circuitry outside the tile, and may be activated by various configurations of one or more access lines, where the various configurations may be implemented to trade off or otherwise support design and performance characteristics such as power consumption, layout complexity, operational complexity, and other characteristics. Such techniques may be implemented for other aspects of tile operations, including memory cell shunting or equalization, tile selection using transistors of a different level, or signal development, or various combinations thereof.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: March 28, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 11599185
    Abstract: Energy consumption is reduced within an Internet of Things (IoT) device, without degrading operating performance of the corresponding internal circuitry. A first internal supply voltage (VDDa) used to supply the internal circuitry is reduced from a VDD supply voltage to a lower voltage during an idle state, thereby reducing leakage currents in the internal circuitry. The first internal supply voltage (VDDa) may be reduced to a voltage that is one threshold voltage (Vtp) lower than the VDD supply voltage. A second internal supply voltage (VSSa) used to supply the internal circuitry is increased from the VSS supply voltage to a voltage higher than the VSS supply voltage during the idle state, thereby further reducing leakage currents in the internal circuitry. The second internal supply voltage (VSSa) may be increased to a voltage that is one threshold voltage (Vtn) higher than the VSS supply voltage.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: March 7, 2023
    Assignee: Synopsys, Inc.
    Inventors: Jamil Kawa, Thu Nguyen
  • Patent number: 11586898
    Abstract: Various embodiments of high voltage generation circuits, high voltage operational amplifiers, adaptive high voltage supplies, adjustable high voltage incrementor, adjustable reference supplies, and reference circuits are disclosed. These circuits optionally can be used for programming a non-volatile memory cell in an analog neural memory to store one of many possible values.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: February 21, 2023
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly
  • Patent number: 11573588
    Abstract: Apparatus and methods are disclosed for providing a bias, comprising a bias generator circuit including a high voltage (HV) circuit configured to generate a regulated high voltage (HV) from an HV line and provide the regulated HV at an HV regulated line and a low voltage (LV) circuit configured to generate a low voltage (LV) differential from the HV line and to provide the LV differential at an LV line.
    Type: Grant
    Filed: December 24, 2021
    Date of Patent: February 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Michele Piccardi, Xiaojiang Guo
  • Patent number: 11562784
    Abstract: Apparatuses, systems, and methods for voltage based random number generation. A memory may include a number of different voltages, which may be used to power various operations of the memory. During access operations to the memory, the voltage may vary, for example as word lines of the memory are accessed. The variability of the voltage may represent a source of randomness and unpredictability in the memory. A random number generator may provide a random number based on the voltage. For example, an analog to binary converter (ADC) may generate a binary number based on the voltage, and the random number may be based on the binary number.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: January 24, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Sujeet Ayyapureddi
  • Patent number: 11521682
    Abstract: Numerous embodiments are disclosed for providing temperature compensation in an analog memory array. A method and related system are disclosed for compensating for temperature changes in an array of memory cells by measuring an operating temperature within the array of memory cells and changing a threshold voltage of a selected memory cell in the array of memory cells to compensate for a change in the operating temperature.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: December 6, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Steven Lemke, Nhan Do, Vipin Tiwari, Mark Reiten
  • Patent number: 11521679
    Abstract: Disclosed is a memory device for cancelling a sneak current. The memory device according to the exemplary embodiment of the present disclosure includes a memory cell array which includes a plurality of word lines and a plurality of bit lines intersecting each other and memory cells disposed at intersections of the word lines and the bit lines; and a sensing circuit which supplies a bit line current to all or some of the bit lines, cancels a sneak current based on the bit line current by at least one switching control, and senses and amplifies data stored in the memory cell to output the sensed and amplified data.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: December 6, 2022
    Assignee: UIF (University Industry Foundation), Yonsei University
    Inventors: Seong Ook Jung, Tae Hyun Kim, Byung Kyu Song
  • Patent number: 11500858
    Abstract: Aspects described herein include a method of generating three-dimensional (3D) spikes. The method comprises receiving a signal comprising time-series data and generating a first two-dimensional (2D) grid. Generating the first 2D grid comprises mapping segments of the time-series data to respective positions of the first 2D grid, and generating, for each position, a spike train corresponding to the respective mapped segment. The method further comprises generating a second 2D grid including performing, for each position, a mathematical operation on the spike train of the corresponding position of the first 2D grid. The method further comprises generating a third 2D grid including performing spatial filtering on the positions of the second 2D grid. The method further comprises generating a 3D grid based on a combination of the first 2D grid, the second 2D grid, and the third 2D grid. The 3D grid comprises one or more 3D spikes.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: November 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: Umar Asif, Subhrajit Roy, Jianbin Tang, Stefan Harrer
  • Patent number: 11495638
    Abstract: Technologies relating to crossbar array circuits with a 2T1R RRAM cell that includes at least one NMOS transistor and one PMOS transistor for low voltage operations are disclosed. An example apparatus includes a word line; a bit line; a first NMOS transistor; a second PMOS transistor; and an RRAM device. The first NMOS transistor and the second PMOS transistor are in parallel as a pair, wherein the pair connects in series with the RRAM device. The apparatus may further include an inverter, via which the second gate terminal of the second PMOS transistor is connected to the first gate terminal.
    Type: Grant
    Filed: August 25, 2019
    Date of Patent: November 8, 2022
    Assignee: TETRAMEM INC.
    Inventors: Wenbo Yin, Ning Ge
  • Patent number: 11450396
    Abstract: A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: September 20, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungryun Kim, Yoonna Oh, Hohyun Shin, Jaeho Lee
  • Patent number: 11430502
    Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: August 30, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Toshifumi Watanabe, Naofumi Abiko
  • Patent number: 11386944
    Abstract: According to one embodiment, a memory device includes first and second wiring lines, a memory cell connected between the first and second wiring lines and including a resistance change memory element and a switching element connected in series to the resistance change memory element, and a determination circuit determining a determination object resistance state set in advance to the resistance change memory element based on a determination object voltage applied to the second wiring line when the switching element makes a transition from an on-state to an off-state.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: July 12, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Kosuke Hatsuda
  • Patent number: 11367469
    Abstract: A shift register unit circuit includes an input sub-circuit, a pull-up sub-circuit, a pull-down control sub-circuit, a pull-down sub-circuit, and a voltage regulating sub-circuit. The input sub-circuit receives an input signal from a signal input terminal to control a potential of a pull-up node. The pull-up sub-circuit outputs a gate driving signal to an output terminal under control of the potential of the pull-up node and a signal from a first signal terminal. The pull-down control sub-circuit conducts a pull-down node with a first node under control of a signal from the second signal terminal. The pull-down sub-circuit conducts the pull-up node with the first node and the turn-down signal terminal with the output terminal under control of a potential of the pull-down node. The voltage regulating sub-circuit conducts the first node with the turn-down signal terminal under control of a potential of the first node.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: June 21, 2022
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xianrui Qian, Guolei Wang, Tong Yang, Suzhen Mu, Peng Chen, Yuting Chen, Zixuan Wang, Bo Li
  • Patent number: 11355189
    Abstract: A method of programming a resistive memory device, and a corresponding resistive memory device, which includes the resistive memory device, in response to a write command, applying a write pulse to a selected memory cell arranged in a region where a selected word line intersects with a selected bit line; and after the applying the write pulse, applying a dummy pulse to at least one unselected memory cell. The at least one unselected memory cell is connected to at least one of the selected word line, the selected bit line, a first word line adjacent to the selected word line, and a first bit line adjacent to the selected bit line.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: June 7, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Moonki Jung
  • Patent number: 11335400
    Abstract: In a computing-in-memory chip and a memory cell array structure, a memory cell array therein includes a plurality of memory cell sub-arrays arranged in an array. Each memory cell sub-array comprises a plurality of switch units and a plurality of memory cells arranged in an array; and first terminals of all memory cells in each column are connected to a source line, second terminals of all the memory cells are connected to a bit line, third terminals of all memory cells in each row are connected to a word line through a switch unit, a plurality of rows of memory cells are correspondingly connected to a plurality of switch units, control terminals of the plurality of switch units are connected to a local word line of the memory cell sub-array, and whether to activate the memory cell sub-array is controlled by controlling the local word line.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: May 17, 2022
    Assignee: Beijing Zhicun (Witin) Technology Corporation Ltd.
    Inventor: Shaodi Wang
  • Patent number: 11327860
    Abstract: A memory device and methods for programming and reading a memory device are provided. The memory device includes a memory array and a memory controller. The memory array includes a plurality of one-time programmable (OTP) cells, in which the OTP cells comprises a plurality of data cells for storing data, a plurality of supplementary cells in parallel to the data cells, and one or more redundant cells for each of a plurality of sets of the data cells. The memory controller is configured to program the data cells. The memory controller verifies and records a state of each data cell in a set of the data cells in the corresponding supplementary cell after the programming, and stores the data to be programmed to the data cell using the one or more redundant cells reserved for the set of the data cells when the data cell is verified as failed.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Der Chih, Jonathan Tsung-Yung Chang
  • Patent number: 11301148
    Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hao Hsu, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Hung-Jen Liao, Jung-Ping Yang, Jonathan Tsung-Yung Chang, Wei Min Chan, Yen-Huei Chen, Yangsyu Lin, Chien-Chen Lin
  • Patent number: 11289155
    Abstract: According to one embodiment, there is provided a semiconductor memory device including a bit cell, a pair of bit lines and an assist circuit. The pair of bit lines are electrically connected to the bit cell. The assist circuit is configured to be connected to the bit lines and including one or more capacitive elements. A ratio between a parasitic capacitance value of each of the bit lines and a capacitance value of the assist circuit is adjustable.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: March 29, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tsuyoshi Midorikawa, Toshiaki Dozaka
  • Patent number: 11282563
    Abstract: The present disclosure includes apparatuses and methods for performing operations by a memory device in a self-refresh state. An example includes an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to direct performance of compute operations on data stored in the array when the array is in a self-refresh state.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Perry V. Lea, Glen E. Hush
  • Patent number: 11269648
    Abstract: Systems, apparatuses, and methods for organizing bits in a memory device are described. In a number of embodiments, an apparatus can include an array of memory cells, a data interface, a multiplexer coupled between the array of memory cells and the data interface, and a controller coupled to the array of memory cells, the controller configured to cause the apparatus to latch bits associated with a row of memory cells in the array in a number of sense amplifiers in a prefetch operation and send the bits from the sense amplifiers, through a multiplexer, to a data interface, which may include or be referred to as DQs. The bits may be sent to the DQs in a particular order that may correspond to a particular matrix configuration and may thus facilitate or reduce the complexity of arithmetic operations performed on the data.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: March 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Glen E. Hush, Aaron P. Boehm, Fa-Long Luo
  • Patent number: 11257537
    Abstract: Provided are a voltage generator circuitry for generating an internal power supply voltage of a memory device and an operation method thereof. In the memory device, a voltage generator circuitry generates a first internal power supply voltage when the memory device is in an active mode, generates a second internal power supply voltage when the memory device is in a standby mode, and provides the first internal power supply voltage or the second internal power supply voltage to an internal power supply voltage line for using as an internal power supply voltage of the memory device. When the memory device is in the standby mode, the voltage generator circuitry blocks generation of the first internal power supply voltage by using a first voltage higher than an external power supply voltage.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: February 22, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sanghoon Jung
  • Patent number: 11249509
    Abstract: An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: February 15, 2022
    Inventor: Scott Hanson
  • Patent number: 11237742
    Abstract: A memory system includes a memory device including a plurality of memory blocks and a controller. At least one memory block among the plurality of memory blocks is allocated for one of data attributes. The controller can determine a first data attribute of first data stored in the memory device, based on a first map information item of the first data, and migrate the first data having the first data attribute to a memory block allocated for the first data attribute among the plurality of memory blocks.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: February 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Kyung-Soo Lee
  • Patent number: 11209853
    Abstract: Apparatus and methods are disclosed for providing a bias, comprising a bias generator circuit including a high voltage (HV) circuit configured to generate a regulated high voltage (HV) from an HV line and provide the regulated HV at an HV regulated line and a low voltage (LV) circuit configured to generate a low voltage (LV) differential from the HV line and to provide the LV differential at an LV line, wherein the LV circuit is configured to direct current used to generate the LV differential into the HV regulated line.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: December 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michele Piccardi, Xiaojiang Guo
  • Patent number: 11205470
    Abstract: A main word driver may be coupled to a subword driver to drive a main word line to select the subword driver. The main word driver may include a first transistor having a body and source/drain both coupled to a well. The main word driver may include a well control circuit configured to bias the well. In some examples, the well control circuit may provide a first low potential to the well followed by a second low potential lower than the first potential responsive to a precharge command. The main word driver may include a second transistor coupled to the well control circuit to receive the first and second low potentials and couple the first and second low potentials to the main word line. The body of the second transistor may be coupled to the well. Additional transistors in the main word driver may also be coupled to the well.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: December 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Sang-Kyun Park, Tae H. Kim
  • Patent number: 11196244
    Abstract: An electronic device includes a monitoring unit that monitors a voltage of a first terminal that receives power supplied from a power supply apparatus, and a control unit that performs control so as to stop the power supply from the power supply apparatus if a voltage variation per unit time of the first terminal is not less than a first predetermined value or the voltage of the first terminal is not less than a second predetermined value.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: December 7, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hiroshi Moritomo
  • Patent number: 11195581
    Abstract: A memory cell includes: a transistor having a control terminal coupled to a first node; a first terminal coupled to a first signal line; and a second terminal coupled to a second signal line; a first resistance element, having a first terminal coupled to the first node and a second terminal coupled to a second node; and a second resistance element, having a first terminal coupled to the first node and a second terminal coupled to a third node.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: December 7, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Ming-Hsiu Lee
  • Patent number: 11183245
    Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a pre-boosting phase occurring prior to a program phase. The control logic causes a first positive pre-boosting voltage to be applied to a first plurality of word lines of a data block of the memory array during the pre-boosting phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: November 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hong-Yan Chen, Yingda Dong
  • Patent number: 11176887
    Abstract: The present disclosure relates to a display apparatus enhancing a display quality and a method of driving the display apparatus. The display apparatus comprises a display panel and a power voltage generator. The display panel comprises a plurality of pixels. The power voltage generator is configured to output a first initialization voltage, a second initialization voltage, a first power voltage, and a second power voltage less than the first power voltage to the plurality of pixels. The power voltage generator is configured to output the second initialization voltage substantially equal to the second power voltage in response to an emergency shutdown signal.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: November 16, 2021
    Inventors: Jung Deok Seo, Seung-Kyu Lee, Min Seong Son
  • Patent number: 11170828
    Abstract: A voltage generating circuit, a semiconductor storage device, and a bit line charging method thereof are provided. The voltage generating circuit includes: an INTVDD generating circuit for generating an internal power supply voltage INTVDD from an external power supply voltage EXVDD; a VDD_V1 generating circuit for generating an internal power supply voltage VDD_V1 from the external power supply voltage EXVDD; and a V1_driving circuit generating a charging voltage for charging the bit line at an output node by using the internal power supply voltage VDD_V1. The V1_driving circuit may generate voltages V1 having different driving capability. The V1_driving circuit charges the bit line with the voltage V1 having a weak driving capability during a first charging period of the bit line and charges the bit line with the voltage V1 having a strong driving capability during a second charging period.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: November 9, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Sho Okabe
  • Patent number: 11158390
    Abstract: A method and apparatus for performing automatic power control in a memory device are provided. The method includes: during an initialization phase of the memory device, performing signal level detection on a reference clock request signal to determine whether the reference clock request signal is at a first predetermined voltage level or a second predetermined voltage level, for performing the automatic power control for the memory device, wherein the reference clock request signal is received through an IO pad; and according to a logic value carried by an input signal of a selective regulation circuit (SRC), performing selective power control to generate a secondary power voltage according to a main power voltage, wherein the selective power control makes the secondary power voltage be either equal to the main power voltage or a regulated voltage of the main power voltage in response to the logic value carried by the input signal.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: October 26, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Yu-Wei Chyan, Ping-Yen Tsai, Jiyun-Wei Lin
  • Patent number: 11156505
    Abstract: A reconfigurable all-digital temperature sensor includes a NAND gate and several delay units, the NAND gate comprises two input terminals and an output terminal, one input terminal is used for external starting control signal; a plurality delay units are connected in series, the input end of the first delay unit is connected to the output terminal of the NAND gate, and the output end of the last delay unit is connected to another input terminal of the NAND gate, thereby forming a ring oscillator structure; each delay unit includes a leakage-based inverter and a Schmitt trigger, and the output end of the leakage-based inverter is connected to the input end of the Schmitt trigger. The reconfigurable all-digital temperature sensor can realize the conversion of temperature-leakage-frequency based on the ring oscillator structure in the temperature range of ?40˜125° C., thereby reducing the design complexity and achieving high accuracy.
    Type: Grant
    Filed: December 25, 2019
    Date of Patent: October 26, 2021
    Assignee: Semitronix Corporation
    Inventors: Zhong Tang, Yun Fang, Xiaopeng Yu, Zheng Shi