Abstract: A bitline sense amplifier including: an amplifier which is connected between a first sensing bitline and a second sensing bitline, and detects and amplifies a voltage difference between a first bitline and a second bitline in response to a first control signal and a second control signal; and an equalizer which is connected between a first supply line through which the first control signal is supplied and a second supply line through which the second control signal is supplied, and pre-charges the first bitline and the second bitline with a precharge voltage in response to an equalizing control signal, wherein the equalizer includes an equalizing enable transistor in which a source terminal is connected to the first supply line and performs equalizing in response to the equalizing control signal.

Abstract: A memory device according to the present invention may comprise: a memory cell array in which memory cells of a latch structure are connected in matrix form to word lines and bit line pairs composed of bit lines and inverted bit lines; and a driving circuit which, during an ON period in which the word lines activate first memory cells connected to the corresponding word lines, continuously programs or reads n (n is a natural number of 2 or more) second memory cells among the first memory cells through n first bit line pairs.

Abstract: Prior knowledge of access pattern is leveraged to improve energy dissipation for general matrix operations. This improves memory access energy for a multitude of applications such as image processing, deep neural networks, and scientific computing workloads, for example. In some embodiments, prior knowledge of access pattern allows for burst read and/or write operations. As such, burst mode solution can provide energy savings in both READ (RD) and WRITE (WR) operations. For machine learning or inference, the weight values are known ahead in time (e.g., inference operation), and so the unused bytes in the cache line are exploited to store a sparsity map that is used for disabling read from either upper or lower half of the cache line, thus saving dynamic capacitance.

Abstract: A method for operating a memory device includes providing a memory block including at least one source select transistor coupled between a source line and a bit line, a plurality of memory cells, and a drain select transistor, controlling a source select line coupled to the at least one source select transistor and a plurality of word lines coupled to the plurality of memory cells to be in a floating state, and applying an erase voltage to the source line and the bit line.

Abstract: A variable resistive memory device includes a memory cell, a first current-applying block, a second current-applying block and a mode setting circuit. The memory cell includes a first electrode, a second electrode, and a memory layer, the memory layer interposed between the first electrode and the second electrode. The first current-applying block is configured to flow a first current to the first electrode that flows from the first electrode to the second electrode. The second current-applying block is configured to flow a second current to the second electrode that flows from the second electrode to the first electrode. The mode setting circuit is configured to selectively provide any one of the first electrode of the first current-applying block and the second electrode of the second current-applying block with a first voltage. When the memory cell is selected, the selected current-applying block, among the first current-applying block and the second current-applying block, is driven.

Abstract: Embodiments of the present invention provide a semiconductor integrated circuit of a memory. The semiconductor integrated circuit can comprise a column selection module, a local read-write conversion module, and an amplifier module. The column selection module can be configured to couple a first data line to a bit line and couple a complementary data line to a complementary bit line. The local read-write conversion module can be configured to perform data transmission from at least one of the first data line or the first complementary data line to a second data line. The data transmission can occur during a memory read-write operation and in response to the local read-write conversion module receiving a read write control signal. The amplifier module can be configured to amplify data of the second data line based on a reference signal of a reference data line. The reference signal can serve as a reference for amplifying the data of the second data line.

Abstract: A storage device comprises a nonvolatile memory configured to store data that is written in size units of a mapping size, and a storage controller configured to transmit a command to the nonvolatile memory. The storage controller includes a host interface configured to receive a write command from a host device, the write command including a command to write first data to a first address, the first data having a first size smaller than the mapping size. The storage controller includes processing circuitry configured to transmit a read command to the nonvolatile memory, to cause the nonvolatile memory to read second data stored in the nonvolatile memory addressed based on the first address, in response to a determination that the first size is smaller than the mapping size and before the first data is received at the storage controller through the host interface.

Abstract: A semiconductor device includes an operation flag generation circuit configured to generate an operation flag at a time when a flag period elapses from a time when an internal setting signal is generated to perform a write operation accompanied by an auto-precharge operation; and an auto-precharge pulse generation circuit configured to generate an auto-precharge pulse by shifting the operation flag by a pulse generation period set by a period code based on divided docks generated by dividing an internal dock.

Abstract: A read-write conversion circuit includes: a read-write conversion module, performing a read-write operation in response to a read-write control signal to implement data transmission between each of a local data line, a local complementary data line, and a global data line, data signals of the local data line and data signals of the local complementary data line being opposite in phase during the read-write operation, and a control module, outputting a variable read-write control signal in response to a read-write speed configuration signal to control a speed of the read-write operation of the read-write conversion module to be variable.

Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit may include a memory array with a plurality of memory cells, first logic circuitry, first switching circuitry, first latch circuitry, and second switching circuitry. The first logic circuitry may be configured to generate a first bit line pre-charge signal for a first memory cell of the plurality of memory cells, where the first bit line pre-charge signal is generated in response to a sleep signal. The first switching circuitry may be configured to provide power to one or more bit line of the first memory cell in response to the first bit line pre-charge signal. The first latch circuit may receive the sleep signal and the first bit line pre-charge signal and generate a delayed sleep signal.

Abstract: An electronic device includes a pre-charge control circuit configured to generate first and second pre-charge signals with pulses that are selectively generated based on a first and second output control signals that are generated during a read operation, and a data processing circuit configured to pre-charge one of first and second internal nodes based on the first and second pre-charge signals, latch internal data based on first and second input control signals, and output data that is generated from the latched internal data to an external device based on the first and second output control signals. The data is generated from the internal data that is transmitted through one of the first and second internal nodes.

Abstract: Methods, systems, and devices for cell data bulk reset are described. In some examples, a logic state (e.g., a first logic state) may be written to one or more memory cells based on an associated memory device transitioning power states. To write the first logic state to the memory cells, a first subset of digit lines may be driven to a first voltage and a plate may be driven to a second voltage. While the digit lines and plate are driven to the respective voltages, one or more word lines may be driven to the second voltage. In some instances, the word lines may be driven to the second voltage based on charge sharing occurring between adjacent word lines.

Abstract: An in-memory computing apparatus and a computing method thereof are provided. A memory array includes a shifted weight storage area that stores shifted weight values, a shift information storage area that stores the number of shift units, and a shift unit amount storage area that stores a shift unit amount. A shift restoration circuit restores a weight shift amount of a shifted sum-of-products according to the number of shift units of the shifted weight values and a column shift unit amount, so as to generate multiple restored sum-of-products.

Abstract: A non-volatile memory device, including a non-volatile memory cell array, a sense amplifier, a random access memory (RAM), and a buffer circuit, is provided. The sense amplifier is configured to generate readout data. The RAM is configured to store write-in data. The buffer circuit generates a detection result according to target data and the readout data, and writes the detection result to the RAM.

Abstract: A memory device includes an array of memory cells, a bit line connected to the memory cells, and a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level. A bit line precharge circuit has an input terminal configured to receive the power supply voltage at the first voltage level, and the bit line precharge circuit is configured to precharge the bit lines to a second voltage level lower than the first voltage level.

Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of a data interface circuit of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

Abstract: In one example a semiconductor device has a data latch that includes first and second transmission gates and first and second inverters. The first inverter is connected between a first terminal of the first transmission gate and a first terminal of the second transmission gate. The second inverter is connected between a second terminal of the first transmission gate and a second terminal of the second transmission gate. The data latch is configured to store a datum received at the connection between the first transmission gate and the second inverter, and to store a datum received at the connection between the second transmission gate and the first inverter.

Abstract: A memory device and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells disposed in an area where a plurality of word lines and a plurality of bit lines cross each other; a row decoder including row switches and configured to perform a selection operation on the plurality of word lines; a column decoder including column switches and configured to perform a selection operation on the plurality of bit lines; and a control logic configured to control, in a data read operation, a precharge operation to be performed on a selected word line in a word line precharge period, and to control a precharge operation to be performed on a selected bit line in a bit line precharge period; wherein a row switch connected to the selected word line is weakly turned on in the bit line precharge period.

Abstract: Embodiments provide a read operation circuit, a semiconductor memory, and a read operation method. The read operation circuit includes: a DBI encoder configured to read read data from a memory bank, and determine whether to invert the read data according to the number of bits of high data in the read data to output global bus data for transmission through a global bus and DBI data for transmission through a DBI signal line, a DBI port being configured to receive the DBI data; a parallel-to-serial conversion circuit configured to perform parallel-to-serial conversion on the global bus data to generate output data of the DQ port; a data buffer module connected to the memory bank through the global bus; and a precharge module connected to a precharge signal line and configured to set an initial state of the global bus to Low.

Abstract: The memory device includes a memory cell array including a plurality of memory blocks each including a plurality of strings, wherein the plurality of memory blocks are controlled to have a set temperature; a peripheral circuit for performing a read operation on a selected memory block among the plurality of memory blocks; a temperature detection circuit for detecting a temperature of the memory cell array and generating a temperature detection signal based on the temperature of the memory cell array; and a control logic for controlling the peripheral circuit during the read operation and configured to generate a heating control signal that may control the selected memory block to have the set temperature in response to the temperature detection signal.

Abstract: A memory includes writable memory units. Each memory unit is configurable: in a retention state wherein the memory unit is capable of retaining data until a subsequent power-off of the memory unit, and in a non-retention state wherein the memory unit does not retain data and consumes less power than in the first state. A controller configures any memory unit of the memory having undergone at least one write access since its last power-up to be in the retention state. The controller further configures at least one memory unit of the memory that has not undergone any write access since its last power-up in the non-retention state.

Abstract: A novel memory device is provided. A first cell array including a plurality of memory cells and a second cell array including a plurality of memory cells are provided to overlap with each other. Two bit lines included in the first bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. Two bit lines included in the second bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. In the first cell array, one of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair. In the second cell array, the other of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair.

Abstract: Methods, systems, and devices for a memory error indicator related to high-reliability applications are described. A memory device may perform error detection procedures to monitor trends in the quantity of bit errors as an indication of the health of the memory device. A memory device may perform error detection procedures concurrently with refresh procedures to detect a quantity of errors (e.g., in a memory array) without degrading the performance of the device or the memory array. The memory device may compare a quantity of errors detected (e.g., in the memory array) with one or more previously detected quantities of errors to determine one or more differences in the quantities of errors. The memory device may generate an error metric based on the differences, and may determine whether the error metric satisfies a threshold. The memory device may output a status indicator (e.g., to a host device) based on whether the error metric satisfies the threshold.

Abstract: The disclosed write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

Abstract: Techniques are described for optimizing the peak current during a program operation by controlling a timing and ramp rate of a program-inhibit voltage signal as a function of a program loop number and/or program progress. A transition voltage between a regulated ramp up rate and an unregulated ramp up rate can also be adjusted. For initial and final sets of program loops in a program operation, the ramp up of the program-inhibit voltage signal can occur early so that it overlaps with operations of sense circuits in updating their latches based on results from a verify test in a previous program loop. For an intermediate set of program loops, the overlap is avoided. The ramp up rate can be larger and the transition voltage smaller for the initial and final sets of program loops compared to the intermediate set of program loops.

Abstract: The disclosure introduces a write assist scheme that boost the word line of a selected memory cell by using a parasitic capacitor element coupled between the word line and a bit line of at least one unselected memory cell. The SRAM includes a word line, a first bit line, a second bit line, a first memory cell coupled to the first bit line and the word line, a second memory cell coupled to the second bit line and the word line, and a write assist circuit coupled to the second bit line. The write assist circuit is configured to clamp the second bit line to the word line during a write operation of the first memory cell.

Abstract: A semiconductor device includes a cell array, a computation circuit, and a control circuit. The cell array includes a plurality of unit cells configured to store a plurality of first signals by a write operation and to output a plurality of output signals corresponding to the first signals by a read operation. The computation circuit includes a plurality of unit computation circuits receiving the plurality of output signals and being set according to a plurality of second signals during a computation operation. The control circuit is configured to control the cell array and the computation circuit during the write operation, the read operation, and the computation operation.

Abstract: The reference cells used for reading out data are tested efficiently so as to improve the reliability of the readout data. A memory circuit includes multiple memory arrays, a selection circuit, and a sense amplifier. The selection circuit selects values output from memory cells in any of the multiple memory arrays so as to supply a first value and a second value. A sense amplifier has a first input terminal and a second input terminal. The sense amplifier amplifies and outputs the first value supplied to the first input terminal in reference to the second value supplied to the second input terminal.

Abstract: Methods, systems, and devices related to multiplexed signal development in a memory device are described. In one example, an apparatus in accordance with the described techniques may include a set of memory cells, a sense amplifier, and a set of signal development components each associated with one or more memory cells of the set of memory cells. The apparatus may further include a selection component, such as a signal development component multiplexer, that is coupled with the set of signal development components. The selection component may be configured to selectively couple a selected signal development component of the set of signal development components with the sense amplifier, which may support examples of signal development during overlapping time intervals.

Abstract: Embodiments herein describe a multi-port memory system that includes one or more single port memories (e.g., a memory that can perform only one read or one write at any given time, referred to as a 1W or 1R memory). That is, the multi-port memory system can perform multiple read and writes in parallel (e.g., 1R/1W, 1R/3W, 2R/2W, 3R/1W, etc.) even though the memory in the system can only perform one read or one write at any given time. The advantage of doing so is a reduction in area and power.

Abstract: Multi-stage content addressable memory devices are described. Some embodiments relate to memory devices including a plurality of rows of memory cells, multiple match lines and multiple pre-charge circuits. A first row of the plurality of rows includes a first segment and a second segment. The first segment may include a first subset of the memory cells of the first row and the second segment may include a second subset of the memory cells of the first row. The first match line is coupled to the memory cells of the first subset, and the second match line is coupled to the memory cells of the second subset. The first pre-charge circuit is configured to pre-charge the first match line to a first pre-charge voltage, and the second pre-charge circuit is configured to pre-charge the second match line to a second pre-charge voltage different from (e.g., greater than) the first pre-charge voltage.

Abstract: The present disclosure discloses a ternary content addressable memory based on a memory diode, which includes a plurality of kernel units having functions of storing data, erasing/writing data, and comparing data; the kernel units are arranged in an array, all kernel units in a unit of row are connected to a same matching line, and all kernel units in a unit of column are connected to a same pair of complementary search signal lines; the kernel unit includes two memory diodes; top electrodes of a first memory diode and a second memory diode are respectively connected to a pair of complementary search signal lines, and bottom electrodes of the first memory diode and the second memory diode are connected to a same matching line.

Abstract: A device for performing a refresh operation includes a row control circuit and a row decoder. The row control circuit is configured to generate a bank active signal and a row address for controlling an active operation for a first memory bank based on a refresh signal. The row control circuit is also configured to generate the bank active signal for controlling the active operation for a second memory bank based on a power control signal. The row decoder is configured to receive the bank active signal and the row address to control the active operation for the first memory bank and the second memory bank.

Abstract: A multi-branch analog multiplexer (anamux) includes protection circuitry to help dissipate both positive and negative injected current without increasing the size of hardening transistors in each branch, thereby avoiding increased leakage current and enabling an analog to digital converter to operate with the required accuracy. The protection circuitry is tied to the body of the hardening transistor to lower the threshold voltage of the hardening device, thereby enabling the hardening device to handle more of the injected current.

Abstract: Apparatuses for controlling precharge timings in a semiconductor device are described. An example apparatus includes first and second memory and a precharge timing circuit. The first memory includes a first memory bank including a first data line and a second memory bank including a second data line. The second memory includes a third memory bank including a third data line and a fourth memory bank memory bank including a fourth data line. The precharge timing circuit provides first, second, third and fourth precharge activation signals. The first, second, third and fourth precharge activation signals activate precharge of the first, second, third and fourth data lines, respectively. The precharge timing circuit provides the first and second precharge activation signals at different times from each other. The precharge timing circuit provides the third and fourth precharge activation signals at different times from each other.

Abstract: A semiconductor device includes a peripheral circuit and a core circuit. The peripheral circuit enters a smart refresh mode in which a smart refresh operation is performed based on a command. The peripheral circuit generates a latch address signal from a target address signal to output the latch address signal through a global input/output (I/O) line in the smart refresh mode. The core circuit performs an adding operation and a subtracting operation of the latch address signal to generate first and second internal address signals. The core circuit performs the smart refresh operation for first and second banks based on the first and second internal address signals.

Abstract: Disclosed are a reference voltage generating circuit and a display device. The reference voltage generating circuit includes a timing control circuit, a digital-to-analog conversion circuit, an operational amplifier circuit, a drive circuit, a switch control circuit, a first switch circuit, and a second switch circuit. The switch control circuit generates a control signal according to a frame start signal and a clock signal provided by the timing control circuit, and outputs the control signal to the first switch circuit and the second switch circuit to control the channels inside the first switch circuit and the second switch circuit to be turned on sequentially, such that an analog voltage signal output by the digital-to-analog conversion circuit can be output to the drive circuit through the first switch circuit, the operational amplifier circuit and the second switch circuit, to provide a reference voltage signal for the drive circuit.

Abstract: A memory device includes memory cells operably connected to column signal lines and to word signal lines. The column signal lines associated with one or more memory cells to be accessed (e.g., read) are precharged to a first voltage level. The column signal lines not associated with the one or more memory cells to be accessed are precharged to a second voltage level, where the second voltage level is less than the first voltage level.

Abstract: A memory circuit includes a first memory cell, a second memory cell and a sense amplifier. The sense amplifier is coupled to the first memory cell by a first bit line, and coupled to the second memory cell by a second bit line. The sense amplifier includes a header switch, a footer switch, a first cross-coupled inverter and a second cross-coupled inverter. The header switch has a first size, and is coupled to a first node and a first supply voltage. The footer switch has a second size, and is coupled to a second node and a second supply voltage. The first size is greater than the second size. The first size includes a first number of fins or a first channel width. The second size includes a second number of fins or a second channel width.

Abstract: A display device includes a display panel including a plurality of pixel rows, and a panel driver configured to drive the display panel. The panel driver includes a scan on time decider configured to receive line image data for each of the plurality of pixel rows, and to determine a scan on time change amount for each of the plurality of pixel rows based on the line image data, and a scan control block configured to adjust a scan pulse applied to each of the plurality of pixel rows according to the scan on time change amount.

Abstract: Devices and methods include a command interface configured to receive commands, such as a write with an automatic precharge. A bank-specific decoder decodes the write with an automatic precharge command for a corresponding memory bank and outputs a write auto-precharge (WrAP) signal. This WrAP signal has not been adjusted for a write recovery time for the memory bank. Accordingly, bank processing circuitry in a bank receiving the WrAP signal uses the WrAP to cause its internal lockout circuitry to apply a tWR lockout based at least in part on a mode register setting and on the WrAP signal indicating receipt of the write with an automatic precharge command.

Abstract: Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, an apparatus may include a memory cell, a differential amplifier having a first input node, a second input node, and an output node that is coupled with the first input node via a first capacitor, and a second capacitor coupled with the first input node. The apparatus may include a controller configured to cause the apparatus to bias the first capacitor, couple the memory cell with the first input node, and generate, at the output node, a sense signal based at least in part on biasing the first capacitor and coupling the memory cell with the first input node. The apparatus may also include a sense component configured to determine a logic state stored by the memory cell based at least in part on the sense signal.

Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.

Abstract: A low-power image capture device includes a first image buffer in SRAM coupled to receive images from an image sensor, and a second image buffer receiving images transferred in bursts from the first image buffer, the second image buffer implemented in PASR DRAM, the image buffers together operating as a first-in, first-out, (FIFO) buffer. The device includes an activation detector. The PASR DRAM is powered while receiving bursts of images from the first image buffer, and when the image capture device is in the activated mode; and in ultra-low power PASR mode otherwise. A method includes capturing images into the first image buffer, transferring the images in bursts into a second image buffer in PASR DRAM powered while receiving the images in bursts, the PASR DRAM otherwise in ultra-low power PASR mode; and, upon activating, an image processor receiving images from the second image buffer.

Abstract: Low-power compute-in-memory (CIM) systems employing CIM circuits that include static random access memory (SRAM) bit cells circuits. The CIM circuits can be used for multiply-and-accumulate (MAC) operations. The CIM circuits can include five-transistor (5T) SRAM bit cells that each have a single bit line coupled to an access circuit for accessing the SRAM bit cell for read/write operations. The CIM circuit also includes a multiplication circuit (e.g., an exclusive OR (XOR)-based circuit) coupled to the SRAM bit cell. The CIM circuit is configured to perform multiplication of an input data value received by the multiplication circuit with a weight data value stored in the SRAM bit cell. The reduction of an access circuit in the 5T SRAM bit cell allows the pull-up voltage at a supply voltage rail coupled to the inverters of the 5T SRAM bit cell to be reduced to reduce standby power while providing storage stability.

Abstract: In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portions of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portion of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry.

Abstract: Methods, systems, and devices for performing quick precharge command sequences are described. An operating mode that is associated with a command sequence having a reduced duration relative to another operating mode may be configured at a memory device. The operating mode may be configured based on determining that a procedure does not attempt to preserve or is independent of preserving a logic state of accessed memory cells, among other conditions. While operating in the mode, the memory device may perform a received precharge command using a first set of operations having a first duration—rather than a second set of operations having a second set of operations having a second, longer duration—to perform the received precharge command. The first set of operations may also use less current or introduce less disturbance into the memory device relative to the second set of operations.

Abstract: The present technology relates to a memory device and a method of operating the same. The memory device includes a memory block, a first page buffer group and a second page buffer group connected to bit lines of the memory block, and control logic configured to control the first page buffer group and the second page buffer group to perform a sense node precharge operation partially simultaneously.

Abstract: Apparatuses and methods for implementing access line loads for sense amplifiers for open access line sensing. An example apparatus may include a memory array comprising a plurality of sense amplifiers. A first sense amplifier is coupled to a first access line segment and to a second access line segment and a second sense amplifier is coupled to a third access line segment and to a load segment. The first, second, and third access line segments are coupled to a respective plurality of memory cells. The load segment comprise load circuitry configured to provide a capacitive load to the second sense amplifier based on a capacitive load of the third access line segment.

Abstract: Various implementations described herein are related to a device having an array of bitcells that are accessible via wordlines and bitlines including unselected bitlines and a selected bitline. Each bitcell in the array of bitcells may be selectable via a selected wordline of the wordlines and the selected bitline of the bitlines. The device may include precharge circuitry that is configured to selectively precharge the unselected bitlines and the selected bitline before arrival of a wordline signal on the selected wordline.