Abstract: A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.

Abstract: An integrated circuit includes a pulse width modulator. The pulse width modulator includes a multiplexer that receives a plurality of data delay signals. Each of the data delay signals is based on a data signal and a respective clock phase signal. The multiplexer includes a first multiplexer stage and a second multiplexer stage. The first multiplexer stage receives all of the data delay signals and has a relatively large delay. The second multiplexer stage receives to output signals from the first multiplexer stage and has a relatively small delay. The second multiplexer stage outputs a pulse width modulation signal that can have a pulse width corresponding to the offset between two adjacent clock phase signals.

Abstract: A method is presented for temperature assisted programming of flash memory for neuromorphic computing. The method includes training a chip in an environment having a first temperature, adjusting the first temperature to a second temperature in the environment, and employing the chip for inference in the second temperature environment. The first temperature is about 125° C. or higher and the second temperature is about 50° C. or lower.

Abstract: A memory device includes a command interface configured to receive a two-cycle command from a host device via multiple command address bits. The memory device also includes a command decoder configured to decode a first portion of the multiple command address bits in a first cycle of the two-cycle command. The command decoder includes mask circuitry. The mask circuitry includes mask generation circuitry configured to generate a mask signal. The mask circuitry also includes multiplexer circuitry configured to apply the mask signal to block the command decoder from decoding a second portion of the multiple command address bits in a second cycle of the two-cycle command.

Abstract: Memory systems having flying bitlines for improved burst mode read operations and related methods are provided. A memory system comprises a memory array including a first set of memory cells coupled to a first inner wordline and a second set of memory cells coupled to a first outer wordline. The memory system includes a control unit configured to generate control signals for simultaneously: asserting a first wordline signal on the first inner wordline coupled to each of a plurality of inner bitlines, and asserting a second wordline signal on the first outer wordline coupled to each of a plurality of outer bitlines, where each of the plurality of outer bitlines includes a first portion configured to fly over or fly under a corresponding inner bitline, and outputting data from each of the first set of memory cells and the second set of memory cells as part of a burst.

Abstract: The disclosure reduces the risk of collapse of the wall surrounding the trench and suppresses the withstand voltage fluctuation that accompanies the manufacturing variation for a semiconductor device having a super junction structure. The semiconductor device includes a drift layer of a first conductivity type and a plurality of embedded parts embedded in the drift layer. The embedded parts are of a second conductivity type different from the first conductivity type, and the embedded parts are arranged with a first direction as a longitudinal direction and spaced from each other along a second direction that intersects the first direction. A width of each of the embedded parts in the second direction changes continuously along the first direction.

Abstract: An integrated circuit includes a pulse width modulator. The pulse width modulator includes a multiplexer that receives a plurality of data delay signals. Each of the data delay signals is based on a data signal and a respective clock phase signal. The multiplexer includes a first multiplexer stage and a second multiplexer stage. The first multiplexer stage receives all of the data delay signals and has a relatively large delay. The second multiplexer stage receives to output signals from the first multiplexer stage and has a relatively small delay. The second multiplexer stage outputs a pulse width modulation signal that can have a pulse width corresponding to the offset between two adjacent clock phase signals.

Abstract: A memory module includes: a non-volatile memory; and an asynchronous memory interface to interface with a memory controller. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.

Abstract: A sequence circuit (1) includes a detector (2) that detects an occurrence of an event based on an input signal, an acceptor (4) that accepts the event whose occurrence has been detected by the detector, an inhibitor (4) that inhibits the acceptor from accepting another event for a first period using the acceptance of one event by the acceptor as a trigger, a clock pulse generator (3) that generates one or more clock pulses during a period after a second period shorter than the first period elapses from the start of the first period until the first period ends, a determiner (5) that determines a next state based on a current slate and the event accepted by the acceptor, and a latch (6) that latches the next state using the clock pulse. An output of the latch is the current state.

Abstract: Methods, systems, and devices related to data relocation via a cache are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In some cases, the memory device may transfer data from a first address of the memory array to the signal development cache. The memory device may transfer the data stored in the signal development cache to a second address of the memory array based on a parameter associated with the first address of the memory array satisfying a criterion for performing data relocation.

Abstract: Embodiments of the present disclosure provide a method, apparatus, device, and storage medium for processing an access request, and relate to the field of cloud computing. The method includes: acquiring a plurality of to-be-distributed access requests for a storage device, the access requests at least including a group of read requests and a group of write requests; distributing read requests of the group of read requests to a drive device of the storage device without distributing a write request of the group of write requests, until a number of distributed read requests reaches a total number of read requests of the group of read requests or a first threshold number, the drive device being configured to execute the distributed requests on the storage device; and distributing at least one write request of the group of write requests to the drive device.

Abstract: According to one embodiment, a controller of a memory system executes a first write operation of writing write data into a first storage region, in response to reception of one or more write requests for specifying a first zone from a host, during a period from execution of an erase operation of the first storage region until a first time elapses. When the first time has elapsed after execution of the erase operation, in a state in which an unwritten region having a size larger than or equal to a first size remains in the first storage region, the controller does not execute the first write operation, allocates the first storage region as a nonvolatile buffer capable of temporarily storing write data to be written to each of a plurality of zones.

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.

Abstract: A random code generator includes an address Y decoder, an address X decoder, a PUF entropy pool, a processing circuit and an entropy key storage circuit. The address Y decoder includes plural Y control lines. The address Y decoder selectively activates the plural Y control lines according to a first address Y signal. The address X decoder includes plural X control lines. The address X decoder selectively activates the plural X control lines according to a first address X signal. The PUF entropy pool generates an output data according to the activated Y control lines and the activated X control lines. When the random code generator is in a normal working state, the processing circuit processes the output data into a random code according to at least one entropy key from the entropy key storage circuit.

Abstract: Disclosed herein are systems and methods for deleting files. In one aspect, an exemplary method comprises, obtaining at least initial data about a file to be deleted in accordance with an instruction to remove the file from a data storage device, analyzing the file to be deleted and the data storage device to determine at least deletion parameters of the file to be deleted, performing a dynamic formation of a deletion algorithm, wherein the formation further includes the formation of a structure for writing and a determination of a location for the writing during the deletion of the file in accordance with the determined deletion parameters and rules of formation, and deleting the file by applying the deletion algorithm.

Abstract: Apparatus, systems, computer readable storage mediums and/or methods may provide memory integrity by using unused physical address bits (or other metadata passed through cache) to manipulate cryptographic memory integrity values, allowing software memory allocation routines to control the assignment of pointers (e.g., implement one or more access control policies). Unused address bits (e.g., because of insufficient external memory) passed through cache, may encode key domain information in the address so that different key domain addresses alias to the same physical memory location. Accordingly, by mixing virtual memory mappings and cache line granularity aliasing, any page in memory may contain a different set of aliases at the cache line level and be non-deterministic to an adversary.

Abstract: A test control circuit includes a test mode generation circuit. The test mode generation circuit may be configured to generate, while in a fast access mode, a fast test mode signal based on information included in one of a plurality of mode signals and a fast set signal. The test mode generation circuit may be configured to generate, while in a normal mode, a normal test mode signal based on information included in two or more mode signals from the plurality of mode signals and a normal set signal.

Abstract: Methods, systems, and devices for storing and reading data at a memory device are described. A memory device may utilize one or more storage states to store data within a data word. The memory device may exhibit higher data leakage or more power consumption when storing or reading a first storage state compared to storing or reading one or more other storage states. In some cases, the memory device may generate a second data word corresponding to a first data word by modifying each symbol type of the first data word to generate a different symbol type for the second data word. A memory device may reduce the occurrence of a storage state associated with large data leakage, or high-power consumption, or both. Further, the memory device may generate and store an indicator indicating the transformation of a corresponding data word.

Abstract: An information handling system includes a processing unit that is coupled to a memory device by a communication channel. The processing unit includes a memory controller and is configured to host a basic input output system (BIOS). The memory device, which may include a dual in-line memory module (DIMM), stores serial presence detect (SPD) information. In an embodiment, the BIOS obtains the SPD information and parameters of the communication channel, such as channel impedance and channel length. In this embodiment, the BIOS uses a look-up table to determine an equalization of the communication channel based on the obtained SPD information and the obtained parameters of the communication channel, and utilizes the memory controller to set the equalization of the communication channel, such as by setting or controlling settings of transmission and reception components of the memory controller.

Abstract: According to one general aspect, an apparatus may include a flip-flop circuit. The flip-flop circuit may include a selection circuit, a memory element circuit, a clock circuit. The selection circuit to select, as the selected input signal, between at least two input signals. The memory element circuit synchronously controlled by a clock signal, and configured to store the selected input signal. The clock circuit configured to output, at least, an earlier version of the clock signal and a later version of the clock signal. The selection circuit is configured to be synchronously controlled, at least in part, by the earlier version of the clock signal such that the selected input signal is held stable when being read by the memory element circuit.

Abstract: A non-volatile memory is organized in pages and has a word writing granularity of one or more bytes and a block erasing granularity of one or more pages. Logical addresses are scrambling into physical addresses used to perform operations in the non-volatile memory. The scrambling includes scrambling logical data addresses based on a page structure of the non-volatile memory and scrambling logical code addresses based on a word structure of the non-volatile memory.

Abstract: Apparatus, and an associated method, for enhancing security and preventing hacking of a flash memory device. The apparatus and method use a random number to offset the read or write address in a memory cell. The random number is generated by determining the leakage current of memory cells. In another embodiment, random data can be written or read in parallel to thwart hackers from determining contents of data being written or read by monitoring sense amplifiers.

Abstract: A power control device includes a memory device and a resistor coupled to the memory device. The memory device includes a first memory block storing a plurality of groups of performance parameters and a second memory block storing a power supply program. A resistance of the resistor corresponds to one of the groups of performance parameters. The power control device is configured to control power supply to an electronic device coupled to the power control device according to the power supply program and the one of the groups of performance parameters corresponding to the resistance of the resistor.

Abstract: Systems and methods for determining a physical block address (PBA) of a non-volatile memory (NVM) to enable a data access of a corresponding logical block address (LBA) are described. One such method includes generating a first physical block address (PBA) candidate from a LBA using a first function; generating a second physical block address (PBA) candidate from the LBA using a second function; and selecting either the first PBA candidate or the second PBA candidate for the data access based on information related to a background swap of data stored at the first PBA candidate and a background swap of data stored at the second PBA candidate.

Abstract: A double data rate memory includes a circuit board, a goldfinger connection interface, at least 16 first IC chips, at least 16 second IC chips, a first and a second read-only memory. The circuit board has a first surface, a second surface, a first region and a second region. The first IC chips are disposed on the first surface. The second IC chips are disposed on the second surface. The first read-only memory is connected with the first and the second IC chips disposed on the first region. The second read-only memory is connected with the first and the second IC chips disposed on the second region. 10 pins of the goldfinger connection interface are connected with the second read-only memory and the first and the second IC chips disposed on the second region to make them operate. At least 32 IC chips are effectively operated in single one memory.

Abstract: Memory device and methods for controlling the memory device include an input buffer of the memory device receives input data from external to the memory device and outputs serial data. A serial shift register that shifts in the serial data and to output the serial data in a parallel format as parallel data. A parallel register that receives the parallel data from the serial shift register and buffered data directly from the input buffer. The parallel register that passes the parallel data and the buffered data to a data write bus to be stored memory banks of the memory device. Serial-to-parallel conversion circuitry controls loading of the parallel register from the serial shift register and the input buffer. The serial-to-parallel conversion circuitry utilizes a first loading signal to load the buffered data into the parallel register and a second loading signal to load the parallel data into the parallel register.

Abstract: A memory system includes a semiconductor memory device including a plurality of memory blocks, including a first block storing data and a second block storing backup data, a plurality of pins, and a controller configured to output a control signal to the semiconductor memory in accordance with the command. When the controller receives from outside of the memory system, a read command for the data in the first block, and the data in the first block are available, the controller is configured to transmit the data in the first block to the outside of the memory system. When the controller receives from outside of the memory system, a read command for the data in the first block, and the data in the first block are not available, the controller is configured to transmit the backup data in the second block to the outside of the memory system.

Abstract: A resource arbiter in a system with multiple shared resources and multiple requestors may implement an adaptive resource management approach that takes advantage of time-varying requirements for granting access to at least some of the shared resources. For example, due to pipelining, signal timing issues, or a lack of information, more resources than are required to perform a task may need to be available for allocation to a requestor before its request for the needed resources is granted. The requestor may request only the resources it needs, relying on the arbiter to determine whether additional resources are required in order to grant the request. The arbiter may park a high priority requestor on idle resources, thus allowing requests for those resources by the high priority requestor to be granted on the first clock cycle of a request. Other requests may not be granted until at least a second clock cycle.

Abstract: A memory system includes a semiconductor memory and a controller. The controller is configured to perform a read operation on the semiconductor memory in response to a read instruction received from a host. In response to the read instruction that includes a first logical address, the controller converts the first logical address into a first physical address, and issues a read command and a second physical address different from the first physical address, to the semiconductor memory.

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Abstract: Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. In another embodiment, a method includes detecting multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle, and granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache.

Abstract: A memory system includes a memory apparatus including a write driver and a memory controller configured to control the memory apparatuses. The memory controller includes a command comparison circuit configured to compare word line addresses, bit line addresses, and pieces of write data of a first write command and a second write command and output a simultaneous write control signal having a first level when the bit line addresses and the pieces of write data are the same as each other and most significant bits (MSBs) of the word line addresses are different from each other and a processor configured to transfer a simultaneous write command for simultaneously operating the first write command and the second write command to the memory apparatus when the simultaneous write control signal having the first level is output from the command comparison circuit.

Abstract: System and method for performing correlation analysis. A program that includes multiple program structures and one or more data objects is stored. Each data object is shared by at least two of the program structures. For each program structure, decomposition effects on each of the data objects shared by the program structure resulting from each of a respective one or more optimizing transforms applied to the program structure are analyzed. One or more groups of correlated structures are determined based on the analyzing. Each group includes two or more program structures that share at least one data object, and at least one optimizing transform that is compatible with respect to the two or more program structures and the shared data object. For at least one group, the at least one optimizing transform is usable to transform the two or more program structures to meet a specified optimization objective.

Abstract: According to one embodiment, there is provided a power management method for connecting a server to office machines to control electric power of the office machines. The office machines respectively store machine side power plans, which are operation states with respect to transition times. The server stores server side power plans of the office machines and subjects electric powers of the office machines to management control. The power management method includes comparing the server side power plan stored in the server and the machine side power plan stored in the office machines, comparing, when an operation state based on the server side power plan and an operation state based on the machine side power plan are different, power consumptions in the operation state based on the server side power plan and an operation state based on the machine side power plan, and changing an operation state of the office machine to be an operation state with small power consumption.

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

Abstract: A memory system includes a two memory modules and a memory controller. The memory modules each include at least a first memory package corresponding to a first number of memory ranks (e.g. one memory rank) and a second memory package corresponding to a second number of memory ranks (e.g. two memory ranks) that is greater than the first number of memory ranks. For each module, the memory packages may be asymmetrically staggered such that one memory package is further from the memory controller than the other memory package. The memory controller is coupled to the memory packages of both modules via a common data line and generates control information for controlling the on-die termination (ODT) of the memory packages.

Abstract: One embodiment relates to an integrated circuit which includes a method of dynamically adjusting a receive buffer in an integrated circuit. A fixed-size buffer circuit of the receive buffer is used to buffer data received by way of a serial interface circuit. The performance of the serial interface circuit are monitored. The receive buffer is dynamically extended based on said performance. Other embodiments, aspects, and features are also disclosed.

Abstract: A memory system is provided which includes multiple semiconductor memories having arrays of memory cells and a memory controller configured to provide an address in common to the multiple memories. First and second addresses corresponding to first and second rows of memory cells in first and second memories are selected according to the address in common. The first row and its adjacent rows in the first memory can all be different from the second row and its adjacent rows in the second semiconductor memory. Different conversion schemes can provide scramble information used to convert the address in common into the first and second addresses.

Abstract: A cooling controller of a cooling canister is configured to coordinate control of a set of fans coupled with the cooling canister with another set of fans coupled with an adjacent cooling canister. The cooling canister and the adjacent cooling canister include openings that are coupled together that permit air to flow between the cooling canister and the adjacent cooling canister. In some embodiments, the cooling control also coordinates control of a damper in at least one of the coupled openings of the coupled cooling canister and adjacent cooling canister.

Abstract: A semiconductor memory device includes a block array having an m number of memory blocks in a row direction and an n number of memory blocks in a column direction (m being an integer of 2 or more and n being an integer of 1 or more), a page selection circuit configured to select a row in the block array from which a page is to be selected, and a page buffer configured to store data to be written in a page selected by the page selection circuit or data read from the page. Each of the memory blocks includes a memory cell array having a plurality of memory cells, a row selection circuit configured to select a row of the memory cell array, and a column selection circuit configured to select a column of the memory cell array.

Abstract: A secure data storage device for preventing tampering with data stored thereon includes a two-dimensional memory array for storing data, the array includes a predetermined number of data words. Each data word includes a set of bits, and is associated with a single physical address in the memory array. A key storage area for storing a key of the data storage device is included in the device. The secure data storage device includes an address conversion unit configured to convert a logical address to a corresponding physical address which points to a location in the memory array. The device includes a bit mixing unit for mixing bit values of an input data word to obtain a mixed word value, such that the mixed word value is a rearrangement of the bit values of the input data word. The device is electrically connectable to a host.

Abstract: A semiconductor memory device includes a control logic and a memory cell array in which a plurality of memory cells are arranged. The memory cell array includes a plurality of bank arrays, and each of the plurality of bank arrays includes a plurality of sub-arrays. The control logic controls an access to the memory cell array based on a command and an address signal. The control logic dynamically sets a keep-away zone that includes a plurality of memory cell rows which are deactivated based on a first word-line when the first word-line is enabled. The first word-line is coupled to a first memory cell row of a first sub-array of the plurality of sub-arrays. Therefore, increased timing parameters may be compensated, and parallelism may be increased.

Abstract: A read count circuit and a write count circuit, each for providing a count of data read from or written to, respectively, an asynchronous FIFO memory device. These circuits use read/write clock and read/write enable inputs, the selection of which depend on whether a read or write count is being provided. Essentially, the circuit comprises a shift register having a number of cascaded flip-flops, where the number of flip-flops is based on a ratio of one clock frequency to the other. An AND element at the output of each flip-flop AND's the output of the associated flip-flop with a read/write enable signal. A pulse generator at the output of each AND element synchronizes the outputs of the AND elements with the read/write clock. An adder then sums the outputs of the pulse generators. A counter increments with the adder output and decrements with a read/write enable signal, upon each read/write clock signal, thereby providing a read/write count output.

Abstract: In an array processing section, using data strings entered from input ports, a plurality of data processor elements execute predetermined operations while transferring data to each other, and output data strings of results of the operations from a plurality of output ports. A first data string converter converts data strings stored in a plurality of data storages of a data storage group into a placement suitable for the operations in the array processing section, and enters the converted data strings into the input ports of the array processing section. A second data string converter converts the data strings output from output ports of the array processing section into a placement to be stored in the plurality of data storages of the data storage group.

Abstract: A data storage system includes a plurality of non-volatile memory devices arranged in one or more sets, a main controller and one or more processors. The main controller is configured to accept commands from a host and to convert the commands into recipes. Each recipe includes a list of multiple memory operations to be performed sequentially in the non-volatile memory devices belonging to one of the sets. Each of the processors is associated with a respective set of the non-volatile memory devices, and is configured to receive one or more of the recipes from the main controller and to execute the memory operations specified in the received recipes in the non-volatile memory devices belonging to the respective set.

Abstract: The problem was that the high-impedance state of the difference between signals DQS and DQSB cannot be prevented from being brought in. With this invention, a first comparator circuit outputs a signal DQSIN representing the difference between DQS and DQSB after the coupling of input terminals to a terminal potential and from before the start timing of a preamble of the two signals. A second comparator circuit compares the level of DQS or DQSB with a reference voltage Vref and outputs a signal ODT_DET representing the result of the comparison. A gate circuit masks the signal DQSIN with a signal EW in a masking state. A control circuit identifies the start timing of the preamble based on ODT_DET, and sets the signal EW to the masking state before the start of the preamble and to an unmasking state from the start timing of the preamble.

Abstract: Techniques for implementing a data queuing and/or caching scheme for optimizing data storage are described herein. Data write requests are received and processed by at least queuing the requests and/or associated data for recording upon one or more data storage devices. The order within the queue, as well as the order in which the queued requests are serviced, may, in some embodiments, be optimized. The stored data are verified by determining the position of a write pointer implemented by the one or more data storage devices relative to the contents and/or position of the queued data requests.

Abstract: A serial memory may have memory arranged in a plurality of memory blocks, a serial interface for receiving a read instruction and associated memory address; and a controller configured to only store a plurality of most significant bits from each memory block which are accessed in parallel before an entire address has been received through the serial interface. The controller is further configured to stream out one of the plurality of most significant bits upon full reception of the memory address while retrieving the remaining bits from memory using the entire address and stream out the remaining bits after the most significant bits have been streamed out.

Abstract: Memory circuitry, a data processing apparatus and a method of storing data are disclosed. The memory circuitry comprises: a memory for storing the data; and control circuitry for controlling power consumption of the memory by controlling a rate of access to the memory such that an average access delay between adjacent accesses is maintained at or above a predetermined value; wherein the control circuitry is configured to determine a priority of an access request to the memory and to maintain the average access delay at or above the predetermined value by delaying at least some accesses from access requests having a lower priority for longer than at least some accesses from access requests having a higher priority.

Abstract: Data, normally read using a page-by page read process, can be recovered from memory cells connected to a broken word line by performing a sequential read process. To determine whether a word line is broken, both a page-by page read process and a sequential read process are performed. The results of both read processes are compared. If the number of mismatches between the two read processes is greater than a threshold, it is concluded that there is a broken word line.