Abstract: A memory device is disclosed, including a memory array and a selection circuit. At least one first faulty cell and at least one second faulty cell that are in the memory array store data corresponding to, respectively, first and second fields of a floating-point number. The selection circuit identifies the at least one first faulty cell and the at least one second faulty cell based on a priority of a cell replacement operation which indicates that a priority of the at least one first faulty cell is higher than that of the at least one second faulty cell. The selection circuit further outputs a fault address of the at least one first faulty cell to a redundancy analyzer circuit for replacing the at least one first faulty cell.

Abstract: According to an embodiment, a semiconductor memory device includes a memory cell, a first word line coupled between a control end of the memory cell and a first node, a resistance element coupled between the first node and a second node, a control circuit configured to output a voltage to the second node, a first switch coupled between the first node and a third node, a second switch coupled between the second node and the third node, and a comparator including an input end that receives a signal corresponding to a voltage of the third node.

Abstract: An arithmetic device and an electronic device having small power consumption is provided. An arithmetic device and an electronic device capable of high-speed operation is provided. An arithmetic device and an electronic device capable of suppressing heat generation is provided. The arithmetic device includes a first arithmetic portion and a second arithmetic portion. The first arithmetic portion includes a first CPU core and a second CPU core. The second arithmetic portion includes a first GPU core and a second GPU core. The CPU cores each have a power gating function and each include a first data retention circuit electrically connected to a flip-flop. The first GPU core includes a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits. The second GPU core includes a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit.

Abstract: Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.

Abstract: In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.

Abstract: A communications system includes: a control device; a standard proxy input/output circuit configured to control a standard electric device; and an extension proxy input/output circuit configured to control an extension electric device. The control device and the standard proxy input/output circuit are provided on one substrate, and the control device and the extension proxy input/output circuit are connected to each other via an electric wire.

Abstract: A controller determines, for each read operation, a mathematical model by using a) a set function of a read threshold voltage set among the plurality of read threshold voltages and b) a set checksum value; determines a polynomial regression model based on the mathematical model; determines a parameter set by using multiple computations between input and output matrices based on the polynomial regression model; and estimates a next read threshold voltage for a next read operation based on the parameter set. The controller computes mathematical operation algorithms to replace a normal multiplication operation, a normal division operation and a normal multiplication followed by division operation.

Abstract: An arithmetic device and an electronic device having small power consumption is provided. An arithmetic device and an electronic device capable of high-speed operation is provided. An arithmetic device and an electronic device capable of suppressing heat generation is provided. The arithmetic device includes a first arithmetic portion and a second arithmetic portion. The first arithmetic portion includes a first CPU core and a second CPU core. The second arithmetic portion includes a first GPU core and a second GPU core. The CPU cores each have a power gating function and each include a first data retention circuit electrically connected to a flip-flop. The first GPU core includes a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits. The second GPU core includes a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit.

Abstract: Embodiments of the disclosure provide a system, method, or computer readable medium for programming a target analog voltage range of an analog content addressable memory (aCAM) row. The method may comprise calculating a threshold current sufficient to switch a sense amplifier (SA) on and discharge a match line (ML) connected to a cell of the aCAM; and based on calculating the threshold current, programming a match threshold value by setting a memristor conductance in association with the target analog voltage range applied to a data line (DL) input. The target analog voltage range may comprise a target analog voltage range vector.

Abstract: Embodiments provide a scheme for estimating an optimal read threshold voltage using a deep neural network (DNN) with a reduced number of processing. A controller includes a combined neural network, which receives first and second cumulative distribution function (CDF) values, each CDF value corresponding to a program voltage (PV) level associated with a read operation on the cells. The combined neural network generates first and second connection vectors based on the first and second CDF values and first weight values, and estimates an optimal read threshold voltage based on the first and second connection vectors and second weight values.

Abstract: Systems and methods provide new circuits that increase aCAM precision by leveraging the concept of range segmenting to representationally store an analog voltage range across multiple aCAM cells/sub-circuits (here the representationally stored analog voltage range may correspond to a word entry). In this way, a circuit of the presently disclosed technology can increase precision (e.g., the number of programmable levels that can be used to store a word entry and/or the number of programmable levels that an input signal can be search against) linearly with each aCAM cell/sub-circuit added to the circuit. Accordingly, circuits of the presently disclosed technology can be used to carry out more complex computations than conventional aCAMs—and thus can be used in a wider range of computational applications.

Abstract: A method comprising receiving, at a memory sub-system from a host system, receiving, at one or more configuration parameters reflecting an expected type of use of the memory sub-system; receiving one or more environmental parameters of the memory sub-system, wherein the environmental parameters reflect characteristics of an environment of the memory sub-system; and selecting a programming operation parameter to be utilized by the memory sub-system based on the configuration parameters and environmental parameters.

Abstract: A power module, including a high-side switching element and a low-side switching element connected to form a half bridge circuit, a high-side drive circuit which drives the high-side switching element, a low-side drive circuit which drives the low-side switching element, and a high-side current detection circuit which detects a current of the high-side switching element. The high-side drive circuit includes a high-side variable delay circuit which adjusts, according to a value detected by the high-side current detection circuit, a length of a high-side delay time from a time when a signal is inputted to the high-side drive circuit to a time when the high-side switching element is driven.

Abstract: Examples described herein relate to a decision tree computation system in which a hardware accelerator for a decision tree is implemented in the form of an analog Content Addressable Memory (a-CAM) array. The hardware accelerator accesses a decision tree. The decision tree comprises of multiple paths and each path of the multiple paths includes a set of nodes. Each node of the decision tree is associated with a feature variable of multiple feature variables of the decision tree. The hardware accelerator combines multiple nodes among the set of nodes with a same feature variable into a combined single node. Wildcard values are replaced for feature variables not being evaluated in each path. Each combined single node associated with each feature variable is mapped to a corresponding column in the a-CAM array and the multiple paths of the decision tree to rows of the a-CAM array.

Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.

Abstract: An electronic device capable of efficiently recognizing a handwritten character is provided. The electronic device includes a first circuit, a display portion, and a touch sensor. The first circuit includes a neural network. The display portion includes a flexible display. The touch sensor has the function of outputting an input handwritten character as image information to the first circuit. The first circuit has the function of analyzing the image information and converting the image information into character information, and a function of displaying an image including the character information on the display portion. The analysis is performed by inference through the use of the neural network.

Abstract: An analog computing method includes the steps of: (a) generating a biasing current (IWi) using a constant gm bias circuit operating in the subthreshold region for ultra-low power consumption, wherein gm is generated by PMOS or NMOS transistors, the circuit including a switched capacitor resistor; and (b) multiplying the biasing current by an input voltage using a differential amplifier multiplication circuit to generate an analog voltage output (VOi). In one or more embodiments, the method is used in a vision application, where the biasing current represents a weight in a convolution filter and the input voltage represents a pixel voltage of an acquired image.

Abstract: A memory circuit for a print component including plurality of I/O pads, including a first analog pad and a second analog pad, to connect to a plurality of signal paths which communicate operating signals to the print component, including an analog signal path connected to the first analog pad and the second analog pad, the first analog pad electrically isolated from the second analog pad to interrupt the analog signal path to the print component. The memory circuit further includes a memory component to store memory values associated with the print component, and a control circuit to, in response to a sequence of operating signals received by the I/O pads representing a memory read, provide an analog signal to the analog pad to provide an analog electrical value at the analog pad representing stored memory values selected by the memory read.

Abstract: Aspects of the present disclosure provide apparatus, methods, processing systems, and computer readable mediums to enhance the functionality of directional repeaters (wireless devices that relay directional wireless signals). For example, by adding even limited capability to buffer digital samples, repeater functionality may be enhanced to provide better coverage and make more efficient use of time, frequency, and spatial resources. An example method generally includes receiving, from a base station, a configuration indicating how the wireless device is to process stored digital samples of a first radio frequency (RF) signal, receiving the first RF signal, wherein the receiving comprises generating the digital samples of the first RF signal, storing the digital samples, and processing the stored digital samples according to the configuration.

Abstract: Methods, systems, and devices for repair operation techniques are described. A memory device may detect a failure of a read operation associated with a physical row address of a memory die. The memory device may store information associated with the physical row address before performing a media management operation and after detecting the failure. Additionally or alternatively, the memory device may initiate a counter based on detecting the failure and may increment a value of the counter for each media management operation performed after detecting the failure. The memory device may send a command or other information to perform a repair operation for the physical row address. The memory device may determine the physical row address for the repair operation (e.g., despite media management operations) based on the stored information or the value of the counter, and may perform the repair operation on the physical row address.

Abstract: An image sensor device includes a digital pixel that includes a photo detector, a comparator, and a memory circuit, a pixel driver that controls the digital pixel, and a digital logic circuit that performs a digital signal processing operation on a digital signal output from the digital pixel. The photo detector and a first portion of the comparator are formed in a first semiconductor die, a second portion of the comparator, the memory circuit, and the pixel driver are formed in a second semiconductor die under the first semiconductor die, and the digital logic circuit is formed in a third semiconductor die under the second semiconductor die.

Abstract: Devices, systems and methods for improving the performance of a memory device are described. An example method includes obtaining a plurality of cell counts for each of a plurality of read voltages applied to the memory device, generating, based on the plurality of cell counts, a set of Gaussian models for a plurality of PV states corresponding to the plurality of read voltages, each of the set of Gaussian models comprising a mean parameter and a standard deviation parameter, determining, based on the set of Gaussian models, the mean parameter and the standard deviation parameter for each of the plurality of PV states, determining, based on the mean parameter and the standard deviation parameter for each of the plurality of PV states, a plurality of updated read voltages, and applying the plurality of updated read voltages to the memory device to retrieve information from the memory device.

Abstract: A system for processing a data array, such as transposing a matrix, includes a two-dimensional array of memory cells, such as FeFETs, each having an input end, an output end and a control end. The system also includes an input interface is adapted to supply signals indicative of a subset of the data array, such as a row of a matrix, and output control signals to the input ends of a selected column of the memory cells. The system further includes an output interface adapted to receive the data stored in the memory array from the output ends of a selected row of the memory cells. A method of processing a data array, such as transposing a matrix, include writing subsets of the data array to the memory array column-by-column, and reading from the memory cells, row-by-row.

Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output a reset signal, command/address signals and data. The second semiconductor device may be configured to enable a start signal and an oscillation signal based on the reset signal. The oscillation signal starts to oscillate in response to the reset signal.

Abstract: A semiconductor memory device includes a first data input/output (I/O) pad, an X-ray detector and a second data I/O pad. The first data I/O pad receives a test signal. The X-ray detector is connected to the first data I/O pad, includes a bipolar junction transistor (BJT) in which a voltage between an input end and an output end changes according to a cumulative X-ray dosage to the semiconductor memory device, and generates a test result signal indicating the voltage between the input and output ends of the BJT based on the test signal. The second data I/O pad is connected to the X-ray detector and outputs the test result signal.

Abstract: A memory system includes a memory device, and a controller suitable for correcting errors included in request data read through a first read operation performed by the memory device in response to a read command provided from a host, and providing corrected data to the host, wherein the controller includes a first read processor suitable for performing the first read operation, a second read processor suitable for performing a second read operation, a third read processor suitable for performing a third read operation, and a fourth read processor suitable for detecting an optimal read voltage through an e-boost operation and performing a fourth read operation.

Abstract: A memory controller controlling a semiconductor memory device, the memory controller may comprises a host interface configured to receive a write request, from a host, to store data in the semiconductor memory device, a processor configured to generate a program command according to a type of the write request, a memory interface configured to provide the program command to the semiconductor memory device, wherein the type of the write request includes a first type write request and a second type write request, and wherein the first type write request requires faster write completion response than the second type write request.

Abstract: Disclosed are systems and methods of dynamically calibrating a memory control voltage more accurately. According to disclosed implementations, a memory control voltage such as Vpass or Vwlrv may be calibrated during memory operation as a function of the change in slope of total string current, even during increase in the wordline voltage. In one exemplary method, the wordlines are increased in sequence from a start voltage to an end voltage in steps, slope change is measured at every step, the measured slope change is compared against a threshold, and an adjusted memory control voltage is determined as a function of a wordline voltage at which the change in slope reaches the threshold. As such, memory control voltage may be determined and dynamically calibrated with less sensitivity to operating parameters such as temperature, pattern, and/or time of programming.

Abstract: A voltage adjusting method, a memory controlling circuit unit and a memory storage device are provided. The method includes: reading a first physical programming unit in a first physical programming unit group to obtain first data; correcting the first data according to a first error check and correction code corresponding to the first data to obtain first corrected data; reading a second physical programming unit in the first physical programming unit group to obtain second data; and adjusting a first read voltage for reading a first memory cell to a second read voltage according to the first data, the first corrected data, and the second data.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for model based configuration parameter management. An association module is configured to group a plurality of erase blocks of a non-volatile memory medium based on an amount of time since data has been written to the plurality of erase blocks. A read module is configured to sample data of at least two word lines from at least one erase block from each of a plurality of groups of erase blocks. A configuration parameter module is configured to determine different read voltage thresholds for different word lines of groups of erase blocks using different read voltage threshold models for different groups based on sampled data.

Abstract: To detect events in an audio stream, frames of an audio signal (e.g., frames generated by a codec for a voice call or music stream) are received. Based on information in the frames, an index is used to look up an entry in a table associated with the codec. Each entry in the table indicates a likelihood that a frame matches a sound model element. The likelihood is used in the search for a sound bite, word, and/or phrase in the audio signal. The process of dynamic programming is used to find the combined likelihood for a match of the word, phrase, and/or sound bite to a region of the audio stream. Upon detection of the word, phrase, and/or sound bite in the audio stream, an event is generated, such as, notifying a person or logging the event in a database.

Abstract: A circuit includes: a first circuit stage configured to sample a differential input signal at a first logic state of a sampling clock and regenerate the sampled differential input signal at a second logic state of the sampling clock to output a first regenerated differential signal; a second circuit stage configured to amplify the first regenerated differential signal at the second logic state of the sampling clock to output an amplified differential signal; and a third circuit stage configured to regenerate the amplified differential signal at the first logic state of the sampling clock to output a second regenerated differential signal.

Abstract: There is provided a method for setting read thresholds to be used for reading multiple bits per cell flash memory cells, the method may include reading, by a read circuit, the flash memory cells using a set of current read thresholds to provide current read results; finding, by an error evaluation circuit, current read errors direction statistics associated with the current read results; determining multiple read threshold changes based upon the current read error direction statistics, without determining a contribution of each current read threshold to the current read error direction statistics; and altering multiple current read thresholds, by the multiple read threshold updates, to provide a set of next read thresholds.

Abstract: The present invention provides an analog memory cell circuit for the LTPS TFT-LCD. The circuit comprises the first transistor, second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the capacitor. It comprises a plurality of operation period, wherein the transistors are controlled in accordance with the first scan signal, the second scan signal, and the third scan signal, the output signal is output in the opposite to the output jack.

Abstract: Disclosed is a system and method for reading a flash memory cell with an adjusted read level. A current read level is set to a new read level associated with increasing a first error rate to decrease a second error rate. The first error rate is associated with determining that the most significant bit of the flash memory cell is a binary 1 and the second error rate is associated with determining that the most significant bit is a binary 0. On reading the memory cell, a probability value is generated for the most significant bit, the probability being higher if the bit is equivalent to a binary 0 than if the bit is equivalent to a binary 1.

Abstract: A method for data storage includes defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not reduce all of the interference reduced by the first programming scheme. One of the first and second programming schemes is selected based on a criterion defined with respect to the analog memory cells. Data is stored in the group of the analog memory cells using the selected programming scheme.

Abstract: Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory cell and driving a second signal line and a word line; a driver circuit selecting any of writing potentials and outputting it to a first signal line; a reading circuit comparing a potential of a bit line and a reference potential; and a potential generating circuit generating the writing potential and the reference potential. One of the memory cells includes: a first transistor connected to the bit line and a source line; a second transistor connected to the first and second signal line; and a third transistor connected to the word line, bit line, and source line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor is connected to one of source and drain electrodes of the second transistor.

Abstract: A method for data storage includes defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not reduce all of the interference reduced by the first programming scheme. One of the first and second programming schemes is selected based on a criterion defined with respect to the analog memory cells. Data is stored in the group of the analog memory cells using the selected programming scheme.

Abstract: A method of forming a circuitry includes providing a substrate comprising a plurality of die. Each die includes a plurality of resistive random access memory (RRAM) storage cells. The method further includes concurrently initializing substantially all of the RRAM storage cells on the same wafer. Initializing can include applying a voltage potential across the RRAM storage cells.

Abstract: A data storage system includes a plurality of non-volatile memory devices arranged in one or more sets, a main controller and one or more processors. The main controller is configured to accept commands from a host and to convert the commands into recipes. Each recipe includes a list of multiple memory operations to be performed sequentially in the non-volatile memory devices belonging to one of the sets. Each of the processors is associated with a respective set of the non-volatile memory devices, and is configured to receive one or more of the recipes from the main controller and to execute the memory operations specified in the received recipes in the non-volatile memory devices belonging to the respective set.

Abstract: An analog associative memory, which includes an array of coupled voltage or current controlled oscillators, matches patterns based on shifting frequencies away from a center frequency of the oscillators. Test and memorized patterns are programmed into the oscillators by varying the voltage or current that controls the oscillators. Matching patterns result in smaller shifts of frequencies and enable synchronization of oscillators. Non-matching patterns result in larger shifts and preclude synchronization of oscillators. The patterns may each include binary data and the pattern matching may be based on discrete shifts. The patterns may each include grayscale data and the pattern matching may be based on continuously-varied shifts. Other embodiments are described herein.

Abstract: A method includes, in an array of analog memory cells that are arranged in rows associated with respective word lines, reading a first group of the memory cells in a selected word line, including one or more memory cells that store a status of at least one word line in the array other than the selected word line. A readout configuration for a second group of the memory cells is set responsively to the read status. The second group of the memory cells is read using the readout configuration.

Abstract: A method for data storage includes defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not reduce all of the interference reduced by the first programming scheme. One of the first and second programming schemes is selected based on a criterion defined with respect to the analog memory cells. Data is stored in the group of the analog memory cells using the selected programming scheme.

Abstract: The present technology relaxes the precision (or full data-correctness-guarantees) requirements in memory operations, such as writing or reading, of MLC memories so that an application may write and read a digital data value as an approximate value. Types of MLCs include Flash MLC and MLC Phase Change Memory (PCM) as well as other resistive technologies. Many software applications may not need the accuracy or precision typically used to store and read data values. For example, an application may render an image on a relatively low resolution display and may not need an accurate data value for each pixel. By relaxing the precision or correctness requirements is a memory operation, MLC memories may have increased performance, lifetime, density, and/or energy efficiency.

Abstract: A method for data storage includes providing at least first and second readout schemes for reading storage values from a group of analog memory cells that are connected to respective bit lines. The first readout scheme reads the storage values using a first bit line charging configuration having a first sense time, and the second readout scheme reads the storage values using a second bit line charging configuration having a second sense time, shorter than the first sense time. A condition is evaluated with respect to a read operation that is to be performed over a group of the memory cells. One of the first and second readout schemes is selected responsively to the evaluated condition. The storage values are read from the group of the memory cells using the selected readout scheme.

Abstract: A method for data storage includes defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not reduce all of the interference reduced by the first programming scheme. One of the first and second programming schemes is selected based on a criterion defined with respect to the analog memory cells. Data is stored in the group of the analog memory cells using the selected programming scheme.

Abstract: A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer has a magnetic anisotropy, at least a portion of which is a biaxial anisotropy. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

Abstract: A method includes performing a read operation that reads data from a group of analog memory cells using at least one read threshold, to produce readout results. A detection is made that the read threshold is set in a restricted range that causes the readout results not to reflect the read threshold. The data is reproduced from the group of the memory cells while compensating for the read threshold that is set in the restricted range.

Abstract: Memory cell structures for phase change memory. An example memory cell structure comprising includes a bottom electrode comprised of electrically conducting material, and phase change material disposed above the bottom electrode. A layer of thermally insulating material is disposed, at least partially, between the bottom electrode and the phase change material. The thermally insulating material is comprised of Tantalum Oxide. A top electrode is comprised of electrically conducting material.

Abstract: A method for data storage includes defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not reduce all of the interference reduced by the first programming scheme. One of the first and second programming schemes is selected based on a criterion defined with respect to the analog memory cells. Data is stored in the group of the analog memory cells using the selected programming scheme.