Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. In some examples, the nodes of the non-linear input capacitors are conditioned once in a while to preserve function of the multi-input majority gates.

Abstract: A class of complex logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. At least one input to an individual multi-input majority gate is a fixed input. Other inputs are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node, which provides a majority function of the inputs. The summing node is coupled to a CMOS logic. Leakage through the capacitors is configured such that capacitors of a majority gate have substantially equal leakage, and this leakage has a I-V behavior which is symmetric. As such, reset device(s) on the summing node are not used. The non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels, which reduces the high leakage problem faced from majority gates that use linear input capacitors.

Abstract: A class of complex logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. At least one input to an individual multi-input majority gate is a fixed input. Other inputs are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node, which provides a majority function of the inputs. The summing node is coupled to a CMOS logic. Leakage through the capacitors is configured such that capacitors of a majority gate have substantially equal leakage, and this leakage has a I-V behavior which is symmetric. As such, reset device(s) on the summing node are not used. The non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels, which reduces the high leakage problem faced from majority gates that use linear input capacitors.

Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. In some examples, the nodes of the non-linear input capacitors are conditioned once in a while to preserve function of the multi-input majority gates.

Abstract: One embodiment of the present invention is a parallel processing unit (PPU) that includes one or more streaming multiprocessors (SMs) and implements a selective fault-stalling pipeline. Upon detecting a memory access fault associated with an operation executing on a particular SM, a replay unit in the selective fault-stalling pipeline considers the operation as a faulting operation. Subsequently, instead of notifying the SM of the memory access fault, the replay unit recirculates the operation—reinserting the operation into the selective fault-stalling pipeline. Recirculating faulting operations in such a fashion enables the SM to execute other operation while the replay unit stalls the faulting request until the associated access fault is resolved. Advantageously, the overall performance of the PPU is improved compared to conventional PPUs that, upon detecting a memory access fault, cancel the associated operation and subsequent operations.

Abstract: System and method for performing correlation analysis. A program that includes multiple program structures and one or more data objects is stored. Each data object is shared by at least two of the program structures. For each program structure, decomposition effects on each of the data objects shared by the program structure resulting from each of a respective one or more optimizing transforms applied to the program structure are analyzed. One or more groups of correlated structures are determined based on the analyzing. Each group includes two or more program structures that share at least one data object, and at least one optimizing transform that is compatible with respect to the two or more program structures and the shared data object. For at least one group, the at least one optimizing transform is usable to transform the two or more program structures to meet a specified optimization objective.

Abstract: An imaging optical system has a plurality of mirrors. These image an object field in an object plane into an image field in an image plane. In the imaging optical system, the ratio of a maximum angle of incidence of imaging light) on reflection surfaces of the mirrors and an image-side numerical aperture of the imaging optical system is less than 33.8°. This can result in an imaging optical system which offers good conditions for a reflective coating of the mirror, with which a low reflection loss can be achieved for imaging light when passing through the imaging optical system, in particular even at wavelengths in the EUV range of less than 10 nm.

Abstract: The memory system has data lines for transmitting data between memory components and at least one control unit. The memory system is a distributed system with at least one central control unit and at least one group control unit, the group control unit having at least one first data line for connecting the group control unit to the central control unit, and second data lines for connecting a group of memory components to the group control unit.

Abstract: A non-volatile analog memory contains multiple recording pipelines for sampling and storing values representing an analog signal and/or multiple playback pipelines for playing a recorded signal. Each recording pipeline includes a sample-and-hold circuit and a write circuit coupled to a memory array associated with that pipeline and is capable of write operations that overlap write operations of other recording pipelines. Each playback pipeline includes a read circuit and a sample-and-hold circuit coupled to an associated memory array and is capable of read operations that overlap read operations of other playback pipelines. The pipelines operate sequentially during recording or playback, and the number of pipelines is selected according to a desired sampling frequency. One embodiment provides a modular integrated circuit architecture which allows a user selected number of ICs to be connected together to handle a desired sampling frequency.

Abstract: A high performance fault tolerant orthogonal shuffle memory comprising a plurality of memory cells arranged to form a two-dimensional array of rows and columns. Each memory cell includes a data store element for storing data and a multi-state data transmission element to provide access to the data stored in the data store element. Each memory cell has the dual function of storing and transmitting (i.e. shifting) data. The memory cell array is coupled to first and second registers and a shuffle signal generator. In operation, data is shuffled column by column through the array, such that only two columns of memory cells are activated at any time. The shuffle memory herein disclosed may form subarrays of each of a data storage array and a redundancy storage array that are coupled to an improved error detector and corrector to form a high performance fault tolerant orthogonal memory system.

Abstract: A memory device for storing analog or multilevel data which is easy to produce and of a small scale. The memory device according to the present invention circulates data between a plurality of linear CCD arrays which store data as electrical charges, allows high speed memory access by reading and writing data through cache memory which stores row addresses corresponding to CCD arrays, and includes an address register for registering the address of cache memory data.

Abstract: The present invention provides a memory device for preventing data circulating on a plural number of linear CCD array from being corrupted, for accessing data at a high speed, and for reducing the device's electric power consumption.A memory device according to this invention downsizes a block of a memory cell by circulating data on a plural number of linear CCD arrays which are for storing data by an electric charge on a cell and keeping analog data, which sets a clock generation means for circulating data on all arrays and another clock generation means for circulating at a high speed only the array loops having necessary data.

Abstract: An all-optical circulating shift register encodes a received optical clock signal with a value derived from an encoded optical signal received at a control port thereof. A data input to the shift register is used to modify an encoded optical signal. The resulting encoded clock signal, appearing at an output port, is coupled back to the control port. The shift register uses the encoded clock signal at the control port to encode a subsequently-received clock signal. In one embodiment, the optical shift register is implemented using a Sagnac switch having a feedback path coupled between an output port and a control port of the Sagnac switch.

Abstract: An optical shift register constructed from at least two optical memory cells connected in cascade, each memory cell having an optical combiner, a 1.times.2 optical switch, a clock, and an optical amplifier, all connected by optical fibers. Each memory cell in the sequence is connected to the next sequential cell by an optical fiber from its output port to the input port of the next sequential cell. The input port of the first optical memory cell serves as the input to the shift register. The output port of the last sequential optical memory cell serves as the output port of the shift register. Each cell is controlled by a clock, all clocks operating at the same rate, but each out of phase with the clock in the next sequential cell. Control signals are provided by said clocks to shift optical pulses from one cell to the next for the enter-shift-exit cycle of the shift register.

Abstract: Multiaccess memory modules are each connected by means of a bus to a system ddress multiplexer and to a system data multiplexer/demultiplexer. Each module includes a multiaccess memory connected to the system address multiplexer through a component address demultiplexer and a single bus for being addressed. Each multiaccess memory is also connected to the system data multiplexer/demultiplexer through a component data multiplexer/demultiplexer and a single bus for reading or sensing the memory and writing data into the memory. The memory cells of the multiaccess memory components consist of capacitor storage cells, also known as metal oxide silicon (semiconductor) (MOS) capacitors.

Abstract: A recirculating loop memory array is disclosed adapted for the parallel as well as serial fetching and storing of data while requiring only a single input and single output data terminal. Each loop of the array is provided with a shift register stage for parallel data accessing. A particular recirculating bit in all of the loops can be fetched in parallel into their respective shift register stages and, conversely, the bits stored in the shift register stages can be loaded in parallel into predetermined recirculating bits of their respective loops. The shift register is operated at high speed so that it may be completely loaded or unloaded during the interval between successive steppings of the loops.

Abstract: A circulating shift register memory, particularly adaptable to charge coupled device technology, wherein a plurality of circulating shift registers are arranged to provide a matrix of data bits accessible at a common data front. Address counter circuitry cooperating with the register clocking circuits selects a particular bit location on the data front for each shift of the shift registers. Depending upon a mode signal and beginning address from a host system, the address counter circuitry provides successive accesses in predetermined patterns, for example along a row, column or diagonal of the bit matrix.

Abstract: A storage system stores information in the form of records each having a key portion and a data portion. These records are stored in key order. The records are stored in a shift register, preferably cyclic, access to the shift register being achieved through one or more ports in it. At each port there is a comparator for comparing a desired key with the keys of the stored records as they pass that port. On a successful comparison, a record may be read, extracted, or written. The system can cope with missing or duplicated keys, and records can be retrieved in sequential key order by simple sequential readout.

Abstract: This disclosure relates to fast access CCD memory organizations with parallel loops or tracks wherein the total number of data bits which can be stored on a single calculator chip is dependent on the overhead circuitry consisting of a number of refresh amplifiers and various switches required to switch the stored data from a storage track to a read/write location and also on the number of refresh amplifiers as well as control circuitry required for distribution of clock pulses to the respective storage tracks. As the number of switches and refresh amplifiers is increased, so is the total area required for storage bits. As the number of clock switches is increased, the power dissipation for the semiconductor chip is decreased. As the number of refresh amplifiers is increased, the access time and total service time is decreased. A number of different optimum memory organizations are disclosed.

Abstract: A bidirectional serial-parallel-serial charge-coupled device wherein each serial section is both an input register and an output register, and serial streams of charge packets flow simultaneously in opposite directions in the parallel section. Odd data bits of a serial input stream flow into a first serial register and then through the parallel section in one direction and then out of the second serial register, while concurrently the even data bits flow into the second serial register and then through the parallel section in the opposite direction and then out of the first serial register. The data transfer rate is thereby substantially doubled.

Abstract: This disclosure relates to fast access CCD memory organizations with parallel loops or tracks wherein the total number of data bits which can be stored on a single calculator chip is dependent on the overhead circuitry consisting of a number of refresh amplifiers and various switches required to switch the stored data from a storage track to a read/write location and also on the number of refresh amplifiers as well as control circuitry required for distribution of clock pulses to the respective storage tracks. As the number of switches and refresh amplifiers is increased, so is the total area required for storage bits. As the number of clock switches is increased, the power dissipation for the semiconductor chip is decreased. As the number of refresh amplifiers is increased, the access time and total service time is decreased. A number of different optimum memory organizations are disclosed.

Abstract: Insulated gate field effect transistor charge regenerator amplifiers respectively cross-couple the output regions of a pair of two-phase CCD structures with the input regions of those structures. Each amplifier senses the level of binary data charge packets from the output region of one of the shift register structures and in response thereto applies a regenerated and inverted binary data charge packet to the input region of the other shift register structure. One of the amplifiers includes logic gating for inputting and outputting data into and from the shift register structure.A charge regenerator for a two-phase CCD structure comprising first and second shift registers. The charge regenerator comprises a source follower amplifier including a driver transistor, a load transistor and a positive feedback transistor connected between the gate and source of the driver transistor.

Abstract: This disclosure relates to fast access CCD memory organizations with parallel loops or tracks wherein the total number of data bits which can be stored on a single calculator chip is dependent on the overhead circuitry consisting of a number of refresh amplifiers and various switches required to switch the stored data from a storage track to a read/write location and also on the number of refresh amplifiers as well as control circuitry required for distribution of clock pulses to the respective storage tracks. As the number of switches and refresh amplifiers is increased, so is the total area required for storage bits. As the number of clock switches is increased, the power dissipation for the semiconductor chip is decreased. As the number of refresh amplifiers is increased, the access time and total service time is decreased. A number of different optimum memory organizations are disclosed.

Abstract: The invention provides a random access memory which consists of a plurality of recirculating sub-memories each having a fixed number of cells for volatile information storage and a further cell, also for volatile information storage, which is connected to the output thereof. The cells may be constructed according to LSI technique. Under the control of a circulating counter, each further cell is connected to an output of a rewrite amplifier which is connected in the recirculating loop of a sub-memory. The information of the further cell is accessible at random by a selection device and is regenerated once per cycle of the sub-memory. Thus, an advantageous compromise is obtained between the features of serially operating memories and random access memories, without an expensive additional buffer being required.

Abstract: This disclosure relates to error correcting circuits and methods employed thereby for shift register type memories which are formed of a plurality of loops that may be accessed in parallel. Such circuitry is designed to detect when the output of a given loop or shift register becomes a series of ones or a series of zeros which conditions indicate burst mode error. The data bit corresponding to the loop or shift register producing the error is then corrected by complementation.

Abstract: A method and apparatus for transferring digital data between a mass memory and a random access memory. The mass memory has a plurality of memory loops, each having a plurality of memory cells, and a read/write device which either outputs data from the memory cells or inputs data to the memory cells. Each memory cell is identified by an address that specifies its place in the loop sequence starting from a reference cell. A loop position counter is set at zero when the reference cell of the selected memory loop is at the read/write device. The loop position counter is advanced by one count each time the next memory cell in the sequence is moved into operative relationship with the read/write device. Transfer of data between the mass memory and the random access memory is accomplished without any delay under the control of a random access memory address counter which is synchronized with the loop position counter.