Abstract: A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET, and a third FET, and a load resistor connected to a drain of the third FET.

Abstract: The apparatus described herein may comprise a first set of transistors, including a first transistor and a second transistor, and a second set of transistors, including a third transistor and a fourth transistor. Gates of the first and second transistors may be coupled to a first signal and a second signal, respectively, each indicating whether a corresponding one of a first supply voltage and a second supply voltage reaches a first threshold voltage or a second threshold voltage to power on a first circuit or a second circuit of a memory device. Gates of the third and fourth transistors may be coupled to a first inverted version of the first signal and a second inverted version of the second signal, respectively. An outcome signal of the second set of transistors may indicate a power-on state of the memory device responsive to power states of the first and second signals.

Abstract: The apparatus described herein may comprise a first set of transistors, including a first transistor and a second transistor, and a second set of transistors, including a third transistor and a fourth transistor. Gates of the first and second transistors may be coupled to a first signal and a second signal, respectively, each indicating whether a corresponding one of a first supply voltage and a second supply voltage reaches a first threshold voltage or a second threshold voltage to power on a first circuit or a second circuit of a memory device. Gates of the third and fourth transistors may be coupled to a first inverted version of the first signal and a second inverted version of the second signal, respectively. An outcome signal of the second set of transistors may indicate a power-on state of the memory device responsive to power states of the first and second signals.

Abstract: The present invention is directed to an electrical wiring device having a body and a cover coupled to the body including a receptacle face structure which forms an interior region with at least one reflective surface. At least one light emitting device is disposed in the interior region which is configured to emit illumination into at least one neutral opening and a hot opening.

Abstract: There is disclosed a static random access memory (SRAM) device that stores an embedded program that is accessible when the SRAM device is powered up. The SRAM device comprises a plurality of storage cells, each of the storage cells comprises a data latch having an input and an output, wherein the data latch comprises a) a first inverter having an input coupled to the first I/O line and an output coupled to the second I/O line, and b) a second inverter having an input coupled to the second I/O line and an output coupled to the first I/O line. The storage cell also comprises a biasing circuit that forces at least one of the first and second I/O lines to a known logic state when power is applied to the SRAM device. The known logic state comprises one bit in the embedded program.

Abstract: Reducing leakage current when a circuit contains a series of CMOS transistors. The probability that each input signal (connecting to the gate terminal of the corresponding CMOS transistor) will be at a logical value which turns off the corresponding CMOS transistor is determined. A CMOS transistor with a high threshold voltage may be connected to receive an input signal with a high probability to reduce the aggregate leakage current in the circuit. The approach may be used in any environments such as synthesis tools and also manual design methodologies.

Abstract: A ternary CAM cell includes a main memory cell, a mask memory cell, a match line, a mask circuit, and a comparison circuit, where the main memory cell is enabled to a wordline to store data, and the mask memory cell enabled to a wordline to store mask data, data transferred to/from the main memory cell is loaded on a bitline pair, and mask data transferred to a mask memory cell is loaded on a mask bitline pair, comparison data is loaded on a comparison signal line pair, while the mask circuit is coupled between the match line and the mask memory cell to receive the comparison data, and the comparison circuit is coupled between the mask circuit and a ground voltage and includes a pair of transistors coupled to a comparison signal line pair and a pair of match transistors coupled to the data of the main memory cell such that, although the voltage level of the comparison data is lowered, a low voltage operation characteristic is excellent, the capacitive loadings of comparison signal lines are constantly maintai

Abstract: An array of dynamic memory cells and method for programming that array with initial information, as well as a disk drive system incorporating such an array, are disclosed. The array includes dynamic memory cells formed on an integrated circuit substrate. The array is modified by a programming step to contain nonvolatile initial information which may be retrieved immediately following a reset sequence. The array includes storage cells arranged as a matrix of bit line columns and row selects, each cell including a pass transistor having a predetermined threshold voltage characteristic Vth and being associated with a storage capacitor. Predetermined ones of the pass transistors are modified by a programming step, either during or following fabrication, so as to have a different predetermined threshold voltage characteristic Vthm, so that the array is comprised of unmodified cells and modified cells in a manner defining nonvolatile initial information in the array.

Abstract: A frame conversion circuit for changing data with different speeds to the same speed to thereby obtain data of the same frame length is provided with an initial value inputting circuit for writing an arbitrary initial value into a memory at each address each time data is sequentially read out according to a read address signal from the memory. Therefore, no error is produced in a sign bit check and the possibility of occurrence of erroneous synchronization is minimized. The initial value inputting circuit may be implemented using a plurality of pull-up resistors connected to a data bus.

Abstract: Initial data and/or control bits of registers within a digital integrated circuit are simultaneously loaded from localized non-volatile memory cells provided as part of the circuit. Such loading is accomplished each time the circuit is initialized, such as when power is first turned on to a system in which the circuit is a part. An important use of this technique is with a computer peripheral circuit chip such as a serial communications controller.

Abstract: Initial data and/or control bits of registers within a digital integrated circuit are loaded from a non-volatile and/or read-only memory provided as part of the circuit. Such loading is accomplished each time the circuit is initialized, such as when power is first turned on to a system in which the circuit is a part. An important use of this technique is with a computer peripheral circuit chip such as a serial communications controller.

Abstract: A five transistor memory cell that can be reliably read and written from a single data line. The cell includes two inverters and a pass transistor. The cell read/write circuitry includes an address supply voltage source which is maintained at a first level during write and at a second level during read, selected to reduce read disturbance. The memory cell read circuitry includes a circuit for precharging the cell data line prior to reading. The state of the memory cell is continuously available at output nodes to control other circuitry even during the read operation. Selective doping of the pull-up transistors of the inverters in the memory cell controls the initial state of the memory cell after the memory cell is powered up.

Abstract: A semiconductor nonvolatile memory device includes a static type RAM constituted by a flip-flop circuit having a pair of loads, each load being supplied by separate power sources. An electrically erasable programmable ROM is constituted by a nonvolatile memory transistor operatively connected to the flip-flop circuit. A control circuit controls the supply timing of each of the separate power sources when data stored in the nonvolatile memory transistor is recalled to the flip-flop circuit. In the recall, the supply timing of each of the separate power sources is determined in such a way that the flip-flop circuit is set so as to invert from one state to the other corresponding to the ON/OFF state of the nonvolatile memory transistor.

Abstract: A memory cell which includes a pair of cross-coupled CMOS inverters. Each inverter has a capacitor coupled from its output to either the supply voltage or ground potential. One inverter has a capacitor coupled from its output to a voltage supply terminal and the other inverter has a capacitor coupled from its output to a ground terminal. Upon the application of power to the memory cell, the output of each inverter of the pair assumes a predetermined logic state thereby preventing dc current flow in either side of the cross coupled pair. In addition to providing for reduced power consumption, the selective cell assymetry provided makes possible a random access memory device that stores a fixed program at power up.

Abstract: A semiconductor memory device provided with an improved system for detecting an address of a defective column or row of memory cells replaced by a redundant column or row of memory cells through an output port comprises normal memory cells, at least one redundant memory cell, a power-on detection for generating a detection signal when a power supply to the memory circuit is switched on, a first circuit for initializing the normal memory cells at a first logic state in response to the detection signal, and a second circuit for initializing the redundant memory cell at a second logic state different from the first logic state in response to the detection signal.

Abstract: A compound semiconductor memory device having a redundancy configuration is disclosed. A fuse element to reject and replace a defective word line series is formed between a load transistor and a power voltage line in the primary decoder, and the word line is connected to the decoder without fuse element.

Abstract: A semiconductor memory device determines the level of a select control signal, according to the level of drive signals for two systems as generated in the preceding access cycle, and the level of the least significant bit of an address to fetch data in a desired serial access cycle. In accordance with this select signal, a select circuit selects one of the drive signals as generated by drive signal generating circuits, and supplies the selected signal to two data selecting/fetching systems. The function of this select circuit allows one of the two data selecting/fetching systems to first start the data access operation.

Abstract: A selectively definable semiconductor device is provided. In one form, a composite gate array includes a plurality of logic dedicated general purpose cell regions and a plurality of function dedicated cell regions each of which is disposed between the two corresponding ones of the plurality of logic dedicated general purpose cell regions, whereby each of the cell regions may be used as an interconnection region selectively. In another form, a semiconductor memory device which may be selectively defined as a ROM or a RAM by a metalization process is provided.

Abstract: In a CMOS FET IC element including at least one pair of transistors with connected drains, one an N-channel MOSFET and one a P-channel MOSFET, the N-channel MOSFET having a first threshold voltage controlled by the implantation of an ion, and the P-channel MOSFET having a second threshold voltage control are implanted with the same type of ion, so that one of the pair of transistors, either the N-channel MOSFET or the P-channel MOSFET is of a type that is normally ON, and the other MOSFET is of a type that is normally OFF with any gate voltage between the two voltages supplied to their sources.

Abstract: Circuitry, including a non-volatile dynamic random access memory cell, a sense amplifier and a data latch affords non-destructive accessing and comparison of the data stored within the volatile and non-volatile portion of the memory cell. In certain applications, it is desirable to restore the volatile data to the volatile portion of the memory cell, and the circuitry also provides a path for such restoration.

Abstract: A circuit constructed in accordance with this invention includes means for asynchronously forcing a flip-flop (70) or a register to a programmable logical state in response to an initialization input signal (I). In one embodiment, a D-type flip-flop (70) is provided having data input terminal (71), a clock input terminal (77), a data output terminal (103), an initialization input terminal (41), and a programming input terminal (11). When an initialization input signal I is received, a predefined output signal is immediately placed on the data output terminal (103). The predefined output signal is defined by the status of a fuse (13), which is opened, if desired, via the programming input terminal (11). When an initialization input signal is not received, the flip-flop (70) operates as a normal D-type flip-flop.

Abstract: The cell is realized according to a bistable structure which includes a non-volatile memory element. During the normal operation the structure operates as a static RAM cell with the non-volatile element excluded from the circuit. In case of turn-off of the supply line or after suitable control signals, a particular circuit arrangement allows to execute the programming operation of the non-volatile element, that is the information storage, without current absorption. At the turn-on, the automatic reinstatement of the stored information occurs.

Abstract: A memory device is disclosed which is automatically and stably set to a predetermined logic state upon the application of power thereto. The memory device comprises a flip-flop having first and second cross-connection points, a state setting transistor coupled between the second cross-connection point and a reference voltage terminal, a voltage detection circuit for detecting the value of a power supply voltage, and a reset circuit responsive to an output signal of the detection circuit for controlling the state setting transistor.

Abstract: A CMOS circuit is disclosed which has a latent image feature for application in FET memory arrays for writable read only storage applications. A four device cross-coupled CMOS circuit is formed with minimum real estate area, so as to allow for wiring level programming into a preconditioned binary one or zero state. The preconditioned circuit will assume a preselected binary state when power is turned on. Thereafter, the circuit can be accessed for normal binary one and zero selective storage without a significant diminution in its operating characteristics, when compared with conventional CMOS cross-coupled storage circuits.

Abstract: A microprocessor includes an internal data memory, made up of a plurality of memory cells, each of which includes first and second inverter circuits. In selected memory cells, the logic state of the cell is predetermined upon initiation of the power supply by arranging the inverters of each cell such that they have different transistor ratios. The difference in ratio may be effected by altering the channel width or length of one of the constituent transistors of the respective inverter circuit.

Abstract: An I.sup.2 L type nonvolatile memory of this invention has a structure wherein a floating gate is disposed through an insulating film on the surface of a semiconductor layer in the vicinity of a base region of an NPN transistor in an I.sup.2 L. The I.sup.2 L type nonvolatile memory of this invention controls current to flow through the base region of the NPN transistor of the I.sup.2 L, by means of charges to be stored in the floating gate. That is, the collector output current of the NPN transistor of the I.sup.2 L is modulated in dependence on the presence or absence of a channel underneath the floating gate as is generated depending on the presence or absence of charges within the floating gate and the polarity of the charges. As a result, the variation of the base current appears as an output signal at a collector terminal of the NPN transistor of the I.sup.2 L, and data stored in the floating gate can be read out.

Abstract: An asymmetric RAM cell is disclosed which will have a predictable initial storage state when pulsed drain voltage is turned on and yet after the initial turn-on interval, will operate in a symmetric fashion storing either binary ones or zeros. Thus, an initial prestored set of information can be permanently provided in a memory array made up of such cells, by orienting each individual cell at the time of manufacture so as to selectively represent either a binary one or zero. This is illustrated in the FIGURE where the upper cell has a first state by virtue of its orientation and the lower cell has a second, opposite state by virtue of its relative opposite orientation. When the array is turned on, the upper cell will have the opposite binary state from the lower cell. Thereafter, each cell can be respectively switched for storing ones and zeros in a normal RAM operating mode.

Abstract: A nonvolatile memory cell employing a bistable RAM cell and an electrically erasable and electrically programmable (E.sup.2) floating gate memory device. The E.sup.2 cell is coupled between one of the input/output nodes of the RAM cell and a clear/recall line. The loads of the RAM cell are imbalanced, causing this cell to assume a predetermined state. If the E.sup.2 cell is in its erased state after a storage cycle, the potential on the store/recall line causes the RAM cell to assume its other stable state on recall.

Abstract: A monolithic static memory cell has two cross-coupled inverters each comprised of a series connection of a field effect switching transistor and a load element designed as a field effect transistor. The field effect transistors forming the load elements have their channel resistances of different values. A gate insulating layer of one of the load element field effect transistors has its charge state altered, preferably by electron beam writing, so that a change in a threshold voltage of the one transistor results in a change of its channel resistance relative to the channel resistance of the other load element transistor if it was under before the selective altering, or vice-versa.

Abstract: A circuit for detecting power supply variations in which a first and second transistor are connected in a cross-coupled mode. A load device is connected to each transistor and to a source of power. The loads are unbalanced such that upon application of power to the circuit a first state is always assumed. The cell is forced to its second state. A charge transfer device is connected between first and second nodes formed at the connection between the first transistor and its load and the second transistor and its load. Upon reduction of power supply voltage below that of the active node, a charge transfer takes place which allows the cell to return to its initial state. Detection of the initial state indicates loss or reduction of power has occurred.

Abstract: An insulated-gate field-effect-transistor (IGFET) quasi-static decoder for programming an electronically-programmable read-only memory (EPROM) applies to the floating gate of selected memory devices a programming voltage. Prior to selection, each row and column conductor of the memory is latched at a first voltage. Precharge circuitry responsive to a single precharge pulse establishes an enabling voltage for unlatching a selected row and column. The selected row and column is then coupled via a switch to a source of programming voltage.

Abstract: An electrically alterable memory cell is described which has a capacitive imbalance for causing the memory cell to assume either of its two stable states, and which uses a capacitor as a non-volatile storage element for retaining the information stored in the memory cell during power down operation. The capacitor has an alterable capacitance-voltage curve which is employed to identify the information in the bistable multivibrator just prior to loss of power. When power is returned, the capacitor causes the bistable multivibrator to assume that stable state in which it was operating at the time power was lost.

Abstract: A non-volatile MOS memory cell which includes a bistable (flip-flop) circuit with slightly imbalanced loads. An electrically programmable, floating gate device is coupled across a portion of one of the loads to permit selective shunting. When the cell is powered-down (such as at power failure), the floating gate is either charged or discharged as a function of the state of the flip-flop. When power is reapplied, the imbalance caused by the selective shunting forces the flip-flop to its previous state. The relatively small cell does not require resetting, and the stored information is returned in its true (non-complementary) form when the cell is reactivated.

Abstract: An unbalanced bistable, memory cell operable as a read/write and read only memory having a first switch for disconnecting the cell from a power supply and a second switch for interconnecting the information storage nodes in response to a power down signal to discharge the nodes and allow the memory cell to store a preselected bit of information determined by the unbalance after reconnection of the power supply and disconnection of the nodes upon the absence of the power down signal.