Resonant Transfer Substitutes Patents (Class 370/309)
  • Patent number: 8902915
    Abstract: A context-free (stateless) dataport may allow multiple processors to perform read and write operations on a shared memory. The operations may include, for example, structured data operations such as image and video operations. The dataport may perform addressing computations associated with block memory operations. Therefore, the dataport may be able, for example, to relieve the processors that it serves from this duty. The dataport may be accessed using a message interface that may be implemented in a standard and generalized manner and that may therefore be easily transportable between different types of processors.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: December 2, 2014
    Assignee: Intel Corporation
    Inventors: Dinakar Munagala, Hong Jiang, Bishara Shomar, Val Cook, Michael K. Dwyer, Thomas Piazza
  • Patent number: 8451758
    Abstract: The invention relates to a method and a device for operation of two wireless services whereas a first service is broadcasting signals within burst with known time distances between the bursts and a second service is transmitting signals at least between a first partner and a second partner. The problem to be solved by the invention is to enable a user to use applications of at least to services concurrently at the same time with the same device. The problem is solved by an operation of one and the same device which is receiving bursts in a first mode of the first service and is switched from the first mode into a mode of the second service during the time between the bursts of the service.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: May 28, 2013
    Assignee: Entropic Communications, Inc.
    Inventor: Volker Aue
  • Patent number: 8238275
    Abstract: An integrated circuit (IC) includes a processing module and main memory. The processing module includes a processing core and a first processing module millimeter wave (MMW) transceiver coupled to the processing core. The main memory includes memory and a first memory MMW transceiver coupled to the memory. At least one of an instruction and data is conveyed between the processing core and the memory via the first processing module MMW transceiver and the first memory MMW transceiver.
    Type: Grant
    Filed: August 30, 2008
    Date of Patent: August 7, 2012
    Assignee: Broadcom Corporation
    Inventors: Ahmadreza (Reza) Rofougaran, Timothy W. Markison