Automatic Patents (Class 375/230)
  • Patent number: 11942899
    Abstract: Envelope tracking (ET) voltage correction in a transmission circuit is provided. The transmission circuit includes a transceiver circuit and a power amplifier circuit(s). The transceiver circuit generates a radio frequency (RF) signal(s) from a time-variant modulation vector and the power amplifier circuit(s) amplifies the RF signal(s) based on a modulated voltage and provides the amplified RF signal(s) to a coupled RF front-end circuit. Herein, the transceiver circuit is configured to apply a complex filter(s) to the time-variant modulation vector and/or the RF signal(s) to compensate for a voltage distortion filter created across a modulation bandwidth of the RF signal(s) by coupling the power amplifier circuit with the RF front-end circuit.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: March 26, 2024
    Assignee: Qorvo US, Inc.
    Inventors: Nadim Khlat, James M. Retz
  • Patent number: 11923872
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: March 5, 2024
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 11777523
    Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to perform parity permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups including the interleaved parity bits; and a puncturer configured to select some of the parity bits in the group-wise interleaved bit groups, and puncture the selected parity bits, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups are positioned at predetermined positions, respectively, and a remainder of the bit groups are positioned without an order within the group-wise interleaved bit groups so that the puncturer selects parity bits included in the some of the bit groups positioned at the predetermined positions sequentially and selects parity bits included in the remainder of the bit groups without an order.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: October 3, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-Joong Kim, Se-Ho Myung, Hong-sil Jeong
  • Patent number: 11722340
    Abstract: A method for comparing communication links in a communication network includes (a) obtaining first raw equalizer coefficients in a frequency domain, the first raw equalizer coefficients corresponding to a first communication link, (b) obtaining second raw equalizer coefficients in the frequency domain, the second raw equalizer coefficients corresponding to a second communication link, (c) removing time delay from the first raw equalizer coefficients to generate first corrected equalizer coefficients, (d) removing time delay from the second raw equalizer coefficients to generate second corrected equalizer coefficients, and (e) comparing the first corrected equalizer coefficients to the second corrected equalizer coefficients to determine a relationship between the first and second communication links.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: August 8, 2023
    Assignee: Cable Television Laboratories, Inc.
    Inventors: Thomas Holtzman Williams, Luis Alberto Campos, Lin Cheng
  • Patent number: 11677421
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: June 13, 2023
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 11575396
    Abstract: The present invention is directed to data communication. More specifically, an embodiment of the present invention provides an error correction system. Input data signals are processed by a feedforward equalization module and a decision feedback back equalization module. Decisions generated by the decision feedback equalization module are processed by an error detection module, which determines error events associated with the decisions. The error detection module implements a reduced state trellis path. There are other embodiments as well.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: February 7, 2023
    Assignee: MARVELL ASIA PTE LTD.
    Inventors: Jamal Riani, Farshid Rafiee Rad, Benjamin P. Smith, Yu Liao, Sudeep Bhoja
  • Patent number: 11387800
    Abstract: A parametric equalizer includes a first parametric equalizer circuit, a second parametric equalizer circuit, a first multiplication circuit, a second multiplication circuit, an addition circuit, and a weighting control circuit. The first parametric equalizer circuit processes an input signal to output a first output signal. The second parametric equalizer circuit processes the input signal to output a second output signal. The first multiplication circuit multiplies the first output signal and a first weighting value to generate a first adjusted output signal. The second multiplication circuit multiplies the second output signal and a second weighting value to generate a second adjusted output signal. The addition circuit combines the first adjusted output signal and the second adjusted output signal to generate an equalizer output signal. The weighting control circuit dynamically adjusts the first weighting value and the second weighting value according to the equalizer output signal.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: July 12, 2022
    Assignee: Elite Semiconductor Microelectronics Technology Inc.
    Inventor: Jung-Kuei Chang
  • Patent number: 11381431
    Abstract: A receiver receives communications over a communication channel, which may distort an incoming communication signal. In order to counter this distortion, the frequency response of the receiver is manipulated by adjusting several frequency response parameters. Each frequency response parameter controls at least a portion of the frequency response of the receiver. The optimal values for the frequency response parameters are determined by modifying an initial set of values for the frequency response parameters through one or more of stochastic hill climbing operations until a performance metric associated with the receiver reaches a local maximum. The modified values are displaced through one or more mutation operations. The stochastic hill climbing operations may subsequently be performed on the mutated values to generate the final values for the frequency response parameters.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: July 5, 2022
    Assignee: NVIDIA Corporation
    Inventors: Vishnu Balan, Mohammad Mobin, Dai Dai, Raanan Ivry, Rohit Rathi
  • Patent number: 11342941
    Abstract: A bit-interleaved coded modulation (BICM) reception device and a BICM reception method are disclosed herein. The BICM reception device includes a demodulator, a bit deinterleaver, and a decoder. The demodulator performs demodulation corresponding to 4096-symbol mapping. The bit deinterleaver performs group-unit deinterleaving on interleaved values. The interleaved values are generated after the demodulation. The decoder restores information bits by LDPC-decoding deinterleaved values generated based on the group-unit deinterleaving. The deinterleaved values corresponds to a LDPC codeword having a length of 64800 and a code rate of 3/15.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: May 24, 2022
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 11290305
    Abstract: A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: March 29, 2022
    Assignee: Highlands, LLC
    Inventors: Jared L. Zerbe, Vladimir M. Stojanovic, Fred F. Chen
  • Patent number: 11196448
    Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to perform parity permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups including the interleaved parity bits; and a puncturer configured to select some of the parity bits in the group-wise interleaved bit groups, and puncture the selected parity bits, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups are positioned at predetermined positions, respectively, and a remainder of the bit groups are positioned without an order within the group-wise interleaved bit groups so that the puncturer selects parity bits included in the some of the bit groups positioned at the predetermined positions sequentially and selects parity bits included in the remainder of the bit groups without an order.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 7, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-Joong Kim, Se-ho Myung, Hong-sil Jeong
  • Patent number: 10965397
    Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: March 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Hong-sil Jeong, Kyung-joong Kim
  • Patent number: 10886209
    Abstract: A self-equalizing interconnect in a connector is installed in a microelectronic device. The self-equalizing interconnect is formed of a plurality of electrically conductive layers under conditions to offset skin-effect losses with respect to frequency change during operation. Each successive layer is configured to with the next highest electrical conductivity and subsequent electrically conductive films gradually decrease in electrical conductivity. In an embodiment, thickness of the conductive film adjacent the reference plain is configured thinnest and subsequent films are added and are seriatim gradually thicker. The highest electrically conductive film is configured closest to a reference plane in the connector, and the lowest electrically conductive film is farthest from the reference plane.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Stephen Harvey Hall, Bok Eng Cheah, Chaitanya Sreerama, Jackson Chung Peng Kong
  • Patent number: 10735058
    Abstract: An objective problem of the invention is to provide a mechanism for improving the performance of a radio access network. According to a first aspect of the present invention, the object is achieved by a method in a first node for adapting a multi-antenna transmission to a second node over an effective channel. The first node and the second node are comprised in a wireless communication system. The method comprises the steps of obtaining at least one symbol stream and determining a precoding matrix having a block diagonal structure. The method comprises the further steps of precoding the at least one symbol stream with the determined precoding matrix, and transmitting the at least one precoded symbol stream over the effective channel to the second node.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: August 4, 2020
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: George Jöngren, Bo Göransson
  • Patent number: 10616015
    Abstract: A signal processing system and method, and an apparatus are provided. A phase recovery apparatus may be used to: receive a feedback signal fed back by an information iteration apparatus, perform, based on the feedback signal, phase recovery on a signal output by an equalizer, and output a phase-recovered signal to a post filtering apparatus, so that the post filtering apparatus performs noise filtering on the phase-recovered signal, and outputs a noise-filtered signal to the information iteration apparatus. To be specific, the phase recovery may be performed, based on the signal fed back by the information iteration apparatus, on the signal output by the equalizer. Because output of the information iteration apparatus is more accurate in determining the signal, precision of the phase recovery can be improved, cycle skipping is reduced, and input signal quality of the post filtering apparatus is improved.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: April 7, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Ling Liu, Zhiyu Xiao, Liangchuan Li
  • Patent number: 10461890
    Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system for supporting higher data rates Beyond 4th-Generation (4G) communication systems such as Long Term Evolution (LTE). A method for operating a receiver in a wireless communication system may include: receiving a signal from a transmitter; performing Integer Forcing (IF) equalization on the received signal; determining a log LikeLihood Ratio (LLR) value of each bit by using a posteriori probability of each bit for the signal determined based on an equalization matrix and a likelihood value for the signal; and decoding the signal by using the LLR value.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: October 29, 2019
    Assignees: Samsung Electronics Co., Ltd., Postech Academy-Industry Foundation
    Inventors: Seok-Ki Ahn, Kyeongcheol Yang, Daeyeol Yang, Sunghye Cho
  • Patent number: 10447428
    Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: October 15, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Hong-sil Jeong, Kyung-joong Kim
  • Patent number: 10432229
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: October 1, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Bo-Mi Lim, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 10432255
    Abstract: A transmission device of the present disclosure includes: a driver unit that transmits a data signal with use of a first voltage state, a second voltage state, and a third voltage state interposed between the first voltage state and the second voltage state, and is configured to make a voltage in the third voltage state changeable; and a controller that changes the voltage in the third voltage state to cause the driver unit to perform emphasis.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: October 1, 2019
    Assignee: Sony Corporation
    Inventor: Hiroaki Hayashi
  • Patent number: 10419031
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: September 17, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 10393781
    Abstract: The present invention relates to a system for impedance generation comprising impedance generation means arranged for receiving an input clock signal and for generating at least one parameter at a frequency derived from the input clock signal, impedance tuning means arranged for receiving the at least one parameter, for synthesizing an impedance based on the received at least one parameter and for outputting the synthesized impedance to a device under test.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: August 27, 2019
    Assignee: National Instruments Ireland Resources Limited
    Inventor: Marc Vanden Bossche
  • Patent number: 10340954
    Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a Low Density Parity Check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a plurality of modulation symbols, wherein the modulator is configured to map bits included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of each of the modulation symbols.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: July 2, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Kyung-joong Kim, Se-ho Myung
  • Patent number: 10164804
    Abstract: Devices and methods for adjusting operation of a receiver that includes a continuous time linear equalizer, a decision feedback equalizer, and a feed forward equalizer. Operation of the receiver may be controlled by determining whether the receiver is operating in operation region using frequency responses of the feed forward equalizer at a first frequency and a second frequency and using the frequency responses of the decision feedback equalizer at the first frequency and the second frequency. If the operation is outside the frequency, a parameter of the continuous time linear equalizer is adjusted based on the frequency responses of the feed forward equalizer and the decision feedback equalizer.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: December 25, 2018
    Assignee: INTEL CORPORATION
    Inventors: Yu Liao, Wenyi Jin, Jihong Ren
  • Patent number: 9807675
    Abstract: The invention relates to a method for synchronizing a mobile station to a base station, comprising in the base station a act of generating an information about a frequency of a channel which is used to transmit data about the identity of the base station and a act of transmitting the information from the base station to the mobile station.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: October 31, 2017
    Assignee: Lantiq Deutschland GmbH
    Inventors: Elias Bjarnason, Stefan Eder
  • Patent number: 9749156
    Abstract: An apparatus and a method for generating statistical signals having a characteristic similar to an input signal of a receiving apparatus to determine an optimized filter coefficient through an adaptive equalization algorithm are provided. The apparatus includes a channel estimator, a statistical signal generator, and an adaptive algorithm processor. The channel estimator estimates a channel of a reception signal. The statistical signal generator generates a plurality of signals having the same characteristic as that of a reception signal using a channel determined through a channel estimation process. The adaptive algorithm processor performs an adaptive equalization algorithm using the plurality of generated signals to determine an optimized filter coefficient.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: August 29, 2017
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Seong-Wook Song, Se-Jin Kong, Hun-Kee Kim
  • Patent number: 9705529
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: July 11, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Bo-Mi Lim, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 9698829
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: July 4, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Bo-Mi Lim, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 9698826
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: July 4, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Bo-Mi Lim, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 9660850
    Abstract: A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals comprises an encoder for encoding service data, a mapper for mapping the encoded service data into a plurality of OFDM (Orthogonal Frequency Division Multiplex) symbols to build at least one signal frame, a frequency interleaver for frequency interleaving data in the at least one signal frame by using a different interleaving-seed which is used for every OFDM symbol pair comprised of two sequential OFDM symbols, a modulator for modulating the frequency interleaved data by an OFDM scheme and a transmitter for transmitting the broadcast signals having the modulated data.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: May 23, 2017
    Assignee: LG ELECTRONICS INC.
    Inventors: Jongseob Baek, Jaehyung Kim, Woosuk Ko, Sungryong Hong, Woochan Kim
  • Patent number: 9614644
    Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to perform a low-density parity check (LDPC) encoding on input bits using a parity check matrix to generate an LDPC codeword comprising information word bits and parity bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: April 4, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Kyung-joong Kim, Se-ho Myung, Daniel Ansorregui Lobete, Belkacem Mouhouche
  • Patent number: 9602245
    Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to perform a low-density parity check (LDPC) encoding on input bits using a parity check matrix to generate an LDPC codeword comprising information word bits and parity bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: March 21, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Kyung-joong Kim, Se-ho Myung, Daniel Ansorregui Lobete, Belkacem Mouhouche
  • Patent number: 9577678
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: February 21, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 9577861
    Abstract: The present invention provides a method for transmitting a broadcast signal. The method for transmitting the broadcast signal according to the present invention may comprise the steps of: formatting input streams into multiple data pipes (DPs); encoding data of the multiple DPs according to a code rate for each DP; generating at least one signal frame by mapping the encoded data of the multiple DPs; and modulating data of the generated signal frame in an orthogonal frequency division multiplexing (OFDM) scheme, and transmitting the broadcast signal including data of the modulated signal frame.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: February 21, 2017
    Assignee: LG ELECTRONICS INC.
    Inventors: Jongseob Baek, Byounggill Kim, Woochan Kim, Jaehyung Kim, Woosuk Ko, Sungryong Hong, Chulkyu Moon, Jinyong Choi, Jaeho Hwang, Kookyeon Kwak, Byeongkook Jeong
  • Patent number: 9444437
    Abstract: A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a separate summer circuit configured to add a respective feedback signal to a received input and a latch configured to receive an output of the summer circuit to provide different partial bit sequences based on a clock signal. A feedback circuit includes a multiplexer configured to multiplex the different partial bit sequences of each branch to assemble a full rate bit sequence and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: September 13, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John F. Bulzacchelli, Byungsub Kim
  • Patent number: 9439058
    Abstract: Embodiments of the claimed subject matter provide a method for supporting network monitoring of user equipment events. Some embodiments of the method include receiving, at a home subscriber server (HSS) in a public land mobile network (PLMN), a request to monitor one or more events associated with one or more users. The request is used to configure, activate, or deactivate delivery of reports from one or more entities in the PLMN to a monitor collection entity in response to the event(s). Some embodiments of the method also include configuring one or more profiles in the HSS associated with the user(s) based on the request and providing the request to monitor the event(s) associated with the user(s) to one or more serving nodes for user equipment associated with the user(s).
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: September 6, 2016
    Assignee: Alcatel Lucent
    Inventors: Deborah L Barclay, Bruno Landais, Laurent Thiebaut
  • Patent number: 9264082
    Abstract: A system and method for optimally combining multi-path signals is presented. A first signal is received that traveled a first path from a transmitter to a receiving location and a second signal is received that traveled a different second path from the transmitter to the same receiving location. The paths are different so that the first and second signals contain the same signal data but the first signal has a first distortion that is different than a second distortion in the second signal. According to an objective function, the method adaptively generates a first weight value and a second weight value. The first and second weight values are applied to the respective first and second signals to produce respective first and second weighted signals. The first and second weighted signals are linearly combined producing a combined signal with a combined signal degradation.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: February 16, 2016
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventor: Gary R. Lomp
  • Patent number: 9250327
    Abstract: An adaptive method by which Differential GNSS corrections may be compressed. Each measurement datum to be transmitted to a rover for satellite navigation purposes is decomposed into two parts, namely, an anchor value and a delta value, and in some instances an added third part termed a nonce value is used. Encoding parameters such as the number of bits assigned to each part of the measurement datum, the order of the models used to convey positional data, and scaling constants in the models, are adjusted adaptively based on changing data and/or transmission medium characteristics. Adaptive compression also allows for anomalous conditions such as out-of-range data values to be handled gracefully.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: February 2, 2016
    Assignee: SubCarrier Systems Corporation
    Inventors: David Charles Kelley, Gregory John Berchin
  • Patent number: 9253006
    Abstract: A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals comprises an encoder for encoding service data, a mapper for mapping the encoded service data into a plurality of OFDM (Orthogonal Frequency Division Multiplex) symbols to build at least one signal frame, a frequency interleaver for frequency interleaving data in the at least one signal frame by using a different interleaving-seed which is used for every OFDM symbol pair comprised of two sequential OFDM symbols, a modulator for modulating the frequency interleaved data by an OFDM scheme and a transmitter for transmitting the broadcast signals having the modulated data.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: February 2, 2016
    Assignee: LG ELECTRONICS INC.
    Inventors: Jongseob Baek, Jaehyung Kim, Woosuk Ko, Sungryong Hong
  • Patent number: 9246635
    Abstract: A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals comprises an encoder for encoding service data, a mapper for mapping the encoded service data into a plurality of OFDM (Orthogonal Frequency Division Multiplex) symbols to build at least one signal frame, a frequency interleaver for frequency interleaving data in the at least one signal frame by using a different interleaving-seed which is used for every OFDM symbol pair comprised of two sequential OFDM symbols, a modulator for modulating the frequency interleaved data by an OFDM scheme and a transmitter for transmitting the broadcast signals having the modulated data, wherein the different interleaving-seed is generated based on a cyclic shifting value and wherein an interleaving seed is variable based on an FFT size of the modulating.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: January 26, 2016
    Assignee: LG ELECTRONICS INC.
    Inventors: Jongseob Baek, Jongwoong Shin, Jaehyung Kim, Woosuk Ko, Sungryong Hong
  • Patent number: 9203503
    Abstract: A signal repeating system includes at least one input antenna that receives input signals, at least one output antenna that radiates output signals, and a signal path between the input and output antennas. The signal path includes circuitry for conditioning the input signals with down conversion circuitry that converts input signals to lower frequency signals and analog-to-digital conversion circuitry that converts the input signals to digital signals. A suppression circuit suppresses feedback and interference in the repeated output signals with a digital signal processor configured for receiving samples of the input signals, samples of the output signals, and samples of an interference reference signal and an adaptive filter under the control of the digital signal processor for generating echo cancellation signals and interference cancellation signals.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: December 1, 2015
    Assignee: Andrew Wireless Systems GmbH
    Inventor: Thomas Kummetz
  • Patent number: 9178626
    Abstract: A signal processing method is disclosed. The method includes identifying a preferred loss profile for a plurality of signal transmission channels and generating a filter transfer function corresponding to each of the plurality of signal transmission channels, where each filter transfer function is configured to produce a filtered signal with a loss profile approximately equal to the preferred loss profile. The method further includes generating a plurality of filtered signals by filtering a plurality of signals using the filter transfer function corresponding to each of the plurality of signal transmission channels. and transmitting the plurality of filtered signals to a plurality of receivers via the plurality of signal transmission channels.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 3, 2015
    Assignee: Dell Products L.P.
    Inventors: Bhyrav M. Mutnury, Douglas E. Wallace
  • Patent number: 9166768
    Abstract: In order to reduce deterioration of reception performance even further in a case of simultaneously performing transmission and reception, a transmitting circuit (20), which forms a radio transceiver (1), outputs a transmission signal (110) to be wirelessly transmitted through an antenna (10). A duplexer (30) conducts the transmission signal (110) to the antenna (10), and outputs, as differential signals (102p and 102n), a reception signal wirelessly received through the antenna (10) to a receiving circuit (40). The receiving circuit (40) regulates phases of the differential signals (102p and 102n) based on a first characteristic of the reception signal under a condition that the transmission signal (110) is not output, and a second characteristic of the reception signal under a condition that the transmission signal (110) is output.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: October 20, 2015
    Assignee: NEC CORPORATION
    Inventor: Yoshiaki Ando
  • Patent number: 9137745
    Abstract: A system, method and computer product for a mobile station to locate a femto cell, the method comprising: (a) storing in a database information to locate at least one femto cell; (b) receiving, from at least one macro cell, location information of the UE; (c) searching within the database to determine if the UE is in a general proximity of at least one femto cell; (d) if so, accessing the femto cell using the database information corresponding to the femto cell.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: September 15, 2015
    Assignee: QUALCOMM Incorporated
    Inventor: Aleksandar M. Gogic
  • Patent number: 9106339
    Abstract: Embodiments of the present invention provide a coefficient determining apparatus, equalizer, receiver and transmitter. The coefficient determining apparatus comprises: a synchronizer configured to find a position of a training sequence from signals containing the training sequence received by a transmitter; and a first processor configured to set an initial tap coefficient of an equalizer according to the received signals and the training sequence; wherein in each polarization state, the training sequence comprises n pairs of training symbols, in the n pairs of training symbols, the training symbols of the same pair being identical, the training symbols of the different pair being different, a cyclic prefix and a cyclic postfix being respectively inserted before and after each pair of training symbols, and n being an integer greater than 1.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: August 11, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Meng Yan, Zhenning Tao, Lei Li
  • Patent number: 9094043
    Abstract: A data processing device and a data processing method capable of improving resistance to errors. Code bits of an LDPC code with a code length N of 16200 bits is written to, for example, eight storage units. When the code bits are stored in the storage units, a process of changing the storage start position of the code bits for each storage unit is performed as a sorting process of sorting the bits of the LDPC code such that a plurality of code bits corresponding to 1s in an arbitrary row of the parity check matrix of the LDPC code are not included in a single symbol which is read from the storage units. The present technology can be applied to, for example, the transmission of the LDPC code.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: July 28, 2015
    Assignee: SONY CORPORATION
    Inventors: Yuji Shinohara, Makiko Yamamoto, Takashi Yokokawa
  • Patent number: 9042501
    Abstract: A receiving circuit, use, and method for receiving an encoded and modulated radio signal is provided. The circuit comprise a demodulator and a digital filter connected downstream of the demodulator for moving averaging. The filter has at least two FIFO registers and subtractors. Whereby for subtracting an output value of the FIFO register from an input value of the FIFO register a subtractor is connected to each FIFO register. Wherein the filter has a weighting unit, which is connected downstream of each FIFO register, and wherein the filter has an integrator, which is connected downstream of the subtractors for integration.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: May 26, 2015
    Assignee: Atmel Corporation
    Inventor: Ulrich Grosskinsky
  • Patent number: 9042436
    Abstract: An apparatus is disclosed to compensate for non-linear effects resulting from the transmitter, the receiver, and/or the communication channel in a communication system. A receiver of the communication system contains an image cancellation module that compensates for images generated during the modulation and/or demodulation process. The image cancellation module includes a fine carrier correction loop to correct for frequency offsets between the transmitter and receiver. The image cancellation module includes a coarse acquisition mode and a decision directed mode. The decision directed mode allows for a larger signal-to-noise ratio for the receiver when compared against the coarse acquisition mode.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: May 26, 2015
    Assignee: Broadcom Corporation
    Inventors: Bruce J. Currivan, Loke Tan, Thomas Kolze, Hanli Zou, Lin He
  • Patent number: 9042434
    Abstract: Method and filter for filtering a signal, in which the signal is applied to a delay line having a plurality of taps. Respective weighting coefficients of a windowing function are applied to outputs from the plurality of taps to thereby generate a plurality of weighted outputs. The method comprises repeatedly selecting, for output, whichever of the weighted outputs has the highest value.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: May 26, 2015
    Assignee: Intel Corporation
    Inventor: Christopher Brian Smart
  • Publication number: 20150139293
    Abstract: A receiving device is provided to coordinate transmissions from a first transmitting device and from a second transmitting device of a plurality of transmitting devices to the receiving device in a communication network.
    Type: Application
    Filed: September 30, 2014
    Publication date: May 21, 2015
    Inventors: Kenneth L. Stanwood, David Gell, Murat Karsi
  • Publication number: 20150139289
    Abstract: A receiver includes a fixed delay unit configured to delay a first clock signal received from a clock channel by a predetermined time and output a second clock signal; a first delay unit configured to delay the first clock signal in response to a first control signal; a first data sampler configured to sample a data signal received from a data channel in response to an output signal of the first delay unit and output a first data signal; a second delay unit configured to delay the first data signal in response to a second control signal and output a second data signal; a second data sampler configured to sample the second data signal in response to the second clock signal; and a delay controller configured to output the first control signal and the second control signal.
    Type: Application
    Filed: September 26, 2014
    Publication date: May 21, 2015
    Inventors: Han-Kyu CHI, Taek-Sang SONG, Seok-Min YE, Gi-Moon HONG, Woo-Rham BAE, Min-Seong CHU, Deog-Kyoon JEONG, Su-Hwan KIM