Abstract: The present disclosure relates to a monotonic counter whose value is represented by a number N of binary words of N memory cells of a non-volatile memory, and being able to implement a step increment operation wherein if only one first memory cell represents a first value different from zero, then a second value equal to the said first value incremented by two times the said step is written into a second memory cell of rank directly higher than the rank of the first memory cell; and if a third and a fourth memory cell of consecutive ranks represent, respectively, a third value and a fourth value different from zero, then the third value of the third memory cell of lower rank is erased.

Abstract: A manufacturing system for a data storage device including a non-networked manufacturing device configured to write manufacturing data into a data storage device reliability log in a memory of a data storage device, and a networked manufacturing device configured to read the manufacturing data from the data storage device reliability log in the memory of the data storage device.

Abstract: Technologies for preventing software-based side-channel attacks are generally disclosed. In some examples, a computing device may receive a cryptographic program having one or more programming instructions for performing a key handling operation and may add one or more programming instructions for performing an anti-attack operation to the one or more programming instructions for performing the key handling operation. The computing device may transmit the resulting cryptographic program with the anti-attack operation to an execution device. The execution device, such as a cloud computing system, may execute the cryptographic program, thereby causing execution of the anti-attack operation. The execution of cryptographic program may prevent a side-channel attack by masking the number of key performance events that occur.

Abstract: Embodiments of the invention provide methods for key fob to control unit verification, retention, and revocation. After an initial pairing between a key fob and a control unit, the devices share a secret operation key (OpKey). For verification, the key fob sends the 8 lowest-order bits of a 128-bit counter and some bits of an AES-128, OpKey encrypted value of the counter to the control unit. For key revocation and retention, the control unit is prompted to enter an OpKey retention and revocation mode. Subsequently, each of the remaining or new key fobs is prompted by the user to send a verification message to the control unit. When the control unit is prompted to exit the OpKey retention and revocation mode, it retains the OpKeys of only the key fobs that sent a valid verification message immediately before entering and exiting the OpKey retention and revocation mode.

Abstract: The method for the representation of video and audio signals on a low-resolution display panel, which includes the steps of: scaling the video or audio frame to fit the display panel, quantization of the video or audio signals to predetermined level values, temporal representation of video data by using the pulse density modulation, sending the signal pulses to the display panel. In further aspect the step of temporal representation contains the anti-flickering signal manipulation technique incorporating maximization of separation of the pulses during the pulse density modulation.

Abstract: A counter in a non-volatile memory including at least two sub-counters, each counting with a different modulo, an increment of the counter being transferred on a single one of the sub-counters and the sub-counters being incremented sequentially.

Abstract: A counter in a non-volatile memory including at least two sub-counters, each counting with a different modulo, an increment of the counter being transferred on a single one of the sub-counters and the sub-counters being incremented sequentially.

Abstract: Occurrences of a particular event in an electronic device are counted by incrementing an event counter each time a variable number of the particular events have occurred, and automatically increasing that variable number as the total count increases. The variable number (prescale value) can increase geometrically according to a programmable counter base each time the count mantissa overflows. The event counter thereby provides hardware-implemented automatic prescaling while significantly reducing the number of interface bits required to support very large count ranges, and retaining high accuracy at very large event counts.

Abstract: Occurrences of a particular event in an electronic device are counted by incrementing an event counter each time a variable number of the particular events have occurred, and automatically increasing that variable number as the total count increases. The variable number (prescale value) can increase geometrically according to a programmable counter base each time the count mantissa overflows. The event counter thereby provides hardware-implemented automatic prescaling while significantly reducing the number of interface bits required to support very large count ranges, and retaining high accuracy at very large event counts.

Abstract: The present invention discloses a vMOS based multi-valued counter unit. The counter unit includes a vMOS source follower and at least a control gate connected the vMOS source follower. The control gate includes a first dual-value D flip-flop, a second dual-value D flip-flop, an AND gate, and an OR gate. The present invention utilizes the vMOS to replace the complicated threshold value operations of the multi-value logic. The current invention implements the true multi-value logic and a multi-base multi-value counter by increasing the number of the dual-value D flip-flop, and connecting the dual-value D flip-flop to the input control gate of the vMOS follower. The present invention applies the asynchronous carry-over concept to implement the multi-digit multi-value counter, and it also has been verified by the simulation of P Simulation Program with Integrated Circuit Emphasis (SPICE).

Abstract: The present invention discloses a neuron MOS based multi-valued counter unit. The counter unit includes a neuron MOS source follower and at least a control gate connected the neuron MOS source follower. The control gate includes a first dual-value D flip-flop, a second dual-value D flip-flop, an AND gate, and an OR gate. The present invention utilizes the neuron MOS to replace the complicated threshold value operations of the multi-value logic. The current invention implements the true multi-value logic and a multi-base multi-value counter by increasing the number of the dual-value D flip-flop, and connecting the dual-value D flip-flop to the input control gate of the neuron MOS follower. Comparing to the conventional multi-value counter, the present invention reduces the necessary components in constructing the counter, and it also reduces the cost and power consumption.

Abstract: A counter is efficiently implemented in non-volatile memory by using two binary counters and selectively using one or the other as a current counter. Writes to the binary counters are minimized by using two linear counters and using the state of the binary counters to determine which binary counter contains the current count. Write operations can be performed to the “not current” binary counter with the final write operation being to the linear counters. The linear counter write operations can be in program-only mode so that a power failure will not result in a loss of counts.

Abstract: The disclosed embodiments relate to an asynchronous down counter, which can be loaded with any value N and then decrement exactly N times. The counter comprises an array of cells, wherein each cell is configured to hold a digit in a redundant base-k representation of a number contained in the array of cells. Each cell further comprises a finite state machine that defines state transitions between states, where these states are held on wires and state transitions are synchronized between neighboring cells. Each cell is further configured to asynchronously borrow, if possible, from a more significant adjacent cell to increase a value of a digit in the cell. This asynchronous borrowing improves performance by ensuring that a decrement operation, which decrements a digit in a least significant cell in the array, will borrow from an adjacent more significant cell, without having to wait for the completion of a rippling sequence of borrows from more significant cells.

Abstract: Systems and methods for designing data structures are provided. In one embodiment, an asynchronous first-in-first-out (FIFO) data structure may include, for example, a FIFO memory having a depth d in which d is an integer and a code generator coupled to the FIFO memory. The code generator may provide, for example, a first code sequence of length 2d. The first code sequence may have a circular property and a Hamming length of one for any two consecutive codes of the first code sequence. The first code sequence may be generated from a second code sequence by removing one or more pairs of mirrored codes of the second code sequence.

Abstract: The present invention relates to a unit counter block. According to an aspect of the present invention, the unit counter block includes a D-flipflop, a second MUX, and a first MUX. The-flipflop outputs first and second output signals in synchronism with a clock signal. The second MUX selects any one of external data and the second output signal of the D-flipflop in response to a data load signal and outputs a selected signal. The first MUX transfers any one of the first output signal of the D-flipflop and the output signal of the second MUX as an input signal of the D-flipflop in response to a counter enable signal or the data load signal.

Abstract: A counting device includes a set of memory cells, which are configured to store respective bits of a count code. A controller is coupled to the memory cells so as to increment, in response to occurrences of a count input, the count code in the set of the memory cells from an initial value up to a preset bound in each of a plurality of successive iterations, and to shift the bits of the count code that are respectively stored in the memory cells in each of the iterations relative to a preceding iteration.

Abstract: A counter device includes: a rewritable counter having a non-volatile memory which requires sector erasure to once turn all data in a sector into high data, prior to changing low data into high data in respective bits; and a control section updating a counter value of the rewritable count by writing in and reading out the data with respect to the rewritable counter using a complement of 1, and thereby controlling writing in and reading out the data of the rewritable counter.

Abstract: Disclosed herein is a counter circuit for controlling an off-chip driver, wherein hexadecimal number counting is performed using a N (N is a natural number) number of T-flip-flops. The plurality of the T-flip-flops performs a hexadecimal number counting operation to generate 4-bit, 5-bit and 6-bit off-chip driver control signals having a logic value of 16, 32 or 64. A plurality of counting controllers controls the counting operation of the T-flip-flops to increase or decrease the logic value of the control signals for controlling the off-chip driver.

Abstract: A non-volatile counter circuit includes a state machine having a first input for receiving one or more control signals, a second input for receiving a current count value, a third input for receiving historical information, and an output for providing a next count value and an up/down control signal, and a non-volatile counter having an input coupled to the output of the state machine, and an output for providing a non-volatile count value. The non-volatile counter can be implemented onto a single integrated circuit using ferroelectric memory technology. The non-volatile counter circuit includes a first power supply node and a second power supply node for receiving power for operating the non-volatile-counter circuit through a first power supply or a second power supply, or both. The first and second power supplies can be low energy power supplies such as that provided by a sensor, or can be conventional power supplies.

Abstract: A method and apparatus for normalized bit counting is described. The method comprising incrementing a bit counter using a first clock, and adjusting a target bit based on a difference in frequency between the first clock and a second clock. The method further comprising determining when the bit counter reaches the adjusted target bit.

Abstract: A nonvolatile counter. A nonvolatile storage is organized in digits having non-uniform bases. Circuitry is provided to increment a count value represented by the digits in response to an increment command.

Abstract: A state machine, a counter, and related method for gating redundant triggering clocks according to the initial states is provided. The state machine includes a plurality of state units and a clock gating circuit. Each of the state unit is triggered by a clock to generate a corresponding varying state, and the clock gating circuit is capable of selectively withholding a triggering clock to at least one state unit according only to an initial state, such that the selected state unit(s) will not be triggered by the triggering clock while the rest of the state units are triggered by the triggering clock to update their corresponding states.

Abstract: A circuit for controlling the random character of a bit flow, including an input shift register receiving the bit flow and having its outputs exploited in parallel, at least one element for comparing at least a partial content of the input register with predetermined patterns, a plurality of counters in a number at most equal to the number of predetermined patterns, and an element for detecting the exceeding of at least one threshold by one of the counters, the result of this detection conditioning the state of a word or bit indicative of the random or non-random character of the bit flow.

Abstract: A digital counter with a dial position having a hardware part which determines the n lowest-value bits of the dial position and a software part which determines the remaining higher-value bits of the dial position includes first and a second software parts as the software part with the dial position being a combination of the first software part and the hardware part when the hardware part is in a first counting range, and being a combination of the second software part and the hardware part when the hardware part is in a second counting range.

Abstract: An LED traffic signal with a display indicating the remaining interval for the current display mode. A switching power supply provides cost of manufacturing and operational efficiencies. Interference with logic circuitry normally associated with switching power supplies is prevented by noise filtering circuitry and isolated ground planes on the printed circuit board.

Abstract: A digital to analog converter (DAC) can comprise: an escalator code generator; and an escalator-code-to-analog converter (ECAC). The generator can (1) represent base 10 numbers with a mixed code having a coin code portion and a cash code portion, which will eliminate multi-bit changes in the cash code upon changes in count direction; and (2) represent a count in a first direction as the sum of the coin code and the cash code. The generator can alter the coin code when the count changes direction while the cash code remains the same until a count capacity of the coin code is exceeded, at which point the cash code can be altered. Cycling between adjacent base 10 numbers is absorbed by the coin code while keeping the cash code the same, which reduces noise introduced into an output of the ECAC due to such cycling.

Abstract: A machine used for digital counting which can provide multiple output counts. The machine is particularly useful in analog-to-digital (A/D) converters and in digital-to-analog (D/A) converters. The multiple output counts can change in different directions or in the same direction, and are generated using shared circuitry. The invention exploits properties of counting systems to allow A/D and D/A conversions in convenient digital number formats or in multiple different formats. The invention can be used in integrating converters to help eliminate errors such as comparator offset and dielectric absorption while converting and to increase the conversion rate.

Abstract: A method and apparatus for providing of normalizing a bit count is provided. The method comprises counting bits for a first frame, and normalizing a target bit in a target frame using the bits of the frame. The method then comprises counting to the normalized target bit in the target frame.

Abstract: A nonvolatile counter. A nonvolatile storage is organized in digits having non-uniform bases. Circuitry is provided to increment a count value represented by the digits in response to an increment command.

Abstract: A digital to analog converter (DAC) can comprise: an escalator code generator; and an escalator-code-to-analog converter (ECAC). The generator can (1) represent base 10 numbers with a mixed code having a coin code portion and a cash code portion, which will eliminate multi-bit changes in the cash code upon changes in count direction; and (2) represent a count in a first direction as the sum of the coin code and the cash code. The generator can alter the coin code when the count changes direction while the cash code remains the same until a count capacity of the coin code is exceeded, at which point the cash code can be altered. Cycling between adjacent base 10 numbers is absorbed by the coin code while keeping the cash code the same, which reduces noise introduced into an output of the ECAC due to such cycling.

Abstract: A system and method are presented for providing a multi-stage counter. In one embodiment, a signal propagates from the most significant bit of the counter to the least significant bit of the counter that indicates that all “more significant” stages of the counter have reached a limit value (e.g., all 1's). Use of this propagating signal means that only the first (or first couple) stages of the counter are time critical, while the remainder are less so. The described counter may have a modular design and may result in lower power consumption.

Abstract: A counter circuit, which is capable of operating at high speed and realizing a sequential binary count order, and a counting method thereof are provided. The counter circuit includes a first bit generation circuit, a second bit generation circuit, a third bit generation circuit, and a fourth bit generation circuit. The first bit generation circuit includes a D-flip-flop, inverts its output value every cycle of the clock signal, and generates a first bit output. The second bit generation circuit includes two D-flip-flops, inverts its output value every two cycles of the clock signal, and generates a second bit output. The third bit generation circuit includes four D-flip-flops, inverts its output value every four cycles of the clock signal, and generates a third bit output. The fourth bit generation circuit includes eight D-flip-flops, inverts its output value every eight cycles of the clock signal, and generates a fourth bit output.

Abstract: A pulse density modulator unit transforms an N-bit input signal representing an input value, into an output digital signal having a digital pulse density which is a linear function of the input value. The pulse density modulator unit includes a first pulse density modulator which produces a binary signal representing a multiplication factor as a pulse density. It further includes a combination module which receives the input signal, the binary signal from the first pulse density modulator and an offset control signal. The combination module produces a combined signal which, on average, represents the product of the input signal and the amplification control signal, offset by an amount dependent upon the offset control signal. A second pulse generator uses the combined signal to generate the output digital signal. The combination module may be a selector.

Abstract: The present invention is embodied in a system and method for using cascaded counters with a programmable branch and one or more event clocks that together provide the capability to generate clock pulses at high speed. Further, the programmable counter of the present invention is capable of generating a precise number of clock pulses within a very wide range of numbers.

Abstract: Structure and method for counting a predetermined number of counts is provided. A count end value is identified which is greater than or equal to (not less than) the predetermined number of counts. The count end value is chosen such that it is representable by n symbols (designated n-1, n-2, . . . , m, m-1, . . . , 1, 0) where the most significant n-1 through m symbols are a first binary symbol and the least significant m-1 through 0 symbols are a different second binary symbol, for example "1"0 and "0". An n-symbol current count value (also representable by n-1, n-2, . . . , m, m-1, . . . , 1, 0 symbols) is initialized to a count start value which is equal to the count end value minus the predetermined number of counts, then as the counter counts, the current count value is incremented by one (or some other count increment) for each count or cycle of the counter. After each iteration (or before the next iteration of the counter cycle) each of the n-1, . . .

Abstract: A shared counter performs multiple counting functions in an electronic circuit, such as a memory integrated circuit. An input selection circuit selects one of M input data sets at a given time to be provided as counter initialization data. A counter circuit provides counter output data based on the counter initialization data. An output circuit provides the counter output data to K destination circuits in the electronic circuit. The output circuit provides only one of the K destination circuits with the counter output data at a given time.

Abstract: A digital counter and method for counting are implemented which minimize fatigue-related failure in the storage element for the count value. The counting sequence is chosen such that the transitions within individual storage elements are the same for each element within a complete counting cycle. The invention extends to software or microcontroller implemented methods for counting, including encoding and decoding applications.

Abstract: A shared counter performs multiple counting functions in an electronic circuit, such as a memory integrated circuit. An input selection circuit selects one of M input data sets at a given time to be provided as counter initialization data. A counter circuit provides counter output data based on the counter initialization data. An output circuit provides the counter output data to K destination circuits in the electronic circuit. The output circuit provides only one of the K destination circuits with the counter output data at a given time.

Abstract: The present invention relates to a synchronization method and to a system for establishing in a signal receiving unit (4) a time position of a significant bit position occurring among received information-carrying bit positions (40a, 40b) into which a predetermined number of uniformly distributed line-code related bit positions are inserted.

Abstract: A counter circuit uses a plurality of counter circuits so as to be used in all products employing a counter circuit in a semiconductor device, and thereby performs a multi-bit linear burst sequence operation. The counter circuit for embodying a linear burst sequence includes: a low order counting means which responds to an external clock signal and an external counting control signal, receives and counts a least significant first bit data among base input signals having bits ranging from a first bit to a N-th bit, and then generates a first data signal and a first high order control signal; and a plurality of high order counting means which receive bits ranging from a second bit successively connected to the least significant first bit to N-th bit, perform a counting operation, and generate a second data signal and a second high order control signal.

Abstract: A method and apparatus for dividing a clock circuit employs a device having a first counting element capable of repetitively incrementing through the first plurality of states and a second counting element, having a second number of states, that generates a second output bit and repetitively increments through the second plurality of states. The first counting element is responsive to the second output bit of the second counting element and the reset signal input of the second counting element is responsive to at least one of the first plurality of output bits so that the second counting element resets to an initial state either when the oscillator signal is asserted and the second counting element counts through each of the second plurality of states or when the oscillator signal is asserted and the reset signal input is asserted and the second counting element has incremented through a preselected number of the second plurality of states.

Abstract: A frequency gain display apparatus for an L/C band frequency up unit which is capable of generating a pulse for adjusting the gain of an L/C band frequency up unit used in a satellite system and a pulse for selecting a band width of a SAW (surface acoustic wave) filter and is capable of displaying a gain step of the same.

Abstract: A method of accumulating and maintaining the accumulated data comprises steps of maintaining an intermediate count in a first memory device (12), reading a plurality of count values from a second memory device (14), determining a greatest count value of a subset of the plurality of count values which satisfy at least one criterion, and determining an updated count based upon the intermediate count and the greatest count value. The at least one criterion includes a criterion that the greatest count value differs from a second greatest count value of the subset of the plurality of count values by at most a predetermined difference greater than one. A system and a device to perform the method are detailed.

Abstract: A programmable burst sequence counter is described. The counter is capable of counting sequences of binary numbers in a linear burst sequence or interleaved burst sequence starting from a initial binary number that is presented to the inputs of the counter. The programmable burst sequence counter is applicable to the generation of addresses for the storage and retrieval of digital data from memory arrays.

Abstract: According to the present invention there is provided an encoder, which in one embodiment, includes a processing circuit which generates an output code according to an encoding algorithm, a counter circuit for incrementing a counter value such that only one bit of the counter value changes each time the counter value is incremented, a non-volatile memory for storing the counter value, and a transmitter which transmits the output code and the counter value. In another embodiment of the invention there is provided a method for use with an encoder having a processing circuit which generates an output code according to an encoding algorithm, a counter circuit for incrementing a counter value, a non-volatile memory for storing the counter value, and a transmitter which transmits the output code and the counter value. In one embodiment, the method includes the steps of incrementing the counter value such that only one bit is changed each time the counter is incremented.

Abstract: A method and apparatus monitor the performance of a DDS loop connecting an information transmitter to an information receiver. The information transmitter is typically at a customer premises while the receiver is typically an OCU at the receiving local office. The DDS loop uses an alternate mark inversion communications protocol and the monitoring method and apparatus feature circuitry for determining a current imbalance on the DDS loop. The numbers of positive and negative pulses on the line are individually counted and if the count of the two counters used deviates either positively or negatively from each other by specified amounts, an error event is declared. If the error events meet a statistical timing criterion, a channel error is declared and appropriate steps are undertaken to prevent signals coming from the channel from interfering with other signals available at the local office.

Abstract: A counter circuit selectively generates counting sequences in binary and interleave counting modes. A counter is formed by 3 toggle flip-flops. The toggle signals are provided by a toggle control circuit which contains logic gates that are enabled or disabled based on the state of a mode select signal. In binary mode, output bits are permitted to be used to toggle higher order count stages. In interleave mode, the binary toggle signals are blocked, and another counter circuit counts toggle signals in the interleave sequence, which signals are passed by the toggle control circuit to toggle inputs of the main counter. The other counter circuit can be reset in response to a reset signal applied to a load enable input.

Abstract: Test circuitry for a counter of n number of bits is described. The circuitry includes that which divides the counter into s number of segments when the counter is being tested in a test mode. The invention also includes circuitry for detecting when each segment nears the last count and overriding test mode to reenable a between-segment clock path between the segments before the last count to permit the last count to ripple through the counter to test connections between the segments on the next clock cycle. Previous test implementations did not test the interface between segments because of the prohibitive cost in tester time. In one embodiment, assuming equal numbers of b bits per segment, to fully test a counter using previous techniques, 2.sup.(n-b) +2.sup.b clock cycles would be required. In this technique, only (s-2)+2.sup.b clock cycles are required.

Abstract: A counter for attribute stored in an Ethernet system is partitioned such that the storage section is separated from the incrementors section. In so doing, counters are implemented in a significantly less space than if the counters were implemented as individual counters. The counter utilizes random access memory as the storage section and a 32 bit incrementor. As the incrementor section along with a pair of latches to implement the counter.

Abstract: Disclosed is an absolute value comparator for comparing respective absolute values of sequentially applied two data. A decoder circuit sequentially converts the applied data into a plurality of bit signals in accordance with a predetermined rule. After a preceding conversion bit signal is once held in a register circuit, the held bit signal is inverted for each bit by an inversion circuit. Thus, a logic circuit receives a preceding inverted bit signal and a succeeding conversion bit signal and outputs an output signal B indicating the result of comparison. Since a full adder is unnecessary, a comparison between the absolute values of the applied data can be made at a high speed.