Abstract: A floor polishing machine for concrete includes a frame with an integrated hydraulic fluid tank, a hydraulic drive system, and a hydraulic pump vacuum system. Further, the machine provides a swivel polishing head that provides abutting contact with a floor and includes a floating ring and rubber skirts that seals the polishing head. The machine provides interchangeable wet and dry vacuum systems for collection of the slurry during wet operation and dust during dry operation. A support member inserts into a receiving sleeve for a choice of wet or dry option. A squeegee system attached to the rear of the apparatus collects slurry and operates to send the slurry to a collection tank. The squeegee lifts out of the way during dry operation.

Abstract: Techniques for reducing the probability of spinlock and/or reducing the time that a virtual central processing unit (CPU) may hold a lock are provided. In one embodiment, a computer-implemented method includes determining that an executing virtual CPU is holding a lock for exclusive use of a resource, and scheduling the executing virtual CPU to run for up to a specified time period before de-scheduling the executing virtual CPU. In one embodiment, the executing virtual CPU holding the lock writes a value to a register to indicate that the executing virtual CPU is holding the lock.

Abstract: It is an object to provide a plant monitoring controller that is used as a plant monitoring controller and that can confirm the soundness of a clock signal serving as a reference for operation of each function unit and can diagnose the soundness of a clock signal inspection device itself, thereby having high reliability based on an accurate clock signal. By using two clock signals having the same frequency, soundness of the respective clocks is diagnosed in two clock signal inspection circuits, and during normal operation of one system, a clock error is caused to occur in the other system in a pseudo manner and detection operation of the clock signal inspection circuit is confirmed, whereby online diagnosis of the clock signal inspection device itself is enabled.

Abstract: An on-chip system uses a time measurement circuit to trap code that takes longer than expected to execute by breaking code execution on excess time consumption.

Abstract: The present invention provides a digital low dropout regulator and a control method thereof. The regulator comprises a voltage comparator, a counter, a decoder, a PMOSFET array and a divider. The voltage comparator receives an actual voltage output from the PMOSFET array through the positive input terminal, receives a reference voltage through the negative input terminal, and compares the actual voltage and the reference voltage to obtain a level signal. The divider calculates based on an output voltage pre-configured for a PMOSFET array and an actual voltage output by the PMOSFET array in at least two clock cycles to obtain a first value. The counter generates a control signal based on the level signal and the first value. The decoder receives the control signal transmitted by the counter and controlling the number of switched-on transistors, in the PMOSFET on a basis of the control signal.

Abstract: Method and apparatus for detecting a hung up and/or slow-running syscall without affecting the performance of the syscall. Before a syscall is started, a time stamp can be created at a memory address that is distinct from memory addresses to be used by the syscall. While a syscall thread handles the syscall operation, a separate monitor thread monitors the time stamp to track the length of time the syscall operation has been running. If the syscall thread operation exceeds a threshold time limit, then a flag can be sent to a network administrator to indicate that the syscall may be hung up and/or slow running.

Abstract: A paper-sheet counting machine (10) includes: a recognition and counting unit (24) configured to count paper sheets; a stacking unit (26) configured to stack therein the paper sheets that have been counted by the recognition and counting unit (24), an opening being provided in a front face of the stacking unit (26); a rotary guide unit (28) provided to the stacking unit (26) and configured to allow the paper sheets that have been counted by the recognition and counting unit (24) to be stacked in the stacking unit (26); a shutter (40) configured to close the opening provided in the front face of the stacking unit (26); a shutter drive unit (50) configured to drive the shutter (40) to open and close the opening provided in the front face of the stacking unit (26); and a control unit (70) configured to control the shutter drive unit (50).

Abstract: The present disclosure includes, but is not limited to, a method, system and computer-usable medium for improving performance measurement by analyzing the various events in a multiplexing counting mode and configuring the sampling time accordingly to more effectively performing the sampling. In certain embodiments, when groups of operations are identified for sampling, the present disclosure generates a time sampling table for these groups of operations. The time sampling table is dynamically altered during the runtime of the application to alter the sampling interval of each group. The sampling interval of each group can be increased or decreased based on a threshold of occurrence of the event. This disclosure provides more accurate performance measurement of important events and facilitates a determination of how important events impact application performance.

Abstract: A counter circuit includes a first counter and a second counter. The first counter is configured to count a first counter clock signal which toggles with a first frequency to generate upper (N?M)-bit signals of N-bit counter output signals, in response to a first counting enable signal based on a first comparison signal during a coarse counting interval. N and M are natural numbers, N is greater than M, and M is greater than or equal to 3. The second counter is configured to count a second counter clock signal which toggles with a second frequency which is higher than the first frequency to generate lower M-bit signals of the N-bit counter output signals, in response to a second counting enable signal based on the first comparison signal and a second comparison signal during a fine counting interval which follows the coarse counting interval.

Abstract: Tracking several open data connections is difficult with a large number of connections. Checking for timeouts in software uses valuable processor resources. Employing a co-processor dedicated to checking timeouts uses valuable logic resources and consumes extra space. In one embodiment, a finite state machine implemented in hardware increases the speed connections can be checked for timeouts. The finite state machine stores a last accessed time stamp for each connection in a memory, and loops through the memory to compare each last accessed time stamp with a current time stamp of the system minus a global timeout value. In this manner, the finite state machine can efficiently find and react to timed out connections.

Abstract: A digital period divider has a first counter with R least significant bits (LSB) and P most significant bits (MSB) having a count input and a reset input, wherein the count input receives a first clock signal and the reset input receives a second clock signal; a latch having P bits and being coupled with the P bits of the first counter; a second counter having P bits and a count input and a reset input, wherein the count input receives the first clock signal; and a first comparator operable to compare the P bits of the latch with the P bits of the second counter and generating an output signal, wherein the output signal is also fed to the reset input of the second counter.

Abstract: A digital period divider has a first counter with R least significant bits (LSB) and P most significant bits (MSB) having a count input and a reset input, wherein the count input receives a first clock signal and the reset input receives a second clock signal; a latch having P bits and being coupled with the P bits of the first counter; a second counter having P bits and a count input and a reset input, wherein the count input receives the first clock signal; and a first comparator operable to compare the P bits of the latch with the P bits of the second counter and generating an output signal, wherein the output signal is also fed to the reset input of the second counter.

Abstract: A method of implementing a system time in an electronic device using a timer is disclosed. The method comprises storing a first count reset value in the electronic device; increasing a count value; comparing the first count reset value with the count value at a first particular time; resetting the count value when the count value is the same as the first count reset value at the first particular time; and generating an interrupt request signal when the count value is reset.

Abstract: A control integrated circuit for a power factor correction converter has a pin for detecting an alternating-current information and a direct-current information of an input signal. The control integrated circuit comprises a signal peak detector for detecting a peak value of the input signal to the pin to obtain the direct-current information of the input signal. Since the alternating-current information and the direct-current information of the input signal can be obtained through the same pin, the pin count of the control integrated circuit can be decreased.

Abstract: A method and apparatus in accordance with the present disclosure relate to monitoring gain of a proportional counter. The method includes generating a pulse height spectrum of the proportional counter, defining a first window and a second window within the pulse height spectrum, counting electrical pulses outputted by the proportional counter within the first window of the pulse height spectrum, thereby defining a first window count, counting electrical pulses outputted by the proportional counter within the second window of the pulse height spectrum, thereby defining a second window count, and determining a difference between the first window count and the second window count.

Abstract: A counting circuit of a semiconductor device includes a plurality of counting units configured to count respective bits of counting codes in response to a plurality of counting clocks, respectively, and to control in a counting direction in response to a counting control signal; a clock toggling control unit configured to control the number of counting clocks that toggle among the plurality of counting clocks in response to clock control signals; and a counting operation control unit configured to compare a value of target codes and a value of the counting codes, and to determine a value of the counting control signal according to a comparison result.

Abstract: Representative implementations of devices and techniques provide error detection for a phase-locked-loop (PLL) device. A timing monitor is arranged to count pulses output by one or more portions of the PLL device, a quantity or pattern of the pulses indicating an error of the PLL device.

Abstract: Systems and methods disclosed herein may be useful for use in landing identification. In this regard, a method is provided comprising receiving pulse information over a first time period, wherein the pulse information is indicative of an angular distance traveled by a first wheel, comparing the pulse information to a threshold value, and determining a likelihood of a landing event based upon the comparison. In various embodiments, a system is provided comprising a monstable multivibrator in electrical communication with a metal-oxide-semiconductor field-effect transistor (MOSFET), a resistor-capacitor network in electrical communication with the MOSFET, and a comparator that receives a voltage from the resistor-capacitor network and a reference voltage.

Abstract: A circuit configuration for generating pulses within a time interval on the basis of an input signal includes a counting unit, a comparator unit and a first adder circuit; the time interval being predicted on the basis of at least two defined changes in input signals; the circuit configuration being configured for triggering at the beginning of the time interval by the first adder circuit on the basis of clock pulses, for generating and outputting pulses; for counting a number of generated and output pulses using the counting unit; for comparing the counted number to a setpoint value using the comparator unit; and for ending the generation and outputting of the pulses in response to the reaching of the setpoint value or the ending of the time interval.

Abstract: A counting circuit of a semiconductor device includes a plurality of counting units configured to count respective bits of counting codes in response to a plurality of counting clocks, respectively, and to control in a counting direction in response to a counting control signal; a clock toggling control unit configured to control the number of counting clocks that toggle among the plurality of counting clocks in response to clock control signals; and a counting operation control unit configured to compare a value of target codes and a value of the counting codes, and to determine a value of the counting control signal according to a comparison result.

Abstract: Apparatus and a method for correlated double sampling using an up-counter for parallel image sensors. All bits of a counter are set to one. An offset signal is compared to a first reference signal to define a first period during which the counter is incremented. After the first period, all bits of the counter are inverted. A sensor signal is compared to a second reference signal to define a second period during which the counter is incremented to generate a correlated double sampling value.

Abstract: An integrated circuit includes a counter configured to perform a counting operation and output a count code value. The integrated circuit further includes an operation controller, a digital circuit and an alignment unit. The operation controller receives the count code value and generates a first control signal and a second control signal. The first control signal is generated, when the count code value is equal to a first value, which is counted by the counter prior to a target count value. The second control signal is generated, when the count code value is equal to the target count value. A digital circuit performs a first operation based on the first control signal, and output a digital signal. An alignment unit aligns the digital signal, and outputs the aligned digital signal as a final digital signal in response to the second control signal.

Abstract: An integrated circuit includes a counter configured to perform a counting operation and output a count code value. The integrated circuit further includes an operation controller, a digital circuit and an alignment unit. The operation controller receives the count code value and generates a first control signal and a second control signal. The first control signal is generated, when the count code value is equal to a first value, which is counted by the counter prior to a target count value. The second control signal is generated, when the count code value is equal to the target count value. A digital circuit performs a first operation based on the first control signal, and output a digital signal. An alignment unit aligns the digital signal, and outputs the aligned digital signal as a final digital signal in response to the second control signal.

Abstract: The circuit, typically a delay-locked loop, comprises a phase detector, a first counter, a second counter, and a comparator. The phase detector compares a phase of a first clock signal with a phase of a second clock signal. The first counter generates first count signals and adjusts the first count signals when the phase detector indicates that the phases of the first and the second clock signals are out of alignment. The second counter generates second count signals. The first comparator generates a first comparison signal in response to a comparison between the first count signals and the second count signals. The second clock signal is generated in response to the first comparison signal.

Abstract: In one embodiment, the counter circuit is associated with a pixel array and includes a plurality of counting circuits. Each counting circuit is configured to receive an associated input signal, and each input signal is associated with a different column of the pixel array. A first of the plurality of counting circuits is configured to count based on the associated input signal. Each subsequent counting circuit in the plurality of counting circuits is configured to count based on a difference between the associated input signal and the input signal associated with a preceding counting circuit.

Abstract: A state detection circuit comprises: a first counter circuit that counts a series of first command signals indicative of start of an operation control; a second counter circuit that counts a series of second command signals indicative of completion of the operation control; a count coincidence detection circuit that detects coincidence between a count in the first counter circuit and a count in the second counter circuit; and a state storing circuit that is set by the series of first command signals and reset when coincidence is detected by the count coincidence detection circuit. The first and second counter circuits each comprise a binary counter.

Abstract: In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least clock edges. A comparator determines whether the difference between the master count and the slave count is at least. In a related aspect, a synchronous circuit comprises a clock tree for transmitting a clock signal from a start point to one or more other points, the start point and the other points comprising a first point and second point. A first counter is clocked by the clock signal at the first point and memorizes a first count. A first incrementer advances the first count by one increment. A second counter is clocked by the clock signal at the second point and memorizes a second count. A second incrementer advances the second count by one increment.

Abstract: A circuit comprises a clock tree for distributing a clock signal. A first counter is arranged at a first point in the clock tree. Upon detecting a triggering edge in the clock signal, the first counter sets a first current count equal to a first delayed count. After a first delay, the first counter sets the first delayed count equal to the first current count plus an increment. A second counter is arranged at a second point in the clock tree. Upon detecting a triggering edge in the clock signal, the second counter sets a second current count equal to a second delayed count. After a second delay, the second counter sets the second delayed count equal to the second current count plus the increment. A comparator compares the first current count and the second current count. The first point and the second point are not the same, or the second delay is longer than the first delay.

Abstract: A method for maintaining flow control in a buffer memory coupled to a storage controller is provided. The storage controller includes, first and second counters that are used to monitor when data is read from a buffer memory and when data is transferred from the buffer memory to the host. The method includes, incrementing first and second counter values when data is placed in the buffer memory; decrementing a first counter value when data is read from the buffer memory; and decrementing the second counter value when data is sent to a host. The method further includes, pausing a first channel logic between a transport module and a storage disk when there is no data in the buffer memory; and pausing a second channel logic between a disk and the buffer if there is no space in the buffer memory.

Abstract: A system including wireless tags that transmit information from fixed locations to nearby wireless tag readers possessed by moving persons also includes a wireless tag status inference apparatus to which the wireless tag readers send identifying information received from the wireless tags. The wireless tag status inference apparatus logs the information received from the wireless tag readers, and compares the logged information with a stored list of installed wireless tags to identify suspected inoperable wireless tags. Wireless tags requiring replacement or repair can thereby be identified promptly and inexpensively, without the need to dispatch personnel on periodic inspection tours of all areas in which the wireless tags are installed.

Abstract: A method and a circuit for detecting a malfunction of at least one first counter controlled by a first signal, in which a second counter, controlled by a second signal identical to the first signal or to its inverse, and counting in the reverse direction with respect to the first counter, is set with a value complementary to a setting value of the first counter; the respective current values of the first and second counters are added up; and the current sum is compared with at least one value representing the greatest one of the setting values or this greatest value plus one.

Abstract: An invention is provided for wear leveling in a non-volatile memory system utilizing relative wear counters to indicate relative levels of wear for each memory block in a non-volatile memory system. Whenever a memory block is erased, the associated relative wear counter is incremented. Then, when any relative wear counter reaches a predetermined limit, the value of the lowest relative wear counter is subtracted from each relative wear counter. Thus, each relative wear counter indicates a relative wear level of the associated memory block relative to other memory blocks. In this manner, the relative wear levels are maintained while reducing the amount of memory needed to for each relative wear counter.

Abstract: A circuit and method are provided herein for monitoring the status of a clock signal. In general, the method may include supplying a pair of clock signals to a clock monitor circuit, which is configured for monitoring a status of one clock signal relative to the other. The status indicates whether the frequency of the one clock signal is faster, slower or substantially equal to the frequency of the other clock signal. Once determined, the status may be stored as a bit pattern within a status register, which is operatively coupled to the clock monitor circuit. This enables the status to be read by detecting a logic state of one or more bits within the status register.

Abstract: According to one embodiment, a backlight control apparatus includes a setting section which sets a count value according to a cycle of a PWM pulse signal, a counter section which counts to the count value set by the setting section, a comparing/changing section which compares an actually measured count value of the counter section at a timing of a given vertical synchronous signal with a set count value set according to the cycle of the PWM pulse signal so as to change the count value according to the compared result, a determining section which generates a histogram of a given video signal so as to determine a duty ratio based on the histogram, and a PWM pulse signal generating section which generates a PWM pulse signal based on the counted result from the counter section and the duty ratio determined by the determining section.

Abstract: A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A low cost/complexity accumulator circuit connected to internal signals from a clock/data recovery (CDR) circuit provides a measure of high frequency and low frequency jitter in a received signal. The low frequency jitter measurement is used to correct the high frequency jitter measurement which may otherwise contain error. The corrected output may be used to adjust operational characteristics of the link or otherwise evaluate the link for operating margin. The correction may be performed by subtracting a portion of the low frequency jitter measurement from the measured high frequency jitter, or the value of the low frequency jitter measurement may be used to select between two or more correction factors that are then applied to the high frequency jitter measurement.

Abstract: A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A low cost/complexity accumulator circuit connected to internal signals from a clock/data recovery (CDR) circuit provides a measure of high frequency and low frequency jitter in a received signal. The low frequency jitter measurement is used to correct the high frequency jitter measurement which may otherwise contain error. The corrected output may be used to adjust operational characteristics of the link or otherwise evaluate the link for operating margin. The correction may be performed by subtracting a portion of the low frequency jitter measurement from the measured high frequency jitter, or the value of the low frequency jitter measurement may be used to select between two or more correction factors that are then applied to the high frequency jitter measurement.

Abstract: A self test for a counter system in an integrated circuit includes a clock coupled to counters in a plurality of counters. A first counter in the plurality of counters has a first counter output and a first counter rollover. A second counter in the plurality of counters has a second counter output, a second counter rollover less than the first counter rollover, and a second counter rollover signal that is active when the second counter has rolled over. A comparison circuit having inputs coupled to the first and second counter outputs, compares the first and second counter outputs to produce a counter error output signal. A latch latches the counter error output signal in response to the second counter rollover signal being inactive and the counter error output signal indicating a difference in the first and second counter outputs. Counters may be segmented to reduce a number of digits.

Abstract: A frequency comparator circuit is configured to compare whether the frequency of two input signals are within a tolerance of each other. The frequency comparator circuit includes two counter circuits, an AND gate, and a frequency detector circuit that is configured to provide two reset signals. The two counter circuits are arranged to be clocked by a respective one of the two input signals, and further arranged to be reset by a respective one of the two reset signals. Further, the AND gate is arranged to perform an AND function on the overflow outputs of the first and second counter circuits to provide an status signal. If the status signal is high, the difference in frequency between the two input signals is less than the tolerance. If the status signal is low, the difference in frequency between the two input signals exceeds the tolerance.

Abstract: An apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. Each time value from the set of time values is uniquely associated with a detected edge transition from the input signal. The memory is coupled to the edge detector. The memory is configured to receive from the edge detector the set of time values. The memory is configured to store the set of time values. The pulse-input engine is coupled to the memory. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of the time values stored in the memory.

Abstract: A pixel clock pulse generating apparatus for use in an image forming apparatus includes high frequency clock pulse and pixel clock pulse generators. The high frequency clock pulse generator generates relatively high frequency clock pulses. The pixel clock pulse generator generates pixel clock pulses based on the phase data for instructing a transition time of pixel clock pulses and the high frequency clock pulses.

Abstract: A clock generation circuit for generating clocks having a plurality of frequencies by which a suitable frequency for each task can be supplied such that the power consumption is reduced. A clock generation unit is provided for generating a clock with a constant frequency, with a counter operating in synchronization with the clock for counting pulses of the clock, a comparator for comparing a counter value of the counter with the number of pulses of a clock having a desired frequency, and an output gate for controlling the supply and stopping of pulses of the clock input from the clock generation unit based on a comparison result of the comparator.

Abstract: A measurement system and method for determining a revolution rate of a rotating gear is described. Such a rotating gear can be, for example, a turbine or compressor. The described measurement system and method, for example, can perform highly accurate measurements and can be a fault tolerant system providing high reliability. In one embodiment, an apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of time values stored in the memory.

Abstract: Systems and methods are described for clock recovery and detection of rapid phase transients.

Abstract: Systems and methods are described for clock recovery and detection of rapid phase transients.

Abstract: A system is described for reliable monitoring of clock rates, where a first processor which receives a first clock rate causes a counter to count using this first clock rate. A second processor which receives a second clock rate also causes another counter to count using the second clock rate. The readings of the counters are stored by the processors at predefined intervals in a common memory. Subsequently each of the processors loads the counter reading of the other processor, and compares it with its own counter reading. If both readings are within a tolerance range, one of the counter readings is used as a reference for all the other counters and the other counter readings are made equal to this reference value, so that subsequent monitoring of the processors is based on this reference value for the respective counters. If a reading is outside the tolerance range, an error is triggered.

Abstract: The oscillator 40 with cycle time correction includes a low accuracy oscillator 30A generating a clock CLK3, a counter 41 counting the clock CLK3 and cleared by activation of a clear signal CLR1, a register 42 storing a count CN of the counter 41 as a reference value RV in response to activation of a capture signal CAP; a comparator 43 activating a coincidence signal EQ when CN=RV, a control register 44 including a bit outputting a clear signal CLR2, a bit outputting an enable signal EN and a bit outputting a capture signal CAP, and logic circuits 45 and 46 activating the clear signal CLR1 when the clear signal CLR2 is active or when the enable signal EN and the coincidence signal EQ are both active.

Abstract: A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.

Abstract: A single large register increments ticks of a high-speed clock. A single compare register is associated with the clock register, the compare register preferably being of equivalent length to the clock register. Successive previously-stored timing values are then loaded into the compare register. Typically the timing values are pre-sorted in chronological order. A comparator monitors the clock register's current value and compares it with the timing value currently loaded in the compare register. As the clock register's value reaches the current timing value in the compare register, an alert signal is generated and sent out to activate a particular timed operation identified by an event ID (“EID”) associated with the timing value in the compare register. The current timing value in the compare register is then discarded, and the next timing value in sequence is retrieved into the compare register. In a first embodiment, timing values are stored in a hardware stack.

Abstract: A multi-ratio frequency divider, which is implemented in a BiCMOS (bipolar-complementary metal oxide semiconductor) circuit, includes a dual-modulus counter for dividing by P+1 and P. P+1 is a power of two and there is not necessary an additional flip-flop responsive to high input frequency, which consumes power due to bipolar transistor devices. An output from the counter is further divided by a variably set value. When its count reaches another set value, the division ratio of the dual-modulus counter is switched to another division ratio. When the further divided counter reaches the variably set value, a new cycle starts. The total division ratio of the multi-modulus frequency divider is a combination of the variably set division values, both being binary bit data. No decoder is necessary for converting an input division ratio to the set values.

Abstract: A method for determining the change in frequency of a clock signal (168). The method includes the step of counting the number of clock signal cycles (168) that occur over at least two time windows (162, 164). The number of clock signal cycles counted in the first time window (162) is compared to the number of clock signal cycles counted in the second time window (164).