Nonsignificant Zero Elimination Patents (Class 377/40)
  • Patent number: 11877034
    Abstract: Disclosed are a display apparatus and a channel control method. The channel control method includes: upon receiving channel number information that constructs a channel number in a display apparatus from a control device, obtaining a second channel number according to an instruction for indicating the channel number information each time; determining whether a length of the second channel number is equal to the maximum length of a channel number of a channel list in the display apparatus; and in response to the length of the second channel number being equal to the maximum length of the channel list, directly switching to program content corresponding to the second channel number.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: January 16, 2024
    Assignee: HISENSE VISUAL TECHNOLOGY CO., LTD.
    Inventors: Xiaoming Shao, Peng Liu, Xiangtai Xu, Hongxun Huang, Guili Jia, Xuelei Wang
  • Patent number: 6937688
    Abstract: A state machine, a counter, and related method for gating redundant triggering clocks according to the initial states is provided. The state machine includes a plurality of state units and a clock gating circuit. Each of the state unit is triggered by a clock to generate a corresponding varying state, and the clock gating circuit is capable of selectively withholding a triggering clock to at least one state unit according only to an initial state, such that the selected state unit(s) will not be triggered by the triggering clock while the rest of the state units are triggered by the triggering clock to update their corresponding states.
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: August 30, 2005
    Assignee: VIA Technologies Inc.
    Inventors: Yung-Huei Chen, Shan-Ting Hong
  • Patent number: 6904114
    Abstract: A ones counter that accepts a binary input word of ones and zeros and provides a binary output word indicative of the number of ones within the input word. A two-dimensional array is built with a plurality of like cells connected in a regular manner with the first row of the array determining the least significant bit of the output word and each subsequent row determining the output word's next most significant bit. The first row of the array contains approximately one-half the number of cells as bits in the input word with each subsequent row of the array containing approximately one-half the number of cells of the preceding row with the final row containing a single cell that determines the most significant bit of the binary output word. The ones-count output word is computed asynchronously without clocking circuits or data storage elements.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: June 7, 2005
    Inventors: J. Barry Shackleford, David Kent Cullers