Abstract: A computer-implemented method includes obtaining first and second binary vectors. For each of a plurality of vector locations in a first of j words in the first binary vector, the method includes shifting the binary values for the second binary vector so that a particular one of the binary values in the second binary vector is located at a vector location in a first of the k words in the second binary vector that matches the vector location in the first of j words in the first binary vector. For each of the j words in the first binary vector, the method includes aligning the second binary vector with the word in the first binary vector and determining a binary correlation score. A similarity of the first binary vector and the second binary vector can be determined based at least on one or more of the determined binary correlation scores.

Abstract: The present invention discloses a switching driving method used for a driving system. The driving system transforms any type of waveforms to switching signal array by switching strategy modulation, and transmits to switching circuit. Any type of driving waveforms can be generated through high-speed switching the switching circuit. The waveforms can be generated by operating the switching circuit with the switching strategy. The losses of the switch can be reduced, and the modulation ability of driving signal having several waveforms and multi-channels can be improved.

Abstract: A counter configured to perform counting at both edges of an input clock to output an additional value or a subtraction value for a previous count value and a next count value includes a first latch circuit that latches the input clock, a second latch circuit that latches an output from the first latch circuit, a holding section that holds data of the 0th bit of a count value, and a correction section that performs count correction on data of the first and subsequent bits of the count value on the basis of an output of the second latch circuit.

Abstract: An image sensor includes multiple counters and a counter controller. Each counter of the multiple counters is configured to perform counting of a comparison result signal and to generate a count result, the comparison result signal being obtained by comparing a ramp signal and a pixel signal of a column of multiple columns. The counter controller is configured to generate and transmit a counter clock signal and (n-1) delay clock signals to the counters, respectively, “n” being a natural number equal to or greater than two. Each delay clock signal of the (n-1) delay clock signals is obtained by delaying the counter clock signal by a corresponding offset code.

Abstract: An A/D conversion apparatus includes an N-stage pulse circulating circuit including N (N is a natural number, N?3) inverting circuits connected in a ring shape, the inverting circuits delaying an input pulse signal by a delay time corresponding to an amplitude of a separately input analog input signal, and outputting inverted pulse signals obtained by inverting the pulse signal, a counter unit that counts a number of circulations by which the pulse signal has circulated in the pulse circulating circuit within a predetermined time based on the inverted pulse signal output from one of the N inverting circuits, and a switching unit that switches an output destination of the inverted pulse signal, which is output from an inverting circuit of an Mth (M is an odd natural number, 1?M?N?1) stage of the pulse circulating circuit, according to a change in an operation environment.

Abstract: According to one embodiment, S (S is an integer equal to or larger than two) number of sub counters each count S number of clocks of different frequencies, and a clock switching unit is provided for each sub counter and starts a counting operation of a sub counter of a next stage after finishing a counting operation in a sub counter of a local stage.

Abstract: A clock generating circuit in which a plurality of stages of inverting circuits are connected, a start signal that causes start of clock generation and an output signal from the inverting circuit of a predetermined stage are input to one of the inverting circuits, an element having impedance that changes in accordance with a magnitude of an object analog signal that is an object of conversion to a digital signal is provided between the adjacent inverting circuits, generates a clock of a frequency in accordance with the magnitude of the object analog signal. A counter counts the number of clocks generated by the clock generating circuit and outputs a count value.

Abstract: An example embodiment of an image sensor may include a controller and a plurality of up/down ripple counters. The controller may generate a first control signal and a second control signal. Each of the up/down ripple counters may perform a stop operation or a count operation in response to a corresponding one of a plurality of operation control signals generated based on at least in part on the first control signal. The count operation may be an up-count operation or a down-count operation based on the second control signal. The image sensor may also include a plurality of memory chains. Each of the memory chains may receive a count value output from the up/down counters and may shift the received count value in response to a third control signal and a fourth control signal output from the controller.

Abstract: A contactless sensor utilizes analog and digital circuitry to provide direct interchangeability with a simple potentiometric sensor, matching all of the electrical properties of a potentiometer, including supply voltage range, power supply current, output voltage range, and having three connection terminals. The contactless sensor operates with voltages from 2 to 30 volts direct current, which includes all of the common industrial sensor power supply voltages: 5V, 10V, 24V, and +/? 15V. The contactless sensor utilizes a total current of less than 0.005 amperes, and its output voltage range includes the power supply rails. These improvements combine to enable the contactless sensor to be a direct replacement when a potentiometric sensor is removed from service.

Abstract: A digital double sampling method, a related complementary metal oxide semiconductor (CMOS) image sensor, and a digital camera comprising the CMOS image sensor are disclosed. The method includes generating first digital data corresponding to an initial voltage level apparent in a pixel in response to a reset signal, inverting the first digital data, outputting a detection voltage corresponding to image data received from outside of the CMOS image sensor, and counting in synchronization with a clock signal, starting from an initial value equal to the inverted first digital data, and for an amount of time responsive to a voltage level of the detection voltage.

Abstract: An example embodiment of an image sensor may include a controller and a plurality of up/down ripple counters. The controller may generate a first control signal and a second control signal. Each of the up/down ripple counters may perform a stop operation or a count operation in response to a corresponding one of a plurality of operation control signals generated based on at least in part on the first control signal. The count operation may be an up-count operation or a down-count operation based on the second control signal. The image sensor may also include a plurality of memory chains. Each of the memory chains may receive a count value output from the up/down counters and may shift the received count value in response to a third control signal and a fourth control signal output from the controller.

Abstract: A TAD (time analog/digital) type of A/D converter has plural series-connected delay units each producing a delay in accordance with the level of a converter input voltage, with a first-stage delay unit receiving a pulse signal at commencement of each A/D conversion sampling interval, and a latch/encoder circuit detecting the total number of delay units traversed by the pulse signal by the end of the sampling interval, to obtain a numeric value expressing the input voltage level. To ensure uniformity of the delays of the delay units, these are formed using transistors of larger size than transistors of other circuits such as the latch/encoder circuit.

Abstract: Apparatus for rapidly acquiring a large number of samples of a signal under test, stores the samples in a waveform memory without converting the samples to binary form. The signal under test is applied to an arrangement of comparators and exclusive-OR gates to provide a signal indicative of amplitude. The waveform memory is arranged in rows and columns. In one embodiment, the amplitude-indicative signal serves as a row address signal for the waveform memory, and a scanning control signal serves as a column address signal for the waveform memory. In another embodiment, an X-Y display is produced in which the column address signal is responsive to the amplitude of a second signal under test.

Abstract: A sigma-delta modulator is disclosed for conversion of an analog or digital low frequency signal of high resolution into a quantized analog or digital signal, with an error feedback circuit for suppression of quantization errors. The sigma-delta modulator includes a delay device (Z−1) for delaying the input signal (X) for a plurality of scanning periods to obtain a plurality of delayed input signals (Xi), wherein i=1, 2, . . . , n and the ith one of the delayed input signals (Xi) is delayed for i scanning periods; an adder (2) for addition of the delayed input signals (Xi) each delayed by the i scanning periods to obtain a first sum signal (S1); a quantizing device (Q, Q0, Q1 to Qn) for producing quantized input signals (VZi) each delayed by the ith scanning period; an adder (3) for addition of the delayed quantized input signals (VZi) to obtain a second sum signal (S2); and a subtraction device (1) for subtraction of the sum signals (S1, S2) from an actual value of the input signal (X).

Abstract: In order to implement the Digital Video Broadcasting descrambling algorithm in the context of MPEG compressed data streams containing interleaved sections of scrambled and unscrambled data, at a data rate of 60 MBits/sec with a clock of 2.7 MHz, a stream cipher has an input to receive scrambled video data, and an output coupled to a block cipher for providing descrambled data, the stream cipher comprises shift register means for holding input data coupled to a first mapping logic mechanism comprising at least a first logic means and a second logic means coupled in sequence and arranged to carry out similar logical steps, and the block cipher means comprising shift register means for holding the output of the stream cipher means and a second logic mapping mechanism, comprising at least a first logic means, a second logic means, a third logic means and a fourth logic means coupled in sequence being arranged to carry out similar logical steps.

Abstract: A current steering semi-digital reconstruction filter for a digital-to-analog conversion circuit, which includes a shift register having a 1-bit digital input stream and a plurality of output taps, where each output tap provides a 1-bit signal which has a value of a logic 1 or a logic 0, and a plurality of resistive paths, where each resistive path includes a resistive element which is connected to a common current source and to a first terminal of an active high switch and a first terminal of an active low switch. A single output tap is used to control the active high switch and the active low switch for a single resistive path. A second terminal of each active high switch of each of the plurality of resistive paths is connected to a non-inverted current path, and a second terminal of each active low switch for each of the plurality of resistive paths is connected to an inverted current path.

Abstract: This invention is for a digital-to-analog conversion circuit (DAC) which includes an interpolation filter circuit, a noise shaper circuit and a semi-digital FIR filter circuit. The entire DAC circuit provides noise shaping, analog filtering and oversampling functions.

Abstract: A voltage to pulse-width conversion circuit having counter which counts a reference frequency and produces a digital output signal having a multi-bit digital value; a decoder which decode the multi-bit digital value of the digital output signal and outputs first and second decoded signals; a digital/analog converter which receives the first and second decoded signals and produces an analog signal having an analog voltage; a comparator which compares the reference voltage and the analog voltage and produces a comparison result signal and a setting circuit which sets the level of the output node to a predetermined voltage level in response to the first and second decoded signals.

Abstract: A data processing system (10) includes a programmable clock signal for an analog converter (28). A duty cycle of the programmable clock signal is programmed by an external user in a prescaler rate selection register (16). A counter subsequently counts for a first period of time corresponding to a phase in which the programmable clock signal is asserted. The counter then counts for a second period of time corresponding to a phase in which the programmable clock signal is negated. By allowing the user to program and modify the duty cycle of the programmable clock signal, the performance of the analog converter (28) may be optimized without constraining the requirements of an external system clock.

Abstract: A pulse circulating circuit includes inverting circuits each for inverting an input signal and outputting an inversion of the input signal. A time of signal inversion by each of the inverting circuits varies in accordance with a power supply voltage applied thereto. One of the inverting circuits constitutes an inverting circuit for starting which is controllable in inversion operation. The pulse circulating circuit circulates a pulse signal therethrough after the inverting circuit for starting starts to operate. An input terminal subjected to an analog voltage signal is connected to power supply lines of the respective inverting circuits for applying the analog voltage signal to the inverting circuits as a power supply voltage fed thereto. A counter serves to count a number of times of complete circulation of the pulse signal through the pulse circulating circuit.

Abstract: A frequency monitoring system constructed of a rack mountable instrument for monitoring laser pulse frequency. The pulsed laser frequency is displayed on a linear bar-graph array composed of Light Emitting Diodes (LED's). The display is calibrated so that each LED represents a radio frequency (RF). When the transmitter laser pulses, the laser pulse is reflected by the target object and detected by the receiver and amplified. A small amount of the laser pulse transmitted is detected and mixed with a stable local oscillator signal to produce an RF burst that is sent to the frequency monitor and converted to TTL levels with a high-speed TTL voltage comparator. The TTL signal is fed into the clock input of a binary counter which is cleared and gated by a synch pulse from the transmitter. The output of the binary counter is sent to a digital to analog converter which converts it into an output voltage that is in turn amplified and used as reference points for LED dot/bar driver IC's.

Abstract: A voltage to pulse-width conversion circuit includes a logarithmic clock generator for receiving a reference frequency signal and generating a logarithmic clock signal TCK; a counter for counting the number of clock pulses of the logarithmic clock signal TCK and outputting a digital value having a plurality of bits; a digital to analog converter for converting the digital value into an analog signal; and a voltage comparator for comparing the output signal of the digital to analog converter with a pulse width modulated control voltage and generating a pulse width modulated output signal with a predetermined duty ratio.

Abstract: A tuning circuit (10) and method of operation for tuning an analog filter (40). The tuning circuit (10) has an integrator with an input portion (12) and a comparator portion (14), a counter (32), and a decoder (34). The integrator is implemented with an RC time constant which is proportional to an RC time constant of the analog filter (40). The comparator portion (14) provides an enable signal during the RC time constant of the integrator to the counter (16) which quantizes the RC time constant relative to a clock period of the counter (16). A predetermined decoding is performed to provide an output control signal to control adjustment of the RC time constant of the analog filter (40).

Abstract: A system for generating an analog regulating voltage to be supplied to one or more circuit elements on an integrated circuit. The circuit elements have operational characteristics that are voltage dependent and the analog regulating voltage having the a property of changing with temperature, power supply voltage, and manufacturing process variations so as to substantially eliminate the effects of such variations on the operational characteristics of the circuit elements.

Abstract: A system and method for generating a variable frequency sine wave carrier signal operates in response to a start signal and a rate signal. The system includes a first counter which drives a second counter via an EPROM; the second counter is clocked by the output of an oscillator. The output of the second counter is converted by filtering to the desired sine wave signal.

Abstract: A frequency division network is disclosed in which a sinusoidal signal is converted to a digital format for frequency division and then converted back to the sinusoidal format, the sinusoidal output waveform having low phase noise. In a preferred embodiment the frequency conversion takes place in an m-fold plurality of edge triggered flip-flops, connected to divide by two, and clocked by the sinusoidal waveform. Each flip-flop is subject to jitter causing phase noise, which is minimized when the output of two sets of four flip-flops are averaged, and then filtered to obtain the sinusoidal fundamental. When a crystal filter having a very narrow pass band is employed, the phase noise is further reduced. The frequency division network uses low cost components and the phase noise of the output waveform approaches that of a stable crystal oscillator.

Abstract: A delay circuit includes a memory addresses of which is designated by a counter incremented in response to each clock signal from an initial value set by an initial value setting circuit to an end value. A digital signal is written into an address as designated and read and converted into an analog signal to be outputted at an output terminal through a buffer amplifier. A delay time is determined by the writing timing and the reading timing of the digital signal. If the delay time is to be varied in the course of a delaying operation, a further initial value is set in the counter.

Abstract: A digital calibration circuit provides 1/3 octave center frequencies substially in the range of 50 Hz-12.5 kHz (25 tones) simultaneously at the output at repeatable levels. The system converts digital data to an analog representation for use in calibrating hydrophones. The calibration circuit is comprised of a clock section, a counting section, a clearing section, a data storage/transfer section, and a signal conditioning section. The information that is provided to the output in analog form is stored in digital form in an EPROM within the data storage/transfer section.

Abstract: A digital-to-analog converter comprising: a distributing circuit (2, 3, 4, 5; 2, 13, 14-26) for distributing data pulses, which are bit-serially supplied at constant time intervals, into a plurality of routesand for providing them as pulses having a constant width; and a converting circuit (12) for adding together the pulses from the distributing circuit and thereby for converting them to an analog output. Such a circuit arrangement can provide pulses for conversion to analog form which all have an identical waveform and an identical area, and errors caused by the difference between the rise and fall times of the pulses can be eliminated and therefore D/A conversion characteristics can be improved.

Abstract: An apparatus and method for detecting the period of a frequency signal having a period greater than a minimum period and within a period range. A clock frequency is generated such that when multiplied by the predetermined range the product is less than 2.sup.N and when multiplied by the minimum period of the product is less than 2.sup.N+M. The resulting clock frequency is multiplied by the minimum period to generate an offset number. A counter is preset with the offset number in response to a detected edge transition of the frequency signal. The counter counts at the clock frequency from a complement of the offset number to a final count at a subsequent edge transition. The final count is contained within the first N bits and is related to the period of the frequency signal.

Abstract: A voltage to pulse-width conversion circuit includes a counter which counts a reference frequency signal and produces a multi-bit digital value; a digital/analog converter which converts the digital value into an analog signal; and a voltage comparator which compares an output of the digital/analog converter with a control signal and produces a pulse width modulated output signal which has a predetermined duty cycle ratio.

Abstract: A circuit and method for converting a binary number having a plurarity of bits, D.sub.o to D.sub.n, to a signal having a proportionally equivalent characteristic. The circuit comprises a parallel input for receiving each bit, D.sub.o to D.sub.n, of the binary number and means for generating a plurarity of wavetrains, W.sub.o to W.sub.n, having frequencies decreasing by powers of two from the least significant wavetrain, W.sub.o, to the most significant wavetrain, W.sub.n. Each wavetrain comprises pulses having a pulse width equal to the inverse of twice the frequence of the least significant wavetrain, W.sub.o, so that the duty cycle of each of the wavetrains is proportional to the corresponding frequency thereof. The pulses of each of the wavetrains are not overlapping with the pulses of the other wavetrains. The circuit also comprises logic means, connected to the input and the generating means, for logically multiplying each wavetrain taken in an order from the least significant to the most significant, W.

Abstract: The visually observable information is expressed in quantitive form according to an arrangement wherein there is firstly detected the distribution, size, shape and similar characteristics of objects appearing essentially in one level or plane of the sample and deviating visually from their environment. This detection is carried out by forming an image of the primary physical object on a light sensitive detector using known optic means, such as a microscope, in order to code the random information into a digital form, and thereupon the results of detection, that is the information thus brought into digital form, is transferred for further analysis to a computing and registering unit, such as a special purpose or process computer. Preferably, the detector unit comprises an array or matrix of light sensitive elements, such as photo-transistors.

Abstract: A variable force push button is used as an input device for a control system. Specifically, a bi-directional storage device produces a command that is applied to an element to be controlled. A signal is generated having a characteristic representative of the force applied to the push button. A representation of the characteristic is integrated by the storage device. In addition to changing the characteristic by varying the force applied to the push button, the user can change the direction of the integration, thereby increasing and decreasing the value of the command. The push button comprises a pressure sensitive element sandwiched between electrically conductive contacts one of which is actuated by the user. The pressure sensitive element is constructed of conductive particles in an elastomeric matrix. Preferably, electrically conductive micro-agglomerates of unbound finely divided electro-conductive carbon particles having a maximum dimension of between about 0.

Abstract: A circuit for providing an indication of watt-hours from a voltage input that is an analog of watts comprises a source of a high-frequency square wave and a precision triangular wave at a frequency that is derived from the high-frequency square wave by frequency division. A time interval is derived by selecting a period between a time when the triangular wave crosses zero volts and the time at which the amplitude of the triangular wave equals the analog input voltage. A count of the number of cycles of the high-frequency signal during that interval provides a measure of the value of the input voltage, and a continuing count of that number of cycles provides a time-integrated value of the count. When the input signal is analogous to watts, the integrated output provides a measure of watt-hours.

Abstract: An adjuster can provide a potentiometric type of adjustment with a control generator, a driver and a transducer. The control generator can provide an adjusting signal to the driver. The driver is coupled to the control generator for providing a drive signal in response to the adjusting signal. The transducer has its input coupled to the driver and this input is electrically isolated from its output. This output of the transducer can conduct by a variable amount in response to the adjusting signal, to simulate potentiometric action.

Abstract: The present invention performs analog to digital conversion using the system clock of a microprocessor, the system clock being the clock which controls the rate of operation of the microprocessor. A varying analog signal is applied to the clock frequency control input of the microprocessor, thereby causing the clock frequency and the rate of operation of the microprocessor to vary in accordance with the varying analog signal. The clock is counted for a predetermined period of time. In the preferred embodiment this predetermined period of time is set by the 60 Hz AC power line. The counted contents at the end of this predetermined period of time is a digital representation of the varying analog signal. The microprocessor includes circuits for performing other operations at the rate set by the clock frequency. The other operations performed by the microprocessor must not be deleteriously affected by the varying rate of operation caused by the varying analog signal.

Abstract: An improved signal converter which isolates a measurement voltage by converting an analog signal into a pulse-width-modulated output signal. The converter has a first integrator followed in series by a threshold value controller whose output signal actuates at least one reversing switch element which supplies to the summing point of the first integrator at which the signal prevails, and to the threshold value controller, either a positive or negative reference voltage. This signal converter has a very low offset and a high linearity at high sampling rates. The signal also has a second integrator whose summing point is also connected to the signal input and output of the reversing switch element. The output signal of the second integrator is the reference signal of the first integrator. The linearity of the signal converter is thus exclusively dependent upon the parameters of the second integrator.

Abstract: A digital-to-analog converter system for converting a digital input signal having parallel words, each word including multi-bit groups of weighted significance, and which is provided at an input word rate of W Hz, is disclosed. The digital-to-analog converter system (10, 100, 200) includes pulse generating circuitry (11, 13, 111, 113, 211, 213) responsive to a first multi-bit group and a second multi-bit group of the digital input words for providing (a) a first pulse modulated signal as a function of the value of the first multi-bit group and (b) a second pulse modulated signal as a function of the value of the second multi-bit group; weighting elements (15, 19, 115, 119, 215, 219) for weighting the first and second pulse modulated signals as a function of the relative weighted significance of the first and second multi-bit groups; and output circuitry (20, 120, 220) for summing and filtering the weighted signals to provide an analog output signal that is representative of the digital input signal.

Abstract: Analog-to-digital conversion and a computer produce finer resolution for interferometer distance measurement. The system applies to a laser interferometer producing two detected signals with voltages 19 and 20 that vary to form two sine waves in quadrature as interference fringes occur. A pair of analog-to-digital converters 21 and 22 converts each of these signals into digital values subdividing each sine wave fringe cycle into a plurality of increments. An up/down counter 25 supplied with a significant digit from each of the converters counts fringes corresponding to changes in path lengths. A computer 30 arranged with access to the fringe count and the digital increments determines a distance measurement based on the fringe count and a fine resolution of the distance measurement based on final values of the signals at any subdivided fringe cycle increments after changes in the path lengths.

Abstract: A system and method is provided for producing digital signals proportional to selected parameters of an input signal supplied to a modulator. The modulated output of the modulator is supplied to a delaying bistable circuit, and both the original output and the delayed output are then supplied to a gate, together with a clocking signal. The output of the gate includes pulses only when the modulated signal and the delayed modulated signal are simultaneously at the same level. As such, the digital output of the gate is a representation of the amount by which one level of the modulated signal exceeds the other, and is directly proportional to the magnitude of one polarity of the signal input to the modulator. Techniques are described for extracting digital signals proportional to the magnitudes of both the positive and negative half waves of the input signal, full waveform magnitude, and waveform offset and polarity.

Abstract: A method and apparatus for converting radiant energy levels to digital data wherein an image sensor is provided having at least one row of sensor elements each including a light sensitive capacitor and an access switch and which changes state produces a corresponding binary output signal when a predetermined charge threshold is exceeded by the capacitor whose charge is a function of intensity and period of an illumination. The row of elements is first calibrated by illuminating same with a reference light source and sensing at a first frequency (F) such that approximately one half of the elements change state and counting the digital output signals corresponding to the changes of state to obtain a first number (B). Thereafter, the row is illuminated with an unknown light source which has a lower radiant energy level than that of the reference light source and senses at a frequency F/2. The digital output signals corresponding to the changes of state are counted to obtain a second number (A).

Abstract: This invention relates to a method of converting a digital signal into an analog signal and a digital-to-analog converter therefor.In the invention, a digital signal having varying pulse width values is converted into a first pulse width signal, with each pulse varying in its pulse width in response to its respective data values and with the center of each pulse width being at a fixed time position within a respective sampling period, while a complement of the digital signal is converted into a second pulse width signal with each pulse varying in its pulse width in response to its respective data value and relative to said center of each respective pulse width. The first and second pulse width signals, after one of them is inverted, are mixed and pass through a smoothing filter to demodulate the digital signal into the analog signal.

Abstract: The counting circuit described issues a numerical information which is a non-linear function of the number of pulses applied to its input.The circuit comprises dividers which divide by integers K.sub.i the pulses applied to their inputs. A first selector connects the output of one of the dividers to the input of a counter in response to a first signal. The content of the counter is compared with numbers k.sub.i by comparators. The output of one of the comparators is connected to a control circuit by a second selector controlled by a second signal issued by the control circuit in response to a comparison signal.

Abstract: An automatic velocity delay circuit utilizes the output signal of a radio equency velocimeter for determining the time a projectile takes to pass a sensor located at the muzzle end of a gun. The circuit uses this time interval pulse and clocking pulses to provide an X-ray trigger pulse at the precise instant that the projectile passes an X-ray head located at a selected position along a parallel path of projectile travel, thus insuring a photographic record of the projectile in the muzzle blast region.

Abstract: An electrical circuit and method for multiplying an analog input signal by a sinusoidal function having an instantaneous phase specified by a number signaled in binary format. As a sine wave generator, the binary number is supplied by a counter clocked at a multiple of the desired sine wave frequency. The most significant bit of the counter modulates the polarity of or actually constitutes the analog input signal which is then fed to a numerically-controlled attenuator driven by the less significant binary counter outputs. The attenuator has selectively switched resistors with values specifying a sine table of attenuation from 0 to 90 degrees. A particular resistor is selected by an analog multiplexer having paired complementary outputs so that over the range of less significant bit values, a full 180 degrees of the sinusoid is generated.

Abstract: A system for converting the frequency of a pulse train to a binary number includes an output counter which converts the pulse train to the binary number. Sampling time periods are applied as pulses to a comparator through another counter. The number of desired sampling periods is set into the comparator. The comparator enables the counter during the sampling time periods and inhibits the output counter on the termination of the total sampling time periods. The output of the output counter, therefore, is a binary representation of the frequency of the incoming pulse train during the total sampling time period.

Abstract: This invention relates to a signal conversion circuit, and more particularly to a signal conversion circuit to convert a digital signal sampled in synchronism with a sampling pulse into a pulse width signal having a pulse width corresponding to the digital value of the digital signal.A first counter is preset to a first count value corresponding to the digital value of the sampled digital signal and begins to count a first clock signal having a predetermined pulse period from the first count value. A second counter is preset to a second count value which is a complement of the first count value and begins to count a second clock signal having a pulse period twice as many as that of the first clock signal from the second count value in response to the detection of a full count of the first counter.

Abstract: A control apparatus for an internal combustion engine includes pulse converter blocks each comprising a register, a detection circuit for determining if the information content of the register has met a predetermined condition and an increment/decrement circuit for incrementing or decrementing the information content of the register. A block is provided for each of the output signals from a CPU, and the pulse converter blocks are driven by a common clock pulse so that the counting operations and the condition detecting operations of the blocks are effected in synchronism with the common clock pulse.

Abstract: A digital to analog converter utilizes a digital missing pulse detector as a time interval measuring means in which the detector includes a programmable counter, the count of which is set to correspond with the digital number or word to be converted. Clock pulses at a high frequency are applied to advance the programmable counter from a reset condition to a terminal or output condition, and the time interval produced depends upon the binary word or number set into the programmable counter. Pulses at a second lower frequency, equal to the repetition rate of the system, are applied to the input of the time interval measuring circuit; so that the output is a series of pulse width modulated pulses having a duty cycle corresponding to the binary word originally set into the programmable counter.