Abstract: A counting method, a counting device, and a counting system and a pixel array using the counting device are provided. The counting device includes a storage module, which comprises multiple storage units in cascade interconnection, the multiple storage units store a plurality of cumulative count values, the multiple storage units are configured as at least one group of storage units; an arithmetic module connected to a first group of storage units and a last group of storage units for calculation according to a received count value and an added cumulative count values input through the last group of the storage units so as to obtain a current added cumulative count values of corresponding objects, which is then output to the first group of the storage units in cascade interconnection.

Abstract: A method and data processing system are provided for detecting a malicious component in a data processing system. The malicious component may be of any type, such as a hardware trojan, malware, or ransomware. In the method, a plurality of counters is used to count events in the data processing system during operation, where each event has a counter associated therewith. A machine learning model is trained a normal pattern of behavior of the data processing system using the event counts. After training, an operation of the data processing system is monitored using the machine learning model. Current occurrences of events in the data processing system are compared to the normal pattern of behavior. If a different pattern of behavior is detected, an indication, such as a flag, of the different pattern of behavior is provided.

Abstract: There is broadly contemplated herein an arrangement whereby each event source feeds a small dedicated “pre-counter” while an actual count is kept in a 64-bit wide RAM. Such an implementation preferably may involve a state machine that simply sweeps through the pre-counters, in a predetermined fixed order. Preferably, the state machine will access each pre-counter, add the value from the pre-counter to a corresponding RAM location, and then clear the pre-counter. Accordingly, the pre-counters merely have to be wide enough such that even at a maximal event rate, the pre-counter will not be able to wrap (i.e., reach capacity or overflow) before the “sweeper” state machine accesses the pre-counter.

Abstract: A prescaling counter includes a prescaling unit and a counter. The prescaling unit includes a programmable divider that is arranged to divide an event clock that includes signaled events to generate a prescaled clock in response to a prescaling value. The counter includes a register that includes a lower count register and an upper count register for generating a count result. The counter is arranged to increment the lower count register in response to the prescaled clock and to increment the upper count register in response to a terminal condition in the lower count register. The prescaling value is generated in response to the upper count register.

Abstract: Methods and structures that implement an event counter in a RAM are provided. A method includes providing a count-RAM, a carry-RAM, and a pre-counter corresponding to an event source. A column in the count-RAM and a column in the carry-RAM represent a value of a value of the event counter. The method further includes storing a count of the event counter received via the pre-counter in the count-RAM and the carry-RAM in a transposed, bit-serial format, such that location zero of the count-RAM and the carry-RAM counts the least significant bit (LSB) of the event counter.

Abstract: A frequency measuring apparatus includes: a counter section adapted to count a signal including a pulse signal for a predetermined time period, and output a binary count value corresponding to a frequency of the signal including the pulse signal; and a low pass filter section adapted to perform a filtering process on the count value, wherein the low pass filter section includes a first stage filter and a second stage filter, the first stage filter is a moving average filter to which the count value is input, and which provides a binary output with a high-frequency component reduced, and the second stage filter performs an average value calculation on the binary output to provide an output with the high-frequency component reduced.

Abstract: There is broadly contemplated herein an arrangement whereby each event source feeds a small dedicated “pre-counter” while an actual count is kept in a 64-bit wide RAM. Such an implementation preferably may involve a state machine that simply sweeps through the pre-counters, in a predetermined fixed order. Preferably, the state machine will access each pre-counter, add the value from the pre-counter to a corresponding RAM location, and then clear the pre-counter. Accordingly, the pre-counters merely have to be wide enough such that even at a maximal event rate, the pre-counter will not be able to wrap (i.e., reach capacity or overflow) before the “sweeper” state machine accesses the pre-counter.

Abstract: Some embodiments include a counter having a first generator to generate signals having different frequencies, and a second generator to generate counter values of the counter. Each of the counter values may be based at least in part on a number of transitions of a respective signal among the signals. Other embodiments are described.

Abstract: A control device for generating a second trigger with a delay of a predetermined time from generation of a first trigger, the control device having: a counter for counting numbers from 0 to n?1 at a frequency with cycles of a first period; a control section, which operates at a frequency with cycles of a second period that is longer than the first period, for calculating a remainder of a division by adding a number of counts of the counter corresponding to the predetermined time to a count value of the counter at the time of generation of the first trigger and by dividing a result of the addition by n; and an output section for outputting the second trigger at a time when the count value of the counter becomes equal to the remainder.

Abstract: A frequency measuring apparatus includes: a counter section adapted to count a signal including a pulse signal for a predetermined time period, and output a binary count value corresponding to a frequency of the signal including the pulse signal; and a low pass filter section adapted to perform a filtering process on the count value, wherein the low pass filter section includes a first stage filter and a second stage filter, the first stage filter is a moving average filter to which the count value is input, and which provides a binary output with a high-frequency component reduced, and the second stage filter performs an average value calculation on the binary output to provide an output with the high-frequency component reduced.

Abstract: A frequency measurement device for measuring a frequency of a signal to be measured including a pulse signal, includes: a signal multiplier section that multiplies the signal to be measured by n (n is an integer) and outputs a multiplied signal; a counter section that counts the multiplied signal with a predetermined gate time and outputs a count value of the frequency of the signal to be measured at a predetermined period; and a low-pass filter that outputs a signal corresponding to the frequency of the signal to be measured based on the count value outputted at the predetermined period.

Abstract: There is broadly contemplated herein an arrangement whereby each event source feeds a small dedicated “pre-counter” while an actual count is kept in a 64-bit wide RAM. Such an implementation preferably may involve a state machine that simply sweeps through the pre-counters, in a predetermined fixed order. Preferably, the state machine will access each pre-counter, add the value from the pre-counter to a corresponding RAM location, and then clear the pre-counter. Accordingly, the pre-counters merely have to be wide enough such that even at a maximal event rate, the pre-counter will not be able to wrap (i.e., reach capacity or overflow) before the “sweeper” state machine accesses the pre-counter.

Abstract: A frequency measuring apparatus includes: a high-order digit calculation section adapted to measure an input signal and output a high-order digit value of a frequency value of the input signal; a low-order digit calculation section adapted to measure the input signal and output a low-order digit value of the frequency value of the input signal; and an adding section adapted to add the high-order digit value and the low-order digit value to each other to output the frequency value of the input signal.

Abstract: An arithmetic counter circuit for high performance CMOS image sensors includes a plurality of flip-flops of a plurality of counter stages and a plurality of multiplexers of the plurality of counter stages being coupled to the plurality of flip-flops. Each of the plurality of multiplexers coupled to receive control signals including at least one of a toggle signal, a keep signal, a shift enable signal, or a mode signal. The control signals select the output of each of the plurality of multiplexers. Each of the plurality of flip-flops is coupled to be in one of a toggle state, a keep state, a reset state or a set state based on inputs received from the plurality of multiplexers. Other embodiments are described.

Abstract: Methods and structures that implement an event counter in a RAM are provided. A method includes providing a count-RAM, a carry-RAM, and a pre-counter corresponding to an event source. A column in the count-RAM and a column in the carry-RAM represent a value of a value of the event counter. The method further includes storing a count of the event counter received via the pre-counter in the count-RAM and the carry-RAM in a transposed, bit-serial format, such that location zero of the count-RAM and the carry-RAM counts the least significant bit (LSB) of the event counter.

Abstract: In certain arrangements and methods, a reset-able counter (100) produces multiple delay times as required by, for example, a finite state machine. The counter (100) counts a stored value by a configurable amount. That configurable amount is determined based upon the period of a clock cycle divided by a desired time unit. The value held by the counter does not represent a count of clock cycles, but rather a count of time units. In other aspects, a device generates fixed delays derived from a variable frequency input clock. The device includes a count circuit (100) and a comparator (114, 116). The number of time-units between consecutive clock edges of the input clock is stored, and the count circuit changes a current-count value by a corresponding amount, with the change being responsive to a clock edge of the input clock. The comparator (114, 116) compares the current-count value to a fixed value that represents a fixed delay time.

Abstract: A method for decrypting a serial transmission signal includes the following steps. First, the serial transmission signal including a serial data signal and a serial clock signal is received. Then, m bits are sequentially read from the serial data signal according to the serial clock signal. Next, values corresponding to the m bits are generated. Thereafter, each value is added to a content value of a register by an addition operation to obtain an addition result, and then the addition result replaces the content value and is stored in the register.

Abstract: Noise in a semiconductor device including a photo sensor is reduced. The semiconductor device includes an analog/digital converter and a photo sensor including a photodiode. The analog/digital converter includes an oscillation circuit and a counter circuit. A first signal output from the photo sensor is input to the oscillation circuit. The oscillation circuit has a function of outputting a second signal obtained by a change in oscillation frequency of the first signal. The counter circuit has a count function by which addition or subtraction is performed by a control signal with the second signal used as a clock signal. The counter circuit performs subtraction during the reset operation of the photo sensor. The counter circuit performs addition during the selection operation of the photo sensor. Thus, the output value of the analog/digital converter can be corrected.

Abstract: Embodiments described herein are related to a counter. In some embodiments, the counter can be used as a divider, e.g., in a fractional PLL. In some embodiments, the counter (e.g., the main counter or counter C) includes a first counter (e.g., counter C1) and a second counter (e.g., counter C2), which, together with the first counter C1, perform the counting function for counter C. For example, if counter C is to count to the value N, then counter C1 counts, e.g., to N1, and counter C2 counts to N2 where N=N1+N2. For counter C1 to count to N1, N1 is loaded to counter C1. Similarly, for counter C2 to count to N2, N2 is loaded to counter C2. While counter C1 counts (e.g., to N1), N2 can be loaded to counter C2. After counter C1 finishes counting to N1, N2, if loaded, is available for counter C2 to start counting to this N2. Counters C1 and C2 can alternately count and thus provide continuous counting for counter C. Other embodiments and exemplary applications are also disclosed.

Abstract: There is broadly contemplated herein an arrangement whereby each event source feeds a small dedicated “pre-counter” while an actual count is kept in a 64-bit wide RAM. Such an implementation preferably may involve a state machine that simply sweeps through the pre-counters, in a predetermined fixed order. Preferably, the state machine will access each pre-counter, add the value from the pre-counter to a corresponding RAM location, and then clear the pre-counter. Accordingly, the pre-counters merely have to be wide enough such that even at a maximal event rate, the pre-counter will not be able to wrap (i.e., reach capacity or overflow) before the “sweeper” state machine accesses the pre-counter.

Abstract: The present invention generates an output clock signal CLKreq having a frequency freq between the frequency fref/A of a divided clock signal CKL1 and the frequency fref/(A+1) of a divided clock signal CLK2. A clock divider circuit selectively generates divided clock signals CLK1, CLK2. A discrete value correction circuit controls the clock divider circuit so as to repeat C times the process of generating the clock signal CLK2 once and the clock signal CLK1 (Q?1) times and then to generate the clock signal CLK1 R times if C<D and so as to repeat D times the process of generating the clock signal CLK1 once and the clock signal CLK2 (Q?1) times and then to generate the clock signal CLK2 R times if C>D. A, B, and C are natural numbers satisfying freq=fref/(A+C/B). In D=B?C, Q is a quotient of B/C if C<D or a quotient of B/D if C>D.

Abstract: A signal converter is comprised of a plurality of counters (“macro-counters”). In turn, each of the macro-counters is comprised of a plurality of single-bit counters (“micro-counters”) that are adapted to receive configuration data in the form of bit fields. The configuration data is comprised of data corresponding to a plurality of coefficients and of data for grouping the micro-counters into the macro-counters. The coefficients are derived from an input signal/output signal ratio of the converter, and control the manner by which the macro-counters generate the output signal. Thus the converter can be programmed by an end-user in the field.

Abstract: A circuit and related method for distributing events in an event stream (i.e., an electronic signal having a plurality of rising edge transitions and falling edge transitions). The circuit distributes the events in a primary event stream across multiple secondary event streams in such a way that the event rate in each of the secondary event streams is lower than the event rate in the primary event stream, but the relative timing of the events in the primary event stream is maintained in each of the secondary event streams. The secondary event streams can then be provided to respective timestamp circuits, which record the times at which events occur in the secondary event streams. Since the relative timing of the events in the primary event stream is maintained in each of the secondary event streams, the multiple timestamp circuits collectively record the times at which events occur in the primary event stream. The circuit and related method can be used when debugging/testing semiconductor devices.

Abstract: The image coding device comprises data adding means for adding specific data to input image data at the end of image data, and arithmetic coding unit not issuing remaining output code of code register after coding of final input data. In this constitution, increase of circuit scale can be suppressed and decline of operation clock can be prevented.

Abstract: A system and method for performing counting operations for a plurality of components is disclosed. A memory stores a plurality of counts from different components. The memory is coupled to a counter and the plurality of counts are accessible to the adder for adding addends to the plurality of counts. A count engine controls the adding of the addends to the plurality of counts.

Abstract: Circuit for selecting a second set of binary inputs according to the number of high input signals applied to a first input set. A first subcircuit has the first input set, logic generating control output signals, each control output signal represents whether the first input set has exactly a predetermined number of high input signals. Each control output signal corresponds to a different predetermined number of high input signals. A second subcircuit has a second input set, a set of control inputs for receiving control output signals from the first subcircuit, and logic including a plurality of switches including one or more pass gates. Each switching component switches to connect or isolate one of the second input set to a common output. The control inputs control the switches. The first and second subcircuits are configured such that only one switch can be switched to connect at a time.

Abstract: A Gray code counter includes a holding circuit, first and second conversin circuit and an operation circuit. The holding circuit stores gray code signals and outputs the stored gray code signals in response to a clock signal. The first conversion circuit receives the gray code signals from the holding circuit and converts the received gray code signals into first binary code signals. The operation circuit applies a logical operation to the first binary code signals so as to generate second binary code signals. The second conversion circuit receives the second binary code signals and converts the received second binary code signals into the gray code signals. The second conversion circuit outputs the gray code signals to the holding circuit.

Abstract: A ones counter that accepts a binary input word of ones and zeros and provides a binary output word indicative of the number of ones within the input word. A two-dimensional array is built with a plurality of like cells connected in a regular manner with the first row of the array determining the least significant bit of the output word and each subsequent row determining the output word's next most significant bit. The first row of the array contains approximately one-half the number of cells as bits in the input word with each subsequent row of the array containing approximately one-half the number of cells of the preceding row with the final row containing a single cell that determines the most significant bit of the binary output word. The ones-count output word is computed asynchronously without clocking circuits or data storage elements.

Abstract: A ones counter that accepts a binary input word of ones and zeros and provides a binary output word indicative of the number of ones within the input word. A two-dimensional array is built with a plurality of like cells connected in a regular manner with the first row of the array determining the least significant bit of the output word and each subsequent row determining the output word's next most significant bit. The first row of the array contains approximately one-half the number of cells as bits in the input word with each subsequent row of the array containing approximately one-half the number of cells of the preceding row with the final row containing a single cell that determines the most significant bit of the binary output word. The ones-count output word is computed asynchronously without clocking circuits or data storage elements.

Abstract: A real time clock counter includes a serially connected plurality of register units, each register unit having a bit register for storing clock data, a half adder for incrementing the clock data stored in the bit register, and an activation circuit for activating the bit register. Each activation circuit includes a first input for receiving an oscillating timing signal and a second input for receiving a binary carry term from the previous bit register unit's half adder. Each activation circuit also includes an output for outputting a first activation signal or a second activation signal according to the first value and the oscillating timing signal such that when the activation circuit outputs the first activation signal, the bit register is activated, and when the activation circuit outputs the second activation signal, the bit register is not activated, saving power.

Abstract: A method and circuit are disclosed for measuring temperature. An exemplary embodiment of the present invention includes a first oscillator circuit that generates a first signal having a frequency that is dependent upon a sensed temperature. Difference circuitry determines a difference in frequency between the first signal and the second signal having a frequency that is substantially independent of temperature, and generates a difference signal having a number of pulses thereon based upon the difference. A counter circuit is responsive to the difference circuitry for offsetting a predetermined temperature level based upon the pulses appearing on the difference signal, to obtain an output signal indicative of the sensed temperature.

Abstract: The present invention relates to a detecting device of rotational position deviation, which detects deviation of the rotational position of machine axes driven by electric motors with pulse signals outputted from pulse generators, which are attached to at least two electric motors. One or more deceleration mechanisms are provided between an electric motor and a machine axis connected to the electric motor. A pulse transducer transforms two pulse trains outputted from the pulse generators to one pulse train, and an integrating counter counts the pulse train which is outputted from the pulse transducer, thus corresponding to the rotation angle. A zero phase pulse is outputted by each rotation of the pulse generator. The invention further comprises a count transducer transforming the count output from the integrating counter, and a calculator of rotational position counter calculating the output of the integrating counter and the count transducer and outputting rotational position errors.

Abstract: An electronic counter for a semconductor-integrated non-volatile memory device includes a single count cell connected with its output to at least one storage element The count cell comprises a summing block of the half-adder type and a master portion of a master/slave flip-flop of which said storage element is a slave portion. Advantageously, the master portion has an output connected to the input side of a number n of slave registers arranged in parallel.

Abstract: The pulse counter counts high speed pulses and detects an absolute phase difference among a plurality of electric motors. Pulse outputs 5 and 6 from pulse generators 3 and 4 are inputted into integrating counters 15 and 16 through pulse converters 9 and 11 and rotation direction detectors 10 and 12. Integrating counters 15 and 16 count up/dow the pulses in response to the rotation direction. Integrating counters 15 and 16 are cleared with a zero phase pulse output 7, outputted per revolution from the pulse generators 3 and 4. Multipliers 19 and 20 multiply outputs from the integrating counters 15 and 16 by a ratio set by a coefficient unit, and output a signal corresponding to the rotation angle of each electric motor. Adder/subtractor 21 estimates a deviation between the outputs of the multipliers 19 and 20 such that the phase difference between the pulse generators 3 and 4 is estimated.

Abstract: A service clock regenerator regenerates a local clock from time stamps of a remote clock transmitted over a network by determining the slope of (or difference between current and previous) time stamps of the remote clock and the slope of time stamps of the local clock. A phase difference is formed as the difference between the slope of the time stamps of the remote clock and the slope of the time stamps of the local clock and this phase difference is accumulated to generate a phase error signal. The phase error signal is filtered to generate a frequency adjustment signal having a magnitude that depends on the phase error signal. The frequency of the local clock is adjusted according to the magnitude of the frequency adjustment signal thereby reducing a phase difference between the remote time stamps and the local time stamps.

Abstract: Disclosed herein is a fractional N-type PLL frequency synthesizer apparatus. A fractional N-type control circuit employed therein for varying N values for each reference cycle is constructed of a combination of a frequency divider (comprising D flip-flops) and a logic circuit (comprising an exclusive OR circuit, AND circuits and an OR circuit), taking the timing provided to output a carry signal into consideration in advance. Owing to such a construction, the fractional N-type PLL frequency synthesizer apparatus can be activated with low noise and can provide a short lockup time.

Abstract: A rate multiplier for rate multiplying a pulse train comprising: an accumulator, a multiplexer for selecting one of a first and a second number of different signs to feed to the accumulator, and a pulse train gate for providing or blocking the pulse train, wherein the multiplexer and the pulse train gate are controlled by the MSB output signal of the accumulator.

Abstract: A multiplexing decoder/counter circuit for monitoring quadrature position encoders. The system includes an edge detector, a position counter, a position latch, a capture latch, and compare management means. Addressable memory blocks are used throughout the design. Information from external differential receivers is directed into a single quadrature decoder circuit using a switch with an effective 16 to 1 selection. An axis scanning state machine addresses multiple memory block based functions simultaneously. Scanning is performed in a circuitous manner in conjunction with the switch. The total circular loop frequency for the sequence is chosen to be equal to or greater than the maximum encoder frequency required. At each visitation of any particular memory address, the state of the circuit is reestablished from the last visit by the scanning state machine. Any change in quadrature signals is noted, and any up or down count is accumulated to the position counter.

Abstract: Quality requirements on a counter may set a limit to the highest frequency that can be applied to the counter. This will also limit the resolution. A counter is provided including a generator for generating, in response to a first clock frequency, M second clock signals phase shifted with respect to each other and of a second frequency lower than the first frequency, and M secondary counters, each one responsive to a respective one of the M second clock signals for generating a secondary counter signal. The second frequency is adapted to work well in the technology available for realizing the secondary counters, with consideration taken to quality requirements. Furthermore, the counter included a summing circuit responsive to the secondary counter signals for generating the resulting counter signals by adding the secondary counter signals such that the counter signal has the same number of bits and the same significance as the secondary counter signals.

Abstract: A time-based digital temperature sensing system has a first oscillator which is temperature sensitive. The first oscillator has a temperature coefficient which allows the first oscillator to generate an output signal which varies linearly as a function of temperature. A second oscillator is provided and is used to generates a reference clock signal. The outputs from the first and the second oscillator are coupled to a timer. The timer has a clock input coupled to an output of the second oscillator and an enable input coupled to an output of the first oscillator. From these input signals, the timer generates a number indicative of a length of time the timer is enabled by the first oscillator. The number is proportional to a current temperature of a material that is being monitored by the temperature sensing system.

Abstract: Disclosed herein is a fractional N-type PLL frequency synthesizer apparatus. A fractional N-type control circuit employed therein for varying N values for each reference cycle is constructed of a combination of a frequency divider (comprising D flip-flops) and a logic circuit (comprising an exclusive OR circuit, AND circuits and an OR circuit), taking the timing provided to output a carry signal into consideration in advance. Owing to such a construction, the fractional N-type PLL frequency synthesizer apparatus can be activated with low noise and can provide a short lockup time.

Abstract: A temperature detector comprises temperature sensing circuitry calibration circuitry, and power regular circuitry. The temperature sensing circuitry has an output that varies with a temperature to create a temperature variation. The calibration circuitry is coupled to receive the output that varies with temperature to create a temperature variation. The calibration circuitry interprets the temperature variation and outputs a value that represents the temperature. The power supply regulator circuitry coordinates power to the temperature sensing circuitry. Alternate embodiments of the temperature detector comprise temperature sensing circuitry, calibration circuitry, and resolution enhancement circuitry. The temperature sensing circuitry has an output that varies with a temperature to create a temperature variation. The calibration circuitry is coupled to receive the output that varies with temperature to create a temperature variation.

Abstract: The invention discloses a method and an apparatus for implementing an L phase clock in conjuction with L counters, where L is an integer, to count at a frequency scalable by L.

Abstract: A rate generator for use in a video server or other computer system requiring the generation of multiple timing signals from a single fixed frequency clock signal is disclosed. The rate generator stores a count value, a subtrahend value and a preload value for each timing signal that must be generated. The subtrahend value is subtracted from the count value. If this causes an underflow, an underflow signal, which comprises the generated timing signal, is asserted. The preload value is then added to the result of the subtraction, forming the new count value. If an underflow did not result from the subtraction, the result of the subtraction is the new count value. The frequency of the generated timing signal is determined by the ratio of the subtrahend and preload values. This permits the generation of many different timing signals from a single fixed frequency. The architecture required to perform these operations is relatively simple and inexpensive.

Abstract: An integrated circuit temperature detector (thermometer) uses a temperature dependent oscillator to count up to a fixed number and thereby generate a time interval indicative of the temperature (a temperature-to-time converter). The time-to-number converter provides a numeric temperature output. Counting oscillations of a relatively temperature independent oscillator for the time interval may digitize the temperature measurement. Calibration and successive approximation iterations permit simple hardware to achieve good accuracy.

Abstract: A rapidly resettable counting device is described, which is particularly suitable for use in signal processors and which comprises a counter (1) receiving a clock signal at an input and supplying its output signal to a first register (2) clocked by the clock signal and to a second register (3) clocked by a reset signal, and a summing stage (4) by means of which the output signal of the second clocked register (3) is subtracted from the output signal of the first clocked register (2), which stage supplies the output signal of the counting device.

Abstract: A timer has a function of compensation calculation and includes a compensation value register 1 for holding a compensation value and an arithmetic unit 2 which adds or subtracts a compensation value ".alpha." held in the compensation value register 1 and a value "CC" of a count value C of a counter 3 at that time point, and by loading the operation result of the arithmetic unit 2 to the counter 3. Such a timer reduces a burden on a CPU and is capable of compensating the count value correctly regardless of a remaining time.

Abstract: A reference clock frequency divider feasible for a motor drive IC (Integrated Circuit), optical disk drive, hard disk drive or similar apparatus. The frequency divider is capable of setting not only integral frequency division ratios but also decimal frequency division ratios without any circuit modification.

Abstract: Apparatus and method to logically process signals representative of multiple bits of multiple-bit numbers include successively delaying applications of the bit-representative signals to logical processing stages from associated input registers by a delay interval between input registers that is substantially equal to the processing delay interval per bit-level processing stage. In this way, successively more significant bits of each of plural numbers being logically processed are validly available for processing at each bit-level logic stage after a delay that is substantially equal to the processing delay interval of a preceding bit-level logic stage.

Abstract: Apparatus for determining the number of cycles occurring in a frequency modulated signal during a sample period, including not only the number of full cycles but any portion of a cycle, by determining the number of whole cycles and adding to this a value obtained by counting the number of high frequency clock cycles occurring between the time of the last rising edge of a full cycle and the end of the sample period, and the number of high frequency clock cycles occurring from the last rising edge prior to the start of the sample period and the start of the sample period and the number of high frequency clock cycles in a whole cycle.