Abstract: A flow device, method, and system are provided for determining the fluid particle composition. An example flow device includes a fluid sensor configured to monitor at least one particle characteristic of fluid flowing through the fluid sensor. The example flow device also includes at least one processor configured to, upon determining the at least one particle characteristic satisfies a particle criteria, generate a control signal for an external device. The example flow device also includes a fluid composition sensor configured to be powered based on the control signal and further configured to capture data relating to the fluid particle composition. The example flow device is also configured to generate one or more particle profiles of at least one component of the fluid based on the data captured by the fluid composition sensor.

Abstract: An approach for counting particles suspended in a flow of gas or liquid in instruments that direct the flow through an illuminated region. Pulses are detected when the signal is below a threshold amplitude and moves above the threshold amplitude. This movement above the threshold creates a dead time during which only one pulse is detected until the signal amplitude moves sufficiently below the threshold such that a subsequent particle creates a distinct pulse. After counting the number of pulses, and determining the measured live time that the signal is below the threshold value, an initial particle concentration is calculated, and the calculation corrected for coincidence by calculating an actual live time as a measured live time minus a constant multiplied by the number of distinctly counted pulses, where the constant has the units of time. From this, particle concentrations in a volume can be determined.

Abstract: A multiplexer switching device is described herein comprising a first data network comprising a plurality of NO contacts; and a second data network comprising a plurality of NC contacts; wherein said a first data network is connected to said second data network via a common DC voltage link.

Abstract: A method is provided for controlling and/or monitoring a compressor system comprising several components, namely one or more compressors, one or more peripheral devices, and also a control/monitoring unit, wherein the compressors and peripheral devices are arranged or connected in a certain configuration. The method distinguishes itself in that (a) in a measured-value-capture step, measured values are captured within the compressor system or the components; (b) in an allocation step, context information is allocated to the measured value or measured values in advance, simultaneously, or after the measured-value capture, in order to standardize the measured values; and (c) in an evaluation step, the measured value or measured values standardized by the context information are used in a control, monitoring, diagnostics, or evaluation routine.

Abstract: An environmental sensor including an inlet and an outlet such that a flow of fluid moves from the inlet to the outlet, a particle detection portion to detect particles in the fluid, and a controller connected to the particle detection portion. The environmental sensor can be in communication with a data acquisition system (e.g., via a wireless access point) to form a particle counting system. Also disclosed are methods of operating the environmental sensor and methods of operating the particle detection system.

Abstract: The present invention generates an output clock signal CLKreq having a frequency freq between the frequency fref/A of a divided clock signal CKL1 and the frequency fref/(A+1) of a divided clock signal CLK2. A clock divider circuit selectively generates divided clock signals CLK1, CLK2. A discrete value correction circuit controls the clock divider circuit so as to repeat C times the process of generating the clock signal CLK2 once and the clock signal CLK1 (Q?1) times and then to generate the clock signal CLK1 R times if C<D and so as to repeat D times the process of generating the clock signal CLK1 once and the clock signal CLK2 (Q?1) times and then to generate the clock signal CLK2 R times if C>D. A, B, and C are natural numbers satisfying freq=fref/(A+C/B). In D=B?C, Q is a quotient of B/C if C<D or a quotient of B/D if C>D.

Abstract: A frequency comparator circuit is configured to compare whether the frequency of two input signals are within a tolerance of each other. The frequency comparator circuit includes two counter circuits, an AND gate, and a frequency detector circuit that is configured to provide two reset signals. The two counter circuits are arranged to be clocked by a respective one of the two input signals, and further arranged to be reset by a respective one of the two reset signals. Further, the AND gate is arranged to perform an AND function on the overflow outputs of the first and second counter circuits to provide an status signal. If the status signal is high, the difference in frequency between the two input signals is less than the tolerance. If the status signal is low, the difference in frequency between the two input signals exceeds the tolerance.

Abstract: A synchronous counter, the inventive counter is synchronized to a clock, e.g., a master clock of an FPGA, and includes a first counter that increments in response to the master clock, a resynchronizer that receives counter bits from the first counter and, when appropriate, generates an increment signal, and a second counter, clocked by the master clock, that increments in response to the increment signal. In a preferred embodiment, the resynchronizer is an n bit AND gate (where the first counter is an n-bit counter) that ANDs at least selected ones of the counter bits and a latch, e.g., a flip-flop, that latches the output of the AND gate. Thus, small counter chains are linked together using flip-flops clocked at the master clock rate, i.e., the same rate as the counter chains, to form a counter chain of any length that will function at the master clock rate.

Abstract: The period of an input signal is subdivided into N parts by carrying out a count, during this period, of the pulses delivered by a clock. This number is divided by N and then the remainder of this division is distributed among all the N parts of the period of the input signal. This technique may be applied to the generation of scanning signals in television.

Abstract: Quality requirements on a counter may set a limit to the highest frequency that can be applied to the counter. This will also limit the resolution. A counter is provided including a generator for generating, in response to a first clock frequency, M second clock signals phase shifted with respect to each other and of a second frequency lower than the first frequency, and M secondary counters, each one responsive to a respective one of the M second clock signals for generating a secondary counter signal. The second frequency is adapted to work well in the technology available for realizing the secondary counters, with consideration taken to quality requirements. Furthermore, the counter included a summing circuit responsive to the secondary counter signals for generating the resulting counter signals by adding the secondary counter signals such that the counter signal has the same number of bits and the same significance as the secondary counter signals.

Abstract: A method and device for varying interpolation factor of at least one position-dependent, periodic signal in a position measurement system. The method and device allows switching between one of a specified number of different interpolation factors at a switching time point at which the interpolated measurement signal has an identical signal form for every possible interpolation factor.

Abstract: Improved PLL frequency synthesizer circuits, including a novel swallow counter, may be operated at high speeds without experiencing internal delays or malfunctions. The swallow counter supplies a modulus signal to a prescaler which is capable of selectively changing a frequency-dividing ratio of a frequency signal. The swallow counter includes a shift register, a counter, a count-up detector, a modulus signal generator, and a control circuit. The swallow counter is connected to the prescaler and the program counter, and is capable of counting a frequency-divided signal based on a set value data and producing the modulus signal in response to a load signal after counting is completed. The swallow counter supplies the modulus signal to the prescaler and determines whether the set value data is data prepared to fix the frequency-dividing ratio.

Abstract: A phase locked loop includes a voltage controlled oscillator (VCO) for generating output VCO pulses. A frequency divider divides the VCO pulses by a variable number to produce frequency divided pulses whose phase is compared with that of input reference pulses by a phase detector. An update pulse is produced by the phase comparator having a pulsewidth corresponding to the detected phase difference. A pulse generator generates a train of update pulses having a combined pulsewidth equal to the pulsewidth of the update pulse, with the update pulses being substantially equally distributed within each period of the reference pulses to produce low output ripple. The update pulses are integrated by a loop filter to produce a D.C. control voltage that controls the VCO to vary the frequency of the VCO pulses such that the phase difference is adjusted toward zero. The frequency divider comprises a binary counter and a controller that enable the frequency divider to divide by a number N that is not a power of 2.

Abstract: A low cost and easily implemented apparatus and method for synchronizing serially connected clock circuits is ideally suited to audio applications. The circuit takes data from a bitstream clock source and from the local source and counts the number of pulses received from each. A desired clock count is calculated based as a multiple of the ratio of the bitstream clock source frequency to the local clock signal frequency. Based on the samples received from the bitstream clock relative to the local clock at a later point in time, samples are either repeated or dropped to correct any error in the bitstream signal.

Abstract: A low cost and easily implemented apparatus and method for synchronizing serially connected clock circuits is ideally suited to audio applications. The circuit takes data from a bitstream clock source and from the local source and counts the number of pulses received from each. A desired clock count is calculated based as a multiple of the ratio of the bitstream clock source frequency to the local clock signal frequency. Based on the samples received from the bitstream clock relative to the local clock at a late point in time, samples are either repeated or dropped to correct any error in the bitstream signal.

Abstract: A programmable frequency divider circuit includes a prescaler which consists of p cascade-connected dividing cells, a cell of rank i in the cascade having a normal division factor 2 and also being programmable so as to divide by 3 the input frequency applied to the cell. Each cell of rank i supplies, as a signal enabling the programmed mode for the preceding cell of rank i-1, a signal which is referred to as a gating signal and which is calibrated as regards duration and position in time at the operating frequency of the cell i, the prescaler (PPSC) being associated with counting means (CNT) for producing a programmable division factor (R) which is equal to M.2.sup.p +N, where M is an integer number applied to the counting means (CNT), p is the number of cells of the prescaler (PPSC), and N is an integer number applied to the programming inputs of the prescaler (PPSC).

Abstract: The frequency divider of the present invention includes one or more regulated digital divider circuits, each of which is made up of a finite state machine such as a general purpose counter. The regulated digital divider circuits can be cascaded such that the frequency divider provides a high degree of precision within only a few stages, regardless of the division ratio. The frequency divider has an output duty cycle which is adjustable so as to provide a more useful output than existing frequency dividers. Moreover, the frequency divider can be implemented using simple logic circuitry and virtually any architecture.

Abstract: An elasticity buffer for use in a data transmission system having a transmitter and a receiver and utilizing a data transfer protocol that periodically supplies an elasticity element that can be deleted or replicated by the elasticity buffer to maintain the synchronous transfer of data elements.

Abstract: A counter is provided which updates a most-recent counter value to be stored in a non-volatile memory. The counter includes a counter circuit for receiving a series of count pulses defining a count operation and outputting a series of coded binary signals in response thereto. Each one of the series of coded binary signals includes at least first digit data and second digit data. A selecting circuit is coupled to the non-volatile memory and the counter circuit for logically selecting, in response to each respective second digit data, a first select memory cell in the non-volatile memory for which the corresponding first digit data is to be stored.

Abstract: An apparatus and method for providing a microprocessor having an inaccurate oscillator with a desired time base. The cycles of the output signal of the oscillator are counted by a first counter until the counted number equals a predetermined correction count. The first counter then produces a timing signal. A second counter is set up to create an actual count indicative of the number of output signals occurring during a predetermined number of periods of an AC signal generator connected to the microprocessor. A predetermined desired count is then subtracted from the actual count to produce a difference count. The difference count is then added to the old correction count to create a new correction count. By iterating this process until the difference count is equal to zero, the timing signal is modified until it is equal to the desired time base.

Abstract: A clock signal generator using fractional frequency division is provided comprising a division circuit that produces a clock signal starting from a timing rhythm signal. The frequencies of the two signals are in a division ratio which is the sum of a whole part and a fractional part. A pulse subtractor is provided for receiving the rhythm signal and transmitting it to the division circuit while deleting at least one pulse from this signal upon a command. An accumulator commands a pulse subtractor on each occasion when the product of the number of pulses of the clock signal counted, starting from a time of origin and of the fractional part, changes by unity.

Abstract: This invention relates to sinewave frequency measuring apparatus and method and more particularly such apparatus including a frequency estimator triggered by a zero crossing of a sinewave and means for producing sample signals at a constant rate; and a method which provides and uses an approximation of the sinewave through the zero crossing, as a straight line between two sampling periods. Errors are eliminated by means of a low pass filter. The method performs a fractional cycle correction by adding or substracting the interpolation results from the raw period time counts.

Abstract: The electronic counter for counting a periodic clock signal generated at a preset clock frequency (f.sub.o) includes a clock circuit generating the periodic clock signal at the preset clock frequency (f.sub.o); an adjustable frequency divider (4) having an output (8), a first input (5) and a second input (7), the first input of the frequency divider (4) being connected to the clock circuit (6) so as to receive the periodic clock signal and the second input (7) of the frequency divider being connected to receive a cycle speed signal (n), the frequency divider (4) containing means to produce a pulsed output signal at a divider output frequency (c.sub.o); a tracking circuit (T) connected to the output (8) of the frequency divider (4) to receive the pulsed output signal at the divider output frequency (c.sub.

Abstract: A circuit arrangement generates a preset number of output pulses each time between two consecutive input pulses, the distance between the input pulses being subject to variation. The output pulses should be approximately evenly distributed, which even distribution, however, cannot be maintained when the cycle of the input pulses changes. To achieve first and foremost that the total number of output pulses is reached as quickly as possible in the case of a change in the input pulse cycle, the circuit includes a first counter device, which supplies a measure for the cycle duration of the input pulses in relation to a clock pulse, and this measure is used as a preset value for the next cycle for a further counter, which counts down the preset value in period with the clock pulses.

Abstract: In a method and an apparatus for determining the frequency of short oscillation bursts of electrical signals firstly oscillation bursts in desired number are read into a storage means and read out again cyclically adjoined to each other so that an oscillation train of any desired length results of which the mean frequency can be easily determined.

Abstract: A device for displaying a physical measure, including a reference pulse generator, a pulse counter, a memory for storing a measurement number, a second memory for storing values used for adjusting the count of pulses, a display for showing a physically measured value corresponding to the number of counted pulses, and a processing unit. The device updates the display value in accordance with pulse counts and the stored measurement number until the device detects that a correction has to be made from examining the contents of the second memory. Upon detection, the device makes proper corrections to the display values.

Abstract: A method for modifying the frequency of a clock signal includes the steps of producing a clock signal having voltage pulses which occur at a first frequency and producing a control signal having voltage pulses which occur at a lower frequency. The frequency of the voltage pulses in the control signal is incremented in successive time intervals and the clock signal and control signal are combined such that one voltage pulse in the clock signal is deleted for each voltage pulse in the control signal. This results in a modified clock signal having a frequency which may be ramped up or down depending upon the initial frequency of the control signal and the direction in which the frequency of the control signal is incremented.

Abstract: An analog/digital voltage controlled oscillator includes a voltage to pulse converter which responds to a control voltage to generate appropriate control pulses to change the mode of operation of a divider to thereby vary the output frequency of the oscillator.

Abstract: A scale pulse signal is produced whenever a revolution sensor detects a unit revolution angle formed an angle between cogs of poles. A time interval between the scale pulse signal is affected by an error in the formed angle. The time interval between the scale pulse signals can be corrected by using a correction coefficient detrmined by an actual value of the unit revolution angle detected by the revolution sensor and by a design value of the unit revolution angle, so that the time interval corresponds to the design value of the unit revolution angle.

Abstract: A PROM has inupts from error detecting and processing equipment of the signal reproducing channels of equipment reproducing digital signals from magnetic tape and can be controlled to process selectively the recognition of errors and of their respective natures by the error detecting and correcting circuits. The error detection circuits also provide a block end signal at the end of every block of data of the digital signal being processed which is protected against errors by check words. At every block end signal the output of the PROM is transferred to a first register, the contents of which are made available to an adder for adding these contents to the contents of the second register (10) and the output of the adder is written into the second register, either without change or after division by two by a switch (12), to the output of the second register.

Abstract: A unique timing system is provided which allows for a user to program timing events with variable periods and edges from a fixed frequency clock, and having resolution greater than that of the fixed reference frequency. Delay elements, which are inherently expensive, inaccurate, and require repeated calibration, are minimized.

Abstract: A method of analyzing the voltage induced in an exciter coil of a stepping motor. After energization the exciter coil is loaded by a low impedance so that the induction voltage can produce a current. Subsequently, it is attempted to maintain the current through said coil equal to zero by periodically connecting said coil to a positive or negative voltage. The pattern of consecutive polarities of these periodic energizations is analyzed.

Abstract: A counter slip control circuit is described for digital transmission systems wherein the counter uses a feedback circuit to define the permissible counter states. The slip control input modifies the feedback function so that certain counter states are either repeated or skipped. A repeated counter state is equivalent to retardation of the counter output signal phase. A skipped counter state is equivalent to advancing the counter output signal phase. The slip control gate is eliminated from the clock input line to the counter and instead is included in the feedback path which eliminates the skew problem and permits the equivalent of adding clock pulses without the requirement for logic speeds of twice the normal clock speed.

Abstract: A device for measuring the volume of flowing liquid with temperature compensation includes a device for generating a volume signal, a device for detecting the temperature of the fluid to generate a temperature signal, and an electronic computer for receiving the volume and temperature signals to calculate a compensated volume. A device is provided for setting the value of the specific gravity of the liquid so that the computer, which is stored with coefficients for compensating the volume of various liquids each having the respective specific gravity at a standard temperature, the specific gravity being varied depending on the liquid temperature, selects one of the coefficients with reference to the set specific gravity value and the temperature value and calculates the compensated volume per volume signal and outputs the latter to a displaying device.

Abstract: A system for automatic alignment of two pulses is disclosed. The disclosed system is particularly adapted to align the cathode current pulse supplied to a TWT amplifier with the RF exciter pulse so as to improve the efficiency of the TWT amplifier. The system includes a programmable delay circuit for selectively delaying the cathode current pulse after the system trigger. A pulse alignment signal indicates when the two pulses are in alignment. A system controller carries out a calibration algorithm to interatively change the delay while monitoring the alignment signal to determine the calibrated delay setting resulting in pulse alignment. The calibrated delay setting is then stored in memory, and is employed by the controller during the normal operation mode to adjust the programmable delay circuit to the calibrated value.

Abstract: A circuit for correcting for polygon drive motor velocity irregularities in a flying spot scanner is described. A crystal controlled oscillator is used to generate the system clock. As the motor speeds up, or slows down, pulses are subtracted, or added, to the stream of clock pulses so that the data bit stream will always occupy the same line length on the page regardless of polygon velocity variations.

Abstract: A missing pulse detector is disclosed in which the absence of a pulse in a variable frequency periodic pulse train is detected and distinguished from a reduction in the pulse repetition rate. Between successive pulse train pulses a first counter counts clock pulses at a first rate and develops a maximum count related to the time duration between successive pulses. This maximum count is maintained by a latch circuit during the next time duration between successive pulses and is compared with the count of a second pulse counter which counts clock pulses during successive pulse train pulses at a second rate normally less than the first incrementing rate. When the count of the second counter exceeds by a predetermined amount the latched count of the first counter, this indicates the occurrence of longer time duration and a count comparator and logic circuit provides an arming output signal.

Abstract: Constant-percent break interval pulse correctors insure that the break interval of a dial pulse subsists for a substantially constant percentage of the total pulse interval; i.e., break interval plus make interval. The constant-percent break interval pulse correction of the first pulse in a string of pulses is realized by employing an up/down counter which is controlled to count up at a first clock rate for a first predetermined interval from the beginning of the dial pulse, then to count down at a second clock rate for a second interval from the end of the first interval to the beginning of a subsequent dial pulse and then to count down at a third clock rate until a predetermined count is reached, e.g., zero. The second clock rate is the difference between the third and first clock rates. In one embodiment, proper correction of the last dial pulse in a string of dial pulses is realized by employing a plurality of such up/down counters.

Abstract: A fractional divider which functions as a prescaler in a phase lock loop-based frequency synthesizer provides a selectable prescaling factor to the divide-by-N programmable divider. The prescaling factor can assume either the value 2 or 2+1/N. The fractional division, occurring in front of the programmable divider, permits a periodic signal to be generated by that device, while recapturing the frequencies lost to prescaling. When operating in the divide-by-(2+1/N) mode, the fractional divider drops one input clock pulse each time the output signal of the programmable divider assumes a predetermined binary state.

Abstract: Characteristics of a pulse sequence, such as frequency, are controlled in a simple circuit without requirement for specific storage components. The cumulative effect of a sequence of control signals is maintained by providing a phase shift between a pair of waveforms. The phase shift between the waveforms is used to provide a number of control pulses to the circuit for varying the desired characteristic. In a particular embodiment, control signals are externally provided for varying the phase shift between two waveforms. In response to the phase variation, a number of control signals are provided for adding or deleting pulses to a pulse stream. The use of feedback control loops results in repeated addition and/or deletion of pulses to or from the pulse stream, thereby varying the output frequency in accordance with a one time input of the external control signals.

Abstract: New and improved method and apparatus for the correction of coincident errors attendant the automated detection and counting of mixed particles having detectable characteristics of different levels in particle counting applications wherein the detection of "dominant" particles under coincident particle conditions, renders undetectable the "dominated" particles, with resulting inaccuracy in the "dominated" particle count. Such inaccuracy is corrected by modifying the "dominated" particle count in accordance with the time duration of the signals which are generated attendant the detection of the "dominated" particles.

Abstract: A circuit for simulating the effects of a temperature change in a digital transmission medium. The circuit generates lengthened or shortened frequency pulses digitally by operating a pulse counter to reset early for a shortened pulse or skip a timing pulse for a lengthened interval pulse. A second counter and associated decoder are utilized to alternately control the operating modes.