Abstract: A shift register unit, a driving method, a drive circuit, and a display apparatus are disclosed. The shift register unit includes: a control circuit, which is configured to adjust signals of a first node and a second node according to an input signal end, a first control signal end, a second control signal end and a first reference signal end; a cascade circuit, which is configured to provide, according to the signal of the first node, a signal of a first cascade clock signal end to a cascade output end; and an output circuit, which is configured to provide, according to the signal of the first node, a signal of a control clock signal end to a drive output end, and provide, according to the signal of the second node, a signal of a second reference signal end to the drive output end.

Abstract: Provided are a display panel and a display device. The display panel includes multiple cascaded gate drive units. Each gate drive unit includes a shift register unit and an inverted unit. The inverted unit is electrically connected to the shift register unit. A scan output terminal of the shift register unit is electrically connected to one scan line. An inverted scan output terminal of the inverted unit is electrically connected to one inverted scan line. The scan output terminal of the shift register unit outputs a first effective pulse signal. The inverted scan output terminal of the inverted unit outputs a second effective pulse signal. A time period corresponding to the first effective pulse signal at least partially overlaps a time period corresponding to the second effective pulse signal, and the type of the first effective pulse signal is opposite to the type of the second effective pulse signal.

Abstract: An input receiver circuit for a signal line may receive inputs from other signal lines to mitigate crosstalk noise present on the signal line. In some examples, the input receiver circuit may include a transistor with a programmable width. In some examples, the input receiver circuit may include a bias current generator with a programmable current. The width and/or current may be programmed based on an amount of crosstalk noise introduced by the other signal line. In some examples, the input receiver circuit may include a resistance and/or a capacitance. In some examples the resistor and/or capacitor may be programmable. The resistance and/or capacitance may be programmed based on a duration of the crosstalk noise on the signal line.

Abstract: A light emitting display apparatus, which can sense a characteristic change of a transistor provided in a stage and supply a driving voltage, and which can compensate for the characteristic change, includes stages for supplying gate signals to gate lines provided in the light emitting display panel, and a controller for controlling a magnitude of a driving voltage to be transmitted to the stages by using sensing data received from the stages.

Abstract: Disclosed are a gate driver circuit having a reduced size, and a display device including the same. The gate driver circuit includes a plurality of stage circuits. Each stage circuit supplies a gate signal to each of gate lines arranged in a display panel, and includes a M node, a Q node, a QH node, and a QB node. Each stage circuit includes a gate signal output module configured to operate based on a voltage level of the Q node or a voltage level of the QB node to output first to j-th gate signals based on first to j-th scan clock signals or a first low-potential voltage.

Abstract: The embodiments of the present disclosure disclose a shift register unit and a method for driving the same, a gate driving circuit, and a display apparatus. The shift register unit includes: an input circuit configured to output an input signal from an input signal terminal to a pull-up node; an output circuit configured to output a clock signal from a clock signal terminal to an output signal terminal under control of a potential at the pull-up node; a resetting and de-noising circuit configured to reset and de-noise the pull-up node and the output signal terminal under control of a potential at a pull-down node; and a pull-down node control circuit coupled to a first voltage terminal and the pull-down node, and configured to electrically couple the pull-down node to the first voltage terminal under control of the potential at the pull-down node.

Abstract: A shift register unit, a gate drive circuit, a display panel, a display device and a driving method. The shift register unit includes a first input circuit, a second input circuit, a first output circuit, a second output circuit, a first reset circuit and a second reset circuit. The first input circuit is configured to control a level of a first node in response to a first input signal. The second input circuit is configured to control the level of the first node in response to a second input signal. The first output circuit is configured to output a first clock signal to a first output terminal under a control of the level of the first node. The second output circuit is configured to output a second clock signal to a second output terminal under the control of the level of the first node.

Abstract: Disclosed herein is a shift register circuit that is formed on an insulating substrate with thin film transistors having channels of the same conductivity type and includes shift stages, each of the shift stages including: a first thin film transistor; a second thin film transistor; a 3(1)-th thin film transistor; a 3(2)-th thin film transistor; a 4(1)-th thin film transistor; a 4(2)-th thin film transistor; a fifth thin film transistor; and a sixth thin film transistor.

Abstract: A shift register includes a pull-up control circuit, a pull-up circuit, a pull-down control circuit, a pull-down circuit, and a reset circuit. The pull-down circuit is connected to the pull-down node, the pull-up node, a second control terminal, a first voltage terminal, and a signal output terminal, and is configured to pull down potentials of the pull-up node and the signal output terminal to a potential of the first voltage terminal under the control of the pull-down node; moreover, the pull-down circuit is further configured to pull down potentials of the pull-up node and the signal output terminal to a potential of the first voltage terminal under the control of a signal from the second control terminal.

Abstract: The present disclosure provides a shifting register and a driving method thereof, a driving circuit, and a driving method of a panel. The shifting register includes: a shifting register unit circuit configured to transmit a signal of a first voltage terminal to an output terminal and an output control terminal according to a level of a pull-down node, and transmit a signal of a clock terminal to the output terminal and the output control terminal according to a level of a pull-up node; and a control unit circuit configured to transmit the signal of the first voltage terminal to the output terminal according to signals of a first control terminal and a second control terminal.

Abstract: A shift register including an input circuit, an output circuit, a first output control circuit, a second output control circuit, a reset circuit, a first reset control circuit, a second reset control circuit, and an energy-storing circuit. The first output control circuit is configured to transfer a clock signal present at a third clock signal terminal to a first node in response to the clock signal at the third clock signal terminal being active. The second output control circuit is configured to transfer a voltage present at a first voltage terminal to the first node in response to a clock signal at a fourth clock signal terminal being active.

Abstract: The embodiments of the present disclosure provide a shift register, a method for driving the same, and a gate driving circuit. A pull-down sub-circuit of the shift register is under the control of a third clock signal terminal and a fourth clock signal terminal, wherein signals of the third clock signal terminal and the fourth clock signal terminal are mutually inverted signals, and signal periods of the third clock signal terminal and the fourth clock signal terminal are a half of a signal period of a first clock signal terminal or a second clock signal terminal.

Abstract: A display device, a gate drive circuit, a shift register and its control method are described. The shift register includes: an input circuit, a first output circuit, a second output circuit, a control circuit and an output drive circuit, wherein the output drive circuit is connected to a second signal input terminal, a pull-up node, a control terminal of the second output circuit and a low voltage signal terminal, and is configured to write a voltage of the second signal input terminal into the control terminal of the second output circuit and superimpose a voltage of the pull-up node onto the control terminal of the second output circuit under the control of a second input signal provided at the second signal input terminal, such that the second output circuit is fully turned on to ensure that it has good output capability when working at a low temperature.

Abstract: A display apparatus includes a display panel configured to display an image. The display panel includes a plurality of gate lines and a plurality of data lines. A gate driving part is configured to output gate signals to the plurality of gate lines. A data driving part includes a plurality of channels configured to output data signals to the plurality of data lines. The plurality of channels is further configured to shift the data signals by M channel, where M is a positive integer, according to a driving mode selection signal for selecting a driving mode of the display panel.

Abstract: The present application discloses a pull down maintaining circuit, comprising: a first switch transistor, an input terminal is connected to a first direct current power source, and an output terminal outputting a scanning signal of the Nth level scanning line; a second switch transistor, an input terminal is connected to the first direct current power source, and an output terminal outputting a scanning electric level signal of the Nth level scanning line; a control unit for controlling the first and the second switch transistors to turn off in accordance with a low voltage outputted from the first and the second direct current power source, and the third direct current power source, and to control the first and the second switch transistors to normally turn on in accordance with a high voltage is outputted from the first and the second direct current power source, and the third direct current power source.

Abstract: Methods and circuitry for driving a device through drive cycles wherein each drive cycle has a plurality of drive stages are disclosed. An example of the circuitry includes an output for coupling the circuitry to the device and a plurality of drive slices coupled in parallel to the output. Control circuitry selectively activates individual drive slices in the plurality of drive slices during each stage of a drive cycle.

Abstract: A single block shifter design performing arithmetic and logical shift operations on input operands of multiple types is disclosed. The shifter design may be configurable and automatically generated to support multiple partition types including at least one of 80-bit, 40-bit, and 20-bit partition type. The shifter may also be configured and automatically generated to perform rotate operations on input operands. The shifter may include two stages where the first stage includes multiple multiplexers performing shift or rotate operations by one or more shift or rotate amounts without saturation, and the second stage includes multiple multiplexers performing operations with saturation. The shifter includes an inversion block to process signed and unsigned input data. A method of automatically generating the shifter design with an electronic design tool is also disclosed.

Abstract: A shift register unit, a gate driving apparatus and a display device are configured to solve the problem that a bi-directional scan function can not be realized in the prior art.

Abstract: A display device includes a first-stage output circuit adapted to perform output to a first-stage output signal line as an endmost output signal line out of a plurality of output signal lines disposed in parallel to each other, and the first-stage output circuit includes a start signal line to which a start signal for applying a conducting potential sequentially to the plurality of output signal lines is applied, a first clock signal line to which a first clock signal is applied, a second clock signal line to which a second clock signal is applied, a first transistor having a source to which the first-stage output signal line is connected, and a drain to which the first clock signal line is connected, and a second transistor having a gate to which the start signal line is connected.

Abstract: To provide a shift register unit, which comprises a positive control signal input terminal, a reverse control signal input terminal, a first thin film transistor, a second thin film transistor, a positive input terminal, a reverse input terminal, a pull-up module and a first reset module, a gate of the first thin film transistor is connected with the positive input terminal, a first electrode of the first thin film transistor is connected with the positive control signal input terminal, a second electrode of the first thin film transistor is connected with a pull-up node of the pull-up module, a gate of the second thin film transistor is connected with the reverse input terminal, a first electrode of the second thin film transistor is connected with the pull-up node of the pull-up module, a second electrode of the second thin film transistor is connected with the reverse control signal input terminal.

Abstract: Provided is a nonvolatile storage gate embedded logic circuit embedding a nonvolatile storage gate which can hold data after power supply cutoff and can cut off a power supply at the same time shifting into a standby state. The nonvolatile storage gate embedded logic circuit includes a logic calculation unit having a logic gate, and a nonvolatile storage gate having a nonvolatile storage element, a data interface control unit disposed so as to be adjoining to the nonvolatile storage element, and receiving a nonvolatile storage control signal for data read-out from the nonvolatile storage element and data write-in to the nonvolatile storage element, and a volatile storage element disposed so as to be adjoining to the nonvolatile storage element, receiving a data input signal and a clock signal, and outputting a data output signal.

Abstract: An active level shift (ALS) driver circuit and a liquid crystal display apparatus including the ALS driver circuit are disclosed. The ALS driver circuit includes an input unit configured to apply a first polarity voltage to a first node and to apply a second polarity voltage to a second node, a level compensation unit configured to adjust the voltages of the first node and the second node, and an output unit configured to alternately output a first power voltage and a second power voltage according to the adjusted voltages of the first and second nodes.

Abstract: A display device includes a first-stage output circuit adapted to perform output to a first-stage output signal line as an endmost output signal line out of a plurality of output signal lines disposed in parallel to each other, and the first-stage output circuit includes a start signal line to which a start signal for applying a conducting potential sequentially to the plurality of output signal lines is applied, a first clock signal line to which a first clock signal is applied, a second clock signal line to which a second clock signal is applied, a first transistor having a source to which the first-stage output signal line is connected, and a drain to which the first clock signal line is connected, and a second transistor having a gate to which the start signal line is connected.

Abstract: A shift register is configured so that each of first and second intermediate stages includes (i) a first input terminal supplied with a clock signal, (ii) a second input terminal supplied with a clock signal different in phase from the clock signal supplied to the first input terminal, (iii) an output terminal connected to the first input terminal via an output transistor, and (iv) a setting circuit, which is connected to the second input terminal and the output transistor, for setting an electric potential of a control terminal of the output transistor, the second intermediate stage includes a control circuit which is (i) connected to the setting circuit of the second intermediate stage and (ii) supplied with a control signal, an operation period (i) starts at a time when a shift start signal supplied to an initial stage is activated and (ii) ends at a time when an output of a final stage changes from activation to inactivation, and when the clock signal supplied to the first input terminal of the second int

Abstract: A stage circuit and a scan driver, the stage circuit including a switch unit configured to selectively electrically couple a first node to one of a first input terminal and a second input terminal, a first driver coupled to the first node, to a second node, to a third node, to a first clock terminal, and to a second clock terminal, and a second driver coupled to the second node, to the third node, to a third clock terminal, and to a common terminal, and configured to output a scan signal to an output terminal.

Abstract: A gate shift register and a display device using the same are disclosed. The gate shift register includes a plurality of stages that receive a plurality of gate shift clocks and sequentially output a scan pulse. A k-th stage of the plurality of stages includes a scan direction controller for converting a shift direction of the scan pulse in response to carry signals of previous stages input through first and second input terminals and carry signals of next stages input through third and fourth input terminals, a node controller for controlling charging and discharge operations of each of Q1, Q2, QB1, and QB2 nodes, a floating prevention unit for applying a low potential voltage to a gate electrode of a discharge TFT based on a voltage of the QB1 node or the QB2 node, and an output unit for outputting first and second scan pulses.

Abstract: An automated method is provided for designing an integrated circuit. A net list of an integrated circuit design is generated, wherein the net list includes a scan chain having a sequence of individual scan cells. A sequence of two or more individual scan cells of the scan chain is identified as a candidate for replacement by a custom shift array macro cell. The identified sequence of two or more individual scan cells is then replaced with a custom shift array macro cell that provides a functionally equivalent shift function as the replaced sequence of two or more individual scan cells. The custom shift array macro cell includes only two input pins and one output pin.

Abstract: Disclosed are a shift register, a gate driver and a display device, which relate the field of display technology and may eliminate the voltage coupled noise generated by a clock signal at an output terminal of the shift register effectively. The shift register comprises: a first input unit, a clock control unit, a second input unit, an inverting unit, a pulling-down unit and a first level selecting unit, a second level selecting unit, a third level selecting unit; the first input unit is connected with a first input signal terminal, the first level selecting unit and the second input unit, respectively, wherein a node at which the first input unit is connected with the second input unit is a pulling-up node, the first input unit is used for controlling a potential at the pulling-up node. The embodiments of the present disclosure may be applied to various display devices.

Abstract: A shift register unit and a gate drive device for a liquid crystal display are disclosed. Both gate and drain of the tenth thin film transistor are connected to the source of the fifth thin film transistor, a source thereof is connected to a low voltage signal input terminal, threshold voltages of the eighth thin film transistor and the ninth thin film transistor are equal to or less than threshold voltage of the tenth thin film transistor. The shift register unit and the gate drive device for liquid crystal display provided in the present invention, could enable the thin film transistor used to suppress the noise in the shift register unit to maintain turning on, therefore it guarantees the reliability of the shift register unit.

Abstract: A register file cell structure to enable lower voltage writes is disclosed. In one embodiment, a register file includes a state element made up of two cross-coupled inverters. Each of the inverters includes a p-channel metal oxide semiconductor (PMOS) transistor having a source terminal coupled to a virtual voltage node. One or more PMOS transistors are coupled in series between the virtual voltage node and a global voltage node. Each of the one or more PMOS transistors includes a gate terminal that is hardwired to a ground node, and thus these devices remain active when power is applied to the global voltage node. The presence of the one or more PMOS devices coupled between the virtual and global voltage nodes results in the ability to overwrite contents stored in the state element at lower voltages than otherwise attainable without the one or more PMOS devices.

Abstract: A shift register unit comprises: a first transistor, a pulling-up close unit, a pulling-up start unit, a first pulling-up unit, a second pulling-up unit, a trigger unit, and an output unit. A shift register circuit, an array substrate and a display device are also provided. The shift register unit, the shift register circuit, the array substrate and the display device can reduce drift of a gate threshold voltage of a gate line driving transistor and improve operation stability of devices.

Abstract: A configuration of logic elements enables existing Serial-In-Parallel-Out (SIPO) shift registers to perform their own bit count, report the receipt of a valid transmission consisting of an expected number of bits and report the receipt of an invalid transmission consisting of greater than the expected number of bits. Logic elements additional to the foregoing enable SIPO shift registers to receive valid transmissions of varying expected numbers of bits. Special purpose integrated circuits (ICs) are disclosed which also contain the aforementioned configurations of logic elements. Newly designed SIPO shift registers which contain within them the foregoing configurations of logic elements are further disclosed. Potential messages of multiple acceptable message lengths are accommodated. Some embodiments are equipped with tri-state data outputs.

Abstract: According to an embodiment, a gate shift register includes a plurality of stages cascade-connected to each other. An nth one of the stages includes: a pull-up transistor that outputs any one of gate shift clocks as an nth scan pulse of a gate high voltage in accordance with the potential of a Q node; a pull-down transistor that is connected to the pull-up transistor through an output node, and outputs a low-potential voltage as an nth scan pulse of a gate low voltage in accordance with the potential of a QB node; and a switching circuit that charges and discharges the Q node and the QB node, respectively, or vice versa in response to a set signal and a reset signal, wherein an adaptively adjusted variable high-potential voltage is applied to the QB node to correspond to a shift in the threshold voltage of the pull-down transistor.

Abstract: A configuration of logic elements enables existing Serial-In-Parallel-Out (SIPO) shift registers to perform their own bit count, report the receipt of a valid transmission consisting of an expected number of bits and report the receipt of an invalid transmission consisting of greater than the expected number of bits. Logic elements additional to the foregoing enable SIPO shift registers to receive valid transmissions of varying expected numbers of bits. Special purpose integrated circuits (ICs) are disclosed which also contain the aforementioned configurations of logic elements. Newly designed SIPO shift registers which contain within them the foregoing configurations of logic elements are further disclosed. Potential messages of multiple acceptable message lengths are accommodated. Some embodiments are equipped with tri-state data outputs.

Abstract: A shift register circuitry includes plurality stages of shift registers. An Nth stage shift register of the plurality stages of shift registers includes an input unit, an output unit, a control unit, a first pull-up unit, a second pull-up unit and a compensation circuit. The output unit is used to output an unmodified Nth stage scan signal. The input unit and the first pull-up unit are used to control the voltage level of a register control end. The control unit is used to receive a low reference voltage, a high reference voltage and the voltage level of the register control end, and control the voltage level of an output end of the control unit. The second pull-up unit is used to control the voltage level of an output end of the Nth stage shift register. The modification circuit is used to generate a modified Nth stage scan signal.

Abstract: Discussed herein is a shift register which is capable of stabilizing an output thereof. The shift register includes a plurality of stages for sequentially outputting scan pulses in such a manner that high durations of the scan pulses partially overlap with each other. Each of the stages includes a node controller for controlling a charging duration of a set node, and an output unit for outputting a corresponding one of the scan pulses through an output terminal for the charging duration of the set node.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a driving unit, an input unit, a driving adjustment unit and a pull-down unit. The driving unit is utilized for outputting a gate signal according to a system clock and a driving control voltage. The input unit is put in use for outputting the driving control voltage according to an input control signal and a first input signal. The driving adjustment unit is employed for adjusting the driving control voltage according to a second input signal and a third input signal. The pull-down unit is used for pulling down the gate signal and the driving control voltage according to a fourth input signal.

Abstract: A shift register apparatus including a first shift register cell is disclosed. The first shift register cell includes a first logic unit, a first control unit and a first output unit. The first logic unit generates a first control signal and a second control signal according to a start signal and a first setting signal. During a first period, the first control unit employs the first and second control signals to make a first clock signal update the first setting signal and the first output unit employs the first and second control signals to make a second clock signal update the first shifted signal. During a second period, the first output unit controls the first shifted signal according to the first and second control signals such that the first shifted signal does not follow the second clock signal.

Abstract: An exemplary shift register is adapted for receiving a preceding-stage output signal to generate a preceding-stage supply signal and outputting an input signal as an extreme value of a current-stage output signal according to the preceding-stage supply signal. The shift register includes an active controller, a voltage boosting circuit and an output circuit. The active controller receives the preceding-stage output signal and thereby produces an active control signal. The voltage boosting circuit receives a first operating voltage, the preceding-stage supply signal and the active control signal, and uses a capacitive coupling effect to change the voltage value of the preceding-stage supply signal and thereby generates an output control signal. The output circuit is electrically coupled to the voltage boosting circuit, the active controller and the input signal and determines the time of outputting the input signal as the extreme value according to the output control signal.

Abstract: Provided is a shift register circuit which includes: first through N-th circuit sections (1a, 1b) (N is an integer equal to or larger than 2) in each of which a plurality of shift register stages (SR1, SR2, . . . , SRn) are connected in cascade; and supply wires (10b, 10c, 10e, 10f). Each of the first through N-th circuit sections (1a, 1b) receives drive signals (CKA1, CKA2, CKB1, CKB2) for driving the shift register stages (SR1, SR2, . . . , SRn) via supply wires (10b, 10c, 10e, 10f) exclusive for the each of the first through N-th circuit sections (1a, 1b).

Abstract: A shift register circuit is provided that can decrease a power consumption caused by a clock signal and can achieve a high driving capacity. A unit shift register has a first transistor that activates an output signal when a power supply potential is provided to an output terminal. A pull-up driving circuit for driving the first transistor has a second transistor for providing a clock signal to a node connected to the gate of the first transistor and a boosting circuit for the node. When an output signal of a preceding stage is activated, the second transistor turns on. Thereafter, when the clock signal is activated, and the node is charged, the second transistor turns off. The boosting circuit increases the potential at the node when the second transistor turns off. Therefore, the first transistor can operate in non-saturation region and activate the output signal.

Abstract: In a shift register that operates based on four-phase clock signals, including two-phase clock signals that are provided to odd-order stages and two-phase clock signals that are provided to even-order stages, of which phases are shifted by 90 degrees from each other, a potential of a first clock appears as a potential of a scanning signal, when a potential of a first node is at a high level, in each stage. In this configuration, the potential of the first node included in each stage is set to a high level based on a pulse of a scanning signal outputted from a pre-stage, and is set to a low level based on a pulse of a scanning signal outputted from a third stage after a stage concerned.

Abstract: A shift register circuit is provided that can decrease a power consumption caused by a clock signal and can achieve a high driving capacity. A unit shift register has a first transistor that activates an output signal when a power supply potential is provided to an output terminal. A pull-up driving circuit for driving the first transistor has a second transistor for providing a clock signal to a node connected to the gate of the first transistor and a boosting circuit for the node. When an output signal of a preceding stage is activated, the second transistor turns on. Thereafter, when the clock signal is activated, and the node is charged, the second transistor turns off. The boosting circuit increases the potential at the node when the second transistor turns off. Therefore, the first transistor can operate in non-saturation region and activate the output signal.

Abstract: In a semiconductor circuit a floating node is set to any voltage by utilizing a control signal applied to a refresh terminal and has a period shorter than that of a clock signal. The circuit includes first and second transistors connected between a first clock terminal and first power supply terminal, third and fourth transistors connected between the refresh terminal and the first power supply terminal, and fifth and sixth transistors connected between a second power supply terminal and the first power supply. Gates of the fourth and fifth transistors are connected to an input terminal, a gate of the third transistor is connected to a second clock terminal, a gate of the first transistor is connected to a node between the fifth and sixth transistors, gates of the second and sixth transistors are connected, and a node between the first and second transistors is connected to an output terminal.

Abstract: A shift register circuit is provided that can decrease a power consumption caused by a clock signal and can achieve a high driving capacity. A unit shift register has a first transistor that activates an output signal when a power supply potential is provided to an output terminal. A pull-up driving circuit for driving the first transistor has a second transistor for providing a clock signal to a node connected to the gate of the first transistor and a boosting circuit for the node. When an output signal of a preceding stage is activated, the second transistor turns on. Thereafter, when the clock signal is activated, and the node is charged, the second transistor turns off. The boosting circuit increases the potential at the node when the second transistor turns off. Therefore, the first transistor can operate in non-saturation region and activate the output signal.

Abstract: A shift register circuit includes a plurality of shift registers. Each of the shift registers is configured for outputting a corresponding start-pulse signal and a corresponding driving-pulse signal. Each of the shift registers includes a pull-up circuit, a first driving circuit, a second driving circuit and a discharging circuit. The pull-up circuit is configured for charging a first node. The first driving circuit is configured for generating the corresponding start-pulse signal, and the second driving circuit is configured for generating the corresponding driving-pulse signal. The discharging circuit firstly discharges the first node before discharging an output terminal of the second driving circuit.

Abstract: Systems for displaying images are provided. A representative system incorporates a digital data sampling circuit with N stage data inputs. The first stage flip-flop outputs a first output signal. The second stage flip-flop outputs a second output signal. The first stage sample latch circuit receives digital data according to a first control signal. The first stage logic circuit comprises a first converter for inverting the second output signal and generating a first inverse logic signal, and generates the first control signal according to the first output signal and the first inverse logic signal.

Abstract: Provided is a shift register configured by cascade connecting unit circuits each including a bootstrap circuit. In at least one example embodiment, for the unit circuits, a time period during which a transistor is in an ON state and a clock signal is high level corresponds to a clock passing period. Among transistors whose one conduction terminal is connected to a gate of the transistor, channel lengths of transistors configured such that a low-level potential is fed to gates of the transistors to turn the transistors to an OFF state in the clock passing period and that a low-level potential is applied to the conduction terminal of the transistors in the clock passing period are made longer than the channel length of the transistor. With this, it is possible to reduce a leakage current in the clock passing period, and to prevent the fluctuation of a gate potential of the transistor and dullness in an output signal from occurring.

Abstract: A data driver for time-division multiplexing includes a first memory cell set having first memory cells, a second memory cell set having second memory cells, and a plurality of output lines. Each first memory cell is used for generating a first data signal in response to a first sampling control signal, and for outputting the first data signal in response to a first transmitting control signal. Each second memory cell is used for generating a second data signal in response to a second sampling control signal, and for outputting the second data signal in response to a second transmitting control signal. During a first line time period, the first sampling control signal is triggered while the second transmitting control signal is triggered. During a second line time period, the first transmitting control signal is triggered while the second sampling control signal is triggered.

Abstract: A semiconductor device includes a power-supply control portion and a latch portion. The power-supply control portion supplies power to an internal circuit in response to an input signal synchronized with rising of clock. The latch portion latches the input signal in synchronization with falling of the clock and supplies the latched input signal to the internal circuit.