Particular Input Circuit Patents (Class 377/70)
  • Patent number: 9035933
    Abstract: A display apparatus and a method for generating gate signal thereof are provided. The display apparatus includes a timing controller and a display panel. The timing controller is used for providing a plurality of timing signals. The display panel includes a pixel array and a gate drive circuit. The pixel array has a plurality of pixels. The gate drive circuit is electrically connected to the timing controller and the pixel array and including a plurality of shift register circuits. The shift register circuit includes a first shift register and a second shift register. The first shift register is configured for generating a corresponding primary gate signal. The second shift register is configured for generating a corresponding secondary gate signal. The timing controller adjusts overlapping relations of the timing signals according to a frame rate of the display apparatus.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: May 19, 2015
    Assignee: Au Optronics Corporation
    Inventors: Ya-Ting Lin, Yu-Chung Yang, Chun-Hsin Liu, Kun-Yueh Lin
  • Patent number: 8982033
    Abstract: A display device including various portions, circuits and other arrangements for outputting various pulses and triggers, for controlling forward shift and backward shift operations.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: March 17, 2015
    Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima
  • Publication number: 20150049854
    Abstract: Shift registers are provided. The shift register includes a first clock buffer and a second clock buffer. The first clock buffer inverts an input signal and a complementary input signal in response to a clock signal to generate a first output signal and a first complementary output signal. The second clock buffer inverts the first output signal and the first complementary output signal in response to the clock signal to generate a second output signal and a second complementary output signal.
    Type: Application
    Filed: February 3, 2014
    Publication date: February 19, 2015
    Applicant: SK hynix Inc.
    Inventor: Keun Soo SONG
  • Patent number: 8952880
    Abstract: A display panel drive circuit includes a shift register constructed of unit circuits connected in stages. The unit circuits generate signal line selection signals, respectively, which signal line selection signals are made active for a respective certain period of time to form a respective pulse, and the pulses are outputted successively from respective unit circuits in order of ordinal number starting from a first stage until an end stage. In at least one embodiment, each of the unit circuits receive (i) clock signals generated based on a sync signal received from outside of the display panel drive circuit, (ii) a start pulse signal generated based on the sync signal, or a signal line selection signal generated in a stage different from its own stage, and (iii) a clear signal. The clear signal is made active in a case where anomalousness is included in the sync signal, and no pulse is outputted from the shift register until a subsequent vertical scanning period starts.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: February 10, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takayuki Mizunaga, Hideki Morii, Akihisa Iwamoto, Masahiro Hirokane, Yuuki Ohta
  • Patent number: 8949493
    Abstract: Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: February 3, 2015
    Assignee: Altera Corporation
    Inventors: Curt Wortman, Chong H. Lee, Huy Ngo
  • Publication number: 20140355733
    Abstract: A stage circuit and a scan driver, the stage circuit including a switch unit configured to selectively electrically couple a first node to one of a first input terminal and a second input terminal, a first driver coupled to the first node, to a second node, to a third node, to a first clock terminal, and to a second clock terminal, and a second driver coupled to the second node, to the third node, to a third clock terminal, and to a common terminal, and configured to output a scan signal to an output terminal.
    Type: Application
    Filed: May 13, 2014
    Publication date: December 4, 2014
    Inventors: Yong-Jae Kim, Dong-Gyu Kim, Sung-Jae Moon
  • Patent number: 8803782
    Abstract: A bidirectional shift register outputs pulses from a plurality of cascaded unit register circuits in a shift order which is one of a forward direction and a reverse direction. A ?th stage of unit register circuit (38) has two set terminals connected to respective outputs of (??1)th and (?+1)th stages and two reset terminals connected to respective outputs of (?+2)th and (??2)th stages. The unit register circuit (38) sets, when a pulse is input to any one of the set terminals, a reference point N1 to an H level, and, when a pulse is input to any one of the reset terminals, N1 to an L level. The order of phase change of clock signals is reversed according to the direction of a shift, and whether a start trigger signal is applied to a top stage or a bottom stage is switched.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: August 12, 2014
    Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima
  • Patent number: 8803783
    Abstract: A plurality of cascaded unit register circuits which comprises a bidirectional shift register include main stages and dummy stages at the top before the main stages and dummy stages at the bottom after the main stages. A k-th stage outputs a pulse Pk in synchronization with a clock signal with a reference point N1 being at H level. The main stages include terminals NSF and NSB for setting N1 to H to which Pk?1 and Pk+1 are input, respectively, and terminals NRB and NRF for setting N1 to L level to which Pk?2 and Pk+2 are input, respectively. The order of generation of clock signals is reversed according to the direction of a shift, and whether a start trigger signal is applied to a top stage or a bottom stage is switched. Top dummy stages do not have NRB. Bottom dummy stages do not have NRF.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: August 12, 2014
    Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima
  • Patent number: 8773346
    Abstract: A driving device of a liquid crystal display (LCD) utilized for preventing noises of a clock signal from causing error operation of a shift register is disclosed. The driving device includes a shift register, a reception terminal, a noise elimination circuit and a control signal generation circuit. The reception terminal is utilized for receiving a first clock signal. The noise elimination circuit is coupled to the reception terminal, and is utilized for eliminating noises of the first clock signal and delaying the first clock signal for a preset time to generate a second clock signal. The control signal generation circuit is coupled to the reception terminal, the noise elimination circuit and the shift register, and is utilized for generating a first control signal and a second control signal to control the shift register.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: July 8, 2014
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Tung-Shuan Cheng, Yueh-Hsiu Liu, Kai-Shu Han
  • Patent number: 8692758
    Abstract: A display device of an embodiment of the present invention is a display device of an active matrix type, and includes a display driver supplied with image data included in serial data by serial transmission. The serial data has a first flag for specifying a polarity of voltage of a common electrode added thereto. The display driver generates, in accordance with a timing of a serial clock, a timing signal for a horizontal period for a data signal line driver, and a timing signal for a gate signal line driver. This realizes a display device capable of easily generating, within a driver IC, a timing signal for writing the image data in pixels.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: April 8, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Noboru Matsuda, Isao Takahashi, Takahiro Yamaguchi
  • Publication number: 20140079175
    Abstract: A shift register, a driving apparatus and a display. The shift register comprises: an evaluating unit for receiving a second clock signal and outputting an output signal to a signal output terminal under a control of an input signal; a reset controlling unit, a first terminal of which being connected to the evaluating unit and receiving the input signal, a second terminal of which receiving a first clock signal, a third terminal of which receiving a low level signal, for inputting a control signal to a reset unit under controls of the input signal and the first clock signal; the reset unit for receiving a high level signal and resetting the signal output terminal under a control of the control signal input by the reset controlling unit. When the shift register evaluates the output terminal, the gate of the reset transistor (4) is charged rapidly, which renders that the reset transistor (4) is turned off in time.
    Type: Application
    Filed: November 30, 2012
    Publication date: March 20, 2014
    Applicant: BOE Technology Group Co., Ltd.
    Inventor: Zhongyuan Wu
  • Patent number: 8669896
    Abstract: A method of controlling a successive-comparing-register analog-to-digital convertor (SAR ADC) is provided. Based upon the method, the SAR ADC receives a conversion clock that controls a conversion rate of the SAR ADC.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: March 11, 2014
    Assignee: Mediatek Inc.
    Inventors: Jen-Che Tsai, Chao-Hsin Lu
  • Publication number: 20140055334
    Abstract: A shifting register, a gate driving apparatus and a display apparatus comprising the shifting register.
    Type: Application
    Filed: November 12, 2012
    Publication date: February 27, 2014
    Applicants: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Hiagang Qing, Xiaojing Qi
  • Patent number: 8654226
    Abstract: A gated-clock shift register including a series of clocked flip-flops with preceding outputs connected to subsequent inputs as a horizontal digital shift register. Each flip-flop (or other state holding device) includes a clock buffer between the respective flip-flop's clock, and the global clock. Each clock buffer propagates the clock signal when it determines the associated flip-flop will have a state change during that clock cycle (e.g., via an XOR of the flip-flops input and output signals). In the absence of a state change, that buffer does not propagate the clock signal, essentially only clocking the relevant flip-flops. Further, the clock buffer may be implemented with only NMOS devices (or alternatively, only PMOS devices), which offers power savings over an otherwise required CMOS implementation.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: February 18, 2014
    Assignee: Analog Devices, Inc.
    Inventor: Steven Decker
  • Publication number: 20140044229
    Abstract: A shift register and a voltage adjusting circuit and method thereof are disclosed. The voltage adjusting circuit includes a first input terminal, a second input terminal, a transistor, a first capacitor, a second capacitor, and an output terminal. The first input terminal receives a second clock signal. The second input terminal receives a fourth clock signal. The transistor has a source electrode, a drain electrode, and a gate electrode. The source electrode is coupled to ground and the gate electrode is coupled to the second input terminal. The first capacitor is coupled between the drain electrode and the first input terminal. One end of second capacitor is coupled between the first capacitor and drain electrode, and the other end of second capacitor is coupled between the second input terminal and gate electrode. The output terminal is coupled between the first capacitor and drain electrode to output an adjusted voltage.
    Type: Application
    Filed: August 12, 2013
    Publication date: February 13, 2014
    Applicant: HannStar Display Corp.
    Inventors: Chien-Ting CHAN, Chung-Lin CHANG, Kuo-Sheng LEE
  • Patent number: 8614700
    Abstract: A voltage level shifter formed by single-typed transistors comprises two input terminals, two power supply terminals, a plurality of thin-film transistors, and an output terminal. Another voltage level shifter formed by single-typed transistors comprises two input terminals, an output terminal, two power supply terminals, two input units, a first thin-film transistor, a disable unit, a feedback unit, and a second thin-film transistor. The voltage level shifters are formed by single-typed TFTs. When integrating the voltage level shifters into a substrate of a TFT display, the manufacturing processes are simplified. Besides, power is saved.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: December 24, 2013
    Assignee: AU Optronics Corp.
    Inventor: Jian-Shen Yu
  • Patent number: 8558777
    Abstract: A gate driver, comprises a plurality of shift registers configured to output signals sequentially such that an Nth shift register is reset by an output signal of an (N+2)th shift register, wherein last, second last and third last shift registers are reset by a last output signal of the last shift register.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: October 15, 2013
    Assignee: LG Display Co., Ltd.
    Inventors: Yong Ho Jang, Binn Kim, Hyung Nyuck Cho
  • Patent number: 8552961
    Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a driving unit, an input unit, a driving adjustment unit and a pull-down unit. The driving unit is utilized for outputting a gate signal according to a system clock and a driving control voltage. The input unit is put in use for outputting the driving control voltage according to an input control signal and a first input signal. The driving adjustment unit is employed for adjusting the driving control voltage according to a second input signal and a third input signal. The pull-down unit is used for pulling down the gate signal and the driving control voltage according to a fourth input signal.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: October 8, 2013
    Assignee: AU Optronics Corp.
    Inventors: Yu-Chung Yang, Yung-Chih Chen
  • Publication number: 20130222220
    Abstract: An electro-optical device is configured to be capable of using a region of a gate line drive circuit efficiently and preventing rising speed of a gate line selection signal from decreasing (rising delay), and a shift register circuit is composed of a single conductivity type transistor which is suitable for the device. The gate line drive circuit including an odd driver to drive odd rows of a plurality of gate lines, and an even driver to drive even rows thereof. Each unit shift register in the odd and even drivers receives a selection signal in the second previous row and activates its own selection signal two horizontal periods later. A start pulse of the even driver is delayed in phase by one horizontal period with respect to a start pulse of the odd driver.
    Type: Application
    Filed: April 15, 2013
    Publication date: August 29, 2013
    Applicant: Mitsubishi Electric Corporation
    Inventor: Mitsubishi Electric Corporation
  • Patent number: 8497834
    Abstract: A signal output circuit of the present invention is provided in a unit stage of a shift register. The signal output circuit includes a set-reset flip-flop, and a signal generation circuit for generating an output signal by loading or blocking a clock signal in accordance with a signal inputted thereto. The signal output circuit is arranged such that: the signal generation circuit receives a signal outputted from the flip-flop and the output signal fed back to the signal generating circuit; and the output signal is fed back to a reset input of the flip-flop. This makes it possible to achieve a reduction in the area of the circuit and a simplification of the circuit.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: July 30, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Etsuo Yamamoto, Yuhichiroh Murakami, Eiji Matsuda
  • Patent number: 8427355
    Abstract: An analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: April 23, 2013
    Assignee: University of Macau
    Inventors: Sai-Weng Sin, Li Ding, Yan Zhu, He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Seng-Pan U, Rui Paulo da Silva Martins, Franco Maloberti
  • Patent number: 8390611
    Abstract: An image display system includes a gate driving circuit. The gate driving circuit includes several stages of gate drivers each for generating a gate driving signal to drive a row of pixels. Each stage of the gate driver receives a clock signal and a first reset signal. A first stage of the gate driver receives a vertical start pulse as an input signal of the first stage. The remaining stages of the gate drivers respectively receive the gate driving signal generated by a previous stage of the gate driver as the input signal of the remaining stages. Each stage of the gate drivers further receives the gate driving signal generated by a next stage of the gate driver as a second reset signal, and generates the corresponding gate driving signal according to the clock signal, the first reset signal, and the corresponding input signal and second reset signal.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: March 5, 2013
    Assignee: Chimei Innolux Corporation
    Inventors: Fu-Yuan Hsueh, Tzu-Yu Cheng
  • Patent number: 8344988
    Abstract: A signal output circuit of one embodiment of the present invention is provided in a unit stage of a shift register. The signal output circuit includes a set-reset flip-flop, and a signal generation circuit for generating an output signal by loading or blocking a clock signal in accordance with a signal inputted thereto. The signal output circuit is arranged such that: the signal generation circuit receives a signal outputted from the flip-flop and the output signal fed back to the signal generating circuit; and the output signal is fed back to a reset input of the flip-flop. This makes it possible to achieve a reduction in the area of the circuit and a simplification of the circuit.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: January 1, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Etsuo Yamamoto, Yuhichiroh Murakami, Eiji Matsuda
  • Patent number: 8345028
    Abstract: A driving circuit applied in an electronic display apparatus is provided. The driving circuit includes a first exchange circuit and a first buffer. The first buffer includes first and second input stages, a second exchange circuit and first and second output stages. The first exchange circuit selectively couples a first input signal and a first output signal outputted from the first output stage to one of the first and the second input stages; and selectively couples a second input signal and a second output signal outputted from the second output stage to the other of the first and the second input stages. The second exchange circuit selectively couples the first input stage to one of the first and the second output stages and selectively couples the second input stage to the other of the first and the second output stages.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: January 1, 2013
    Assignee: Raydium Semiconductor Corporation
    Inventors: Chih-Chuan Huang, Yu-Lung Lo, Hsin-Yeh Wu
  • Publication number: 20120328070
    Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.
    Type: Application
    Filed: September 6, 2012
    Publication date: December 27, 2012
    Applicant: AU Optronics Corp.
    Inventors: Chih-Ying Lin, Kun-Yueh Lin, Yu-Chung Yang, Kuo-Hua Hsu
  • Patent number: 8310432
    Abstract: A gate driving circuit having improved driving capability and maintaining reliability even after a prolonged period of use includes a shift register having a plurality of stages cascaded to one another, each of the plurality of stages including a pull-up unit, a pull-down unit, a discharging unit, and a holding unit, wherein at least one of the discharging unit and the holding unit includes an amorphous silicon thin film transistor and a polysilicon thin film transistor connected in parallel to each other.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: November 13, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Cheol Lee, Hyung-Guel Kim, Jin Jeon
  • Publication number: 20120044133
    Abstract: Each stage (Xi) of a shift register includes a first output transistor (M5), a first capacitor (C1), an input gate (M1), a first switching element (M2), a second switching element (M3), a third switching element (M4), and a fourth switching element (M6).
    Type: Application
    Filed: October 23, 2009
    Publication date: February 23, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masahiko Nakamizo, Masashi Yonemaru, Kenichi Ishii, Yasuaki Iwase
  • Patent number: 8023612
    Abstract: Disclosed are, inter alia, methods, apparatus, computer-storage media, mechanisms, and means associated with a shift register with a dynamic entry point, which may particularly useful for aligning skewed data. The dynamic entry shift register typically includes a series of storage elements, with multiplexers distributed between the storage elements. Each of the multiplexers is configured to select between: (a) the output signal of a previous storage element, and (b) the input signal. A control is configured to configure the multiplexers for a data signal applied as the input signal to induce an appropriate delay of the data signal as the output signal. The dynamic entry shift register can be scaled to accommodate a longer delay while still using only 2:1 multiplexers between stages in the dynamic entry shift register(s).
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: September 20, 2011
    Assignee: Cisco Technology, Inc.
    Inventors: Kenneth Michael Rose, Matthew Todd Lawson
  • Patent number: 7995049
    Abstract: A voltage level shifter formed by single-typed transistors comprises two input terminals, two power supply terminals, a plurality of thin-film transistors, and an output terminal. Another voltage level shifter formed by single-typed transistors comprises two input terminals, an output terminal, two power supply terminals, two input units, a first thin-film transistor, a disable unit, a feedback unit, and a second thin-film transistor. The voltage level shifters are formed by single-typed TFTs. When integrating the voltage level shifters into a substrate of a TFT display, the manufacturing processes are simplified. Besides, power is saved.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: August 9, 2011
    Assignee: Au Optronics Corp.
    Inventor: Jian-Shen Yu
  • Publication number: 20110182399
    Abstract: In a shift register circuit, a defective operation while an output signal is not outputted and a drive capability lowering while the output signal is outputted are prevented. A unit shift register comprises a first transistor for supplying a clock signal inputted to a first clock terminal to an output terminal, and the first transistor is driven by a drive circuit. A second transistor is connected between the gate of the first transistor and the output terminal and has a gate connected to the first clock terminal. The second transistor connects the gate of the first transistor to the output terminal based on the clock signal when the gate of the first transistor is at L (Low) level.
    Type: Application
    Filed: April 7, 2011
    Publication date: July 28, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Youichi Tobita
  • Patent number: 7934031
    Abstract: An asynchronous logic family of circuits which communicate on delay-insensitive flow-controlled channels with 4-phase handshakes and 1 of N encoding, compute output data directly from input data using domino logic, and use the state-holding ability of the domino logic to implement pipelining without additional latches.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: April 26, 2011
    Assignee: California Institute of Technology
    Inventors: Andrew M. Lines, Alain J. Martin, Uri Cummings
  • Patent number: 7899148
    Abstract: A shift register includes a plurality of stages, each of the stages generate an output signal, in sequence. Each of the shift register includes a present stage and a first capacitor. The present stage outputs an output signal based on one of a scan start signal and a carry signal of the previous stage. The first capacitor reduces a ripple component of the carry signal of the present stage which activates the next stage. Therefore, a carry signal having a reduced ripple component is supplied to the next stage, so that a transient current is intercepted at a transistor receiving the carry signal, which is arranged in the next stage, thus ensuring reliability of the shift register.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: March 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Jae Kang, Seoung-Bum Pyoun
  • Patent number: 7821509
    Abstract: A shift register capable of reducing power consumption is provided. The shift register includes: a clock signal supply line for supplying a clock signal; a plurality of selectors coupled to the clock signal supply line to generate driving signals in response to sampling signals; and a plurality of stages respectively coupled to the selectors to generate the sampling signals in response to the driving signals, wherein at least one of the selectors is adapted to generate at least one of the driving signals in response to a previous one of the sampling signals supplied from a previous one of the stages and a next one of the sampling signals supplied from a next one of the stages.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: October 26, 2010
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventor: Sang Moo Choi
  • Patent number: 7817770
    Abstract: A shift register for use in an LCD is disclosed. The shift register provides better gate driving signals with the lower coupling effect. The shift register includes two switches. The control node of the first switch is electrically coupled to the control node of the second switch. One end of the first switch receives a clock signal, and the other end of the first switch is electrically coupled to one end of the second switch. The other end of the second switch outputs a gate driving signal. Both of the two switches are controlled by a control signal.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: October 19, 2010
    Assignee: AU Optronics Corp.
    Inventors: Lee-Hsun Chang, Yu-Wen Lin, Jing-Ru Chen, Shu-Wen Cheng
  • Patent number: 7778379
    Abstract: A shift register apparatus is provided. The pull-down unit of each of the shift registers in the shift register apparatus is controlled by itself, previous, and next two shift registers to enhance the ability of pull-down and voltage regulating. Therefore, the circuit structure of each of the shift registers does not need to be designed a large compensation capacitor therein to substantially restrain the coupling noise effect caused by the clock signal, and thus permitting that each of the shift registers can be collocated with a small compensation capacitor to enhance the output capability thereof.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: August 17, 2010
    Assignee: Au Optronics Corporation
    Inventors: Yi-Suei Liao, Chien-Liang Chen, Chen-Lun Chiu, Hao-Chieh Lee, Kuan-Yu Chen
  • Patent number: 7773718
    Abstract: A shift register circuit includes a plurality of bit register units, coupled in series, for transferring an input signal among the plurality of bit register units to sequentially output the input signal to a plurality of data output terminals according to a control signal and a clock signal, wherein the number of the plurality of data output terminals is greater than that of the plurality of bit register units, and a control unit for generating the control signal to control transference of the input signal.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: August 10, 2010
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Tung-Shuan Cheng, Yueh-Hsiu Liu
  • Patent number: 7764761
    Abstract: A shift register apparatus and a method thereof are provided. The technique manner submitted by the present invention utilizes two NMOS transistors for pulling down the voltage level of the scan signals output by the shift registers within the shift register apparatus to the low level gate voltage, wherein one of the NMOS transistors is controlled by a control unit, and the other NMOS transistor is controlled by a clock signal or the inverted clock signal provided to the shift registers. Therefore, shifting amount of the threshold voltage of those NMOS transistors can trend to be flat, and the reliability of those NMOS transistors can be promoted. In addition, since only one control unit is needed to dispose in each shift register so that the layout area of whole shift register apparatus can be reduced, and the panel with narrow frame size also can be achieved by the present invention.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: July 27, 2010
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Chih-Jen Shih, Chun-Yuan Hsu, Che-Cheng Kuo, Chun-Kuo Yu
  • Patent number: 7760845
    Abstract: A shift register of the present disclosure switches on and off various transistors in order to reduce power consumption. A high input voltage source and a low input voltage source of the shift register are spaced apart from each other so as to reduce signal noise distortion between the voltage sources. The shift register may be employed in a liquid crystal display (LCD).
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: July 20, 2010
    Assignee: Innolux Display Corp.
    Inventors: Chien-Hsueh Chiang, Sz-Hsiao Chen
  • Publication number: 20100166136
    Abstract: A shift register circuit is provided that can decrease a power consumption caused by a clock signal and can achieve a high driving capacity. A unit shift register has a first transistor that activates an output signal when a power supply potential is provided to an output terminal. A pull-up driving circuit for driving the first transistor has a second transistor for providing a clock signal to a node connected to the gate of the first transistor and a boosting circuit for the node. When an output signal of a preceding stage is activated, the second transistor turns on. Thereafter, when the clock signal is activated, and the node is charged, the second transistor turns off. The boosting circuit increases the potential at the node when the second transistor turns off. Therefore, the first transistor can operate in non-saturation region and activate the output signal.
    Type: Application
    Filed: December 24, 2009
    Publication date: July 1, 2010
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Youichi TOBITA
  • Patent number: 7724864
    Abstract: A shift register includes a plurality of stages to output a plurality of output signals, in sequence. Each of the stages includes a driving part and a discharging part. The driving part outputs an output signal of a present stage based on one of a start signal and an output signal of a previous stage, and a clock signal. The discharging part discharges the output signal of the present stage. The discharging part includes a discharge transistor and an auxiliary transistor. The discharge transistor has a gate electrode receiving an output signal of a next stage. The auxiliary transistor has a gate electrode receiving the output signal of the next stage. The auxiliary transistor is electrically connected in series to the discharge transistor. Therefore, the chance of a malfunction is decreased, and image display quality of the display device is improved.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: May 25, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Beom-Jun Kim, Yu-Jin Kim, Byeong-Jae Ahn, Bong-Jun Lee
  • Patent number: 7697656
    Abstract: It is provided a method of controlling a shift register in which a plurality of transfer unit circuits, each having a storage unit and a writing unit, are connected in series. The storage unit has a hold gate and stores a logical level of a pulse when the hold gate is in an active state, and the writing unit has a writing gate and stores a pulse in the storage unit when the writing gate is in an active state.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: April 13, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Shigenori Katayama
  • Patent number: 7688933
    Abstract: A shift register circuit includes plural stages of signal holding circuits which are cascade-connected to hold a signal based on a supplied input signal, to output an output signal based on the held signal, and to supply the output signal as an input signal to a subsequent stage. Each of the plural stages of signal holding circuits includes an output circuit which is supplied with two types of clock signals consisting of a first clock signal and a second clock signal. A timing of the second clock signal is delayed by a predetermined delay time with respect to a timing of applying the input signal, which is supplied with a signal at a timing delayed by the delay time of the second clock signal from the timing of applying the input signal, and which outputs the output signal at a timing responsive to the first clock signal.
    Type: Grant
    Filed: January 25, 2007
    Date of Patent: March 30, 2010
    Assignee: Casio Computer Co., Ltd.
    Inventor: Katsuhiko Morosawa
  • Publication number: 20100074391
    Abstract: Disclosed are, inter alia, methods, apparatus, computer-storage media, mechanisms, and means associated with a shift register with a dynamic entry point, which may particularly useful for aligning skewed data. The dynamic entry shift register typically includes a series of storage elements, with multiplexers distributed between the storage elements. Each of the multiplexers is configured to select between: (a) the output signal of a previous storage element, and (b) the input signal. A control is configured to configure the multiplexers for a data signal applied as the input signal to induce an appropriate delay of the data signal as the output signal. The dynamic entry shift register can be scaled to accommodate a longer delay while still using only 2:1 multiplexers between stages in the dynamic entry shift register(s).
    Type: Application
    Filed: September 25, 2008
    Publication date: March 25, 2010
    Applicant: Cisco Technology, Inc., a corporation of California
    Inventors: Kenneth Michael Rose, Matthew Todd Lawson
  • Patent number: 7672420
    Abstract: A high voltage shift register stage which directly accepts low voltage clock signal inputs without using clock buffers. In particular, a shift register stage circuit is adapted to operate with a low voltage swing clock signal, with the stage circuit having a single state node, a, driven directly. This arrangement allows for reduced power consumption and higher operating speeds.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: March 2, 2010
    Assignee: Kopin Corporation
    Inventors: Frederick P. Herrmann, Kun Zhang
  • Patent number: 7672419
    Abstract: A pre-charge circuit includes a receiving module, an enabling module, and a reset module. The receiving module receives the received driving signal of the pre-charge circuit and outputs the receiving driving signal according to a control signal. The enabling module outputs a pre-charge signal when receiving the driving signal. The reset module is electrically coupled between the receiving module and the enabling module for receiving a reset signal to reset the pre-charge signal.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: March 2, 2010
    Assignee: AU Optronics Corp.
    Inventor: Chung-Chun Chen
  • Patent number: 7664218
    Abstract: A shift register includes a first transistor supplying an output terminal with a clock signal input to a first clock terminal and a second transistor discharging the output terminal. Defining the gate node of the first transistor as a first node, and the gate node of the second transistor as a second node, the shift register includes an inverter circuit in which the first node serves as its input node and a capacitive element serves as a load, and a buffer circuit receiving the output from the inverter circuit and outputting a signal to the second node.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: February 16, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventor: Youichi Tobita
  • Patent number: 7590214
    Abstract: A shift register and a shift register apparatus are provided. The shift register includes a plurality of shift register apparatus, and each shift register apparatus comprises a pre-charge circuit, a pull-up circuit and a pull-down circuit. The pre-charge circuit is used for sampling an input signal according to a first clock signal and a second clock signal respectively and generate a first charging signal and a second charging signal respectively. The pull-up circuit is coupled to the pre-charge circuit. The pull-up circuit receives the third clock signal and the first charging signal to output an output signal accordingly. The pull-down circuit is coupled to the pre-charge circuit and the pull-up circuit. The pull-down circuit receives the fourth clock signal and the second charging signal to decide whether to couple the output signal to a common potential.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: September 15, 2009
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Chin-Wei Liu, Ya-Hsiang Tai
  • Publication number: 20090202033
    Abstract: A high voltage shift register stage which directly accepts low voltage clock signal inputs without using clock buffers. In particular, a shift register stage circuit is adapted to operate with a low voltage swing clock signal, with the stage circuit having a single state node, a, driven directly. This arrangement allows for reduced power consumption and higher operating speeds.
    Type: Application
    Filed: April 8, 2009
    Publication date: August 13, 2009
    Applicant: Kopin Corporation
    Inventors: Frederick P. Herrmann, Kun Zhang
  • Patent number: 7573971
    Abstract: A shift register circuit has a plurality of shift registers connected in series, each shift register having a phase-shifting element and a pull-high element, wherein the phase-shifting element receives a first input signal, a first clock signal and a second clock signal, and the first clock signal and the second clock signal are complementary in phase. The pull-high element is used for pulling up an output signal to a high logic level, and includes a logic unit, wherein no current path is established in the pull-high element when the shift register is operated in any type of periods.
    Type: Grant
    Filed: May 2, 2007
    Date of Patent: August 11, 2009
    Assignees: Chi Mei Optoelectronics Corp., Chi Mei El Corporation
    Inventors: Ming-Chun Tseng, Hong-Ru Guo, Chien-Hsiang Huang
  • Patent number: RE43850
    Abstract: As multiphase clocks to be supplied to a first gate driver that drives odd-numbered scanning lines in a liquid crystal display region and a second gate driver that drives even-numbered scanning lines, clocks, which are effective within an effective period of the image signal just before an image signal starts to be supplied to display elements for each scanning line of the liquid crystal display region, is generated and the first and second gate drivers drive switching elements in the effective period of the clock.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: December 11, 2012
    Assignee: Onanovich Group AG, LLC
    Inventor: Koji Kikuchi