Abstract: A method for enhancing read performance in a multi-reader two-dimensional magnetic recording system comprising first and second readers includes: receiving first and second analog read signals from the first and second readers, respectively; sampling the first and second analog read signals to generate first and second sampled signals, respectively, each of the first and second sampled signals comprising an integer component, indicative of a value of a corresponding one of the first and second analog read signals, respectively, at an integer multiple of a corresponding sampling period associated therewith, and/or a fractional component, indicative of a value of the corresponding one of the first and second analog read signals, respectively, at an arbitrary point in time between integer multiples of the corresponding sampling period; and combining the integer and/or fractional components of the respective first and second sampled signals to thereby generate a reader offset estimation signal.

Abstract: Methods and apparatus are provided for supporting a variable-length transport packet in a audio and video communication system. Data to be transmitted through a transport packet is determined. A header of the transport packet is generated. The header includes a start sync signal. When a length of the transport packet exceeds a reference size, at least one intermediate sync signal is inserted into the transport packet according to a pre-defined interval. The transport packet is transmitted.

Abstract: An electronic circuit (300) includes a signal processing circuit (310) including first and second signal processing blocks (310.1, 310.3) coupled in cascade, a memory circuit (320) coupled to and adjustable between the first and second signal processing blocks (310.1, 310.3), the memory circuit (320) having memory spaces, the memory circuit (320) configurable to establish a trade-off of the memory spaces between the first and second signal processing blocks (310.1, 310.3), and a configuring circuit (330) operable to configure the trade-off of the memory spaces of the memory circuit (320).