Registration Or Layout Process Other Than Color Proofing Patents (Class 430/22)
  • Patent number: 9719163
    Abstract: A method of manufacturing a deposition mask is disclosed. In one aspect, the method includes depositing a first photoresist layer on a substrate, aligning a first photomask over the first photoresist layer and developing the first photoresist layer to form a plurality of first photoresist patterns having sides that gradually narrow toward the substrate. The method also includes forming a metal layer over the first photoresist patterns and a portion of the substrate exposed by the first photoresist patterns, depositing a second photoresist layer over the metal layer and aligning a second photomask over the second photoresist layer and developing the second photoresist layer to form a plurality of second photoresist patterns between the first photoresist patterns. The method further includes etching the metal layer to form a pattern hole, removing the first and second photoresist patterns and separating the substrate so as to form a deposition mask.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: August 1, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jeongwon Han
  • Patent number: 9709902
    Abstract: A projection exposure tool for microlithography for imaging mask structures of an image-providing substrate onto a substrate to be structured includes a measuring apparatus configured to determine a relative position of measurement structures disposed on a surface of one of the substrates in relation to one another in at least one lateral direction with respect to the substrate surface and to thereby simultaneously measure a number of measurement structures disposed laterally offset in relation to one another.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: July 18, 2017
    Assignee: Carl Zeiss SMT GmbH
    Inventors: Jochen Hetzler, Aksel Goehnermeier
  • Patent number: 9666537
    Abstract: Methods and apparatus for front-to-back alignment using narrow scribe lines are disclosed. An apparatus is disclosed that includes a semiconductor wafer comprising a plurality of areas for the fabrication of integrated circuit devices on a device side, the integrated circuit devices arranged in rows and columns and spaced from one another by a plurality of scribe lines disposed on the semiconductor wafer in areas between the integrated circuit devices and free from integrated circuit devices; and one or more alignment marks disposed on the semiconductor wafer, the alignment marks positioned in an intersection of two of the scribe lines; wherein the scribe lines have a first minimum dimension and the one or more alignment marks have a second minimum dimension that is greater than the first minimum dimension. Methods and additional apparatus are disclosed.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: May 30, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Simon Y S Chang, Arnold C. Conway
  • Patent number: 9659873
    Abstract: The present invention provides a semiconductor structure comprising a wafer and an aligning mark. The wafer has a dicing region which comprises a central region, a middle region surrounds the central region, and a peripheral region surrounds the middle region. The aligning mark is disposed in the dicing region, wherein the alignment mark is a mirror symmetrical pattern. The aligning mark comprises a plurality of second patterns in the middle region and a plurality of third patterns disposed in peripheral region, wherein each third pattern comprises a plurality of lines, and a width of the line is 10 times less than a width of the L-shapes. The present invention further provides a method of forming the same.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: May 23, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ying-Chiao Wang, Yu-Hsiang Hung, Chao-Hung Lin, Ssu-I Fu, Chih-Kai Hsu, Jyh-Shyang Jenq
  • Patent number: 9646902
    Abstract: Among other things, one or more systems and techniques for scanner alignment sampling are provided. A set of scan region pairs are defined along a periphery of a sampling area associated with a semiconductor wafer. Alignment marks are formed within scan regions of the set of scan region pairs, but are not formed within other regions of the sampling area. In this way, scan region pairs are scanned to determine alignment factors for respective scan region pairs. An alignment for the sampling area, such as layers or masks used to form patterns onto such layers, is determined based upon alignment factors determined for the scan region pairs.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: May 9, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Lee Yung-Yao, Ying Ying Wang, Yi-Ping Hsieh
  • Patent number: 9627558
    Abstract: Methods and apparatuses for manufacturing self-aligned integrated back contact heterojunction solar cells are provided. In some embodiments, systems for forming a solar cell on a substrate are provided, the systems comprising: a master shadow mask positioned adjacent to the substrate on a first side of the master shadow mask; a first blocking mask placed adjacent to a second side of the master shadow mask; and a deposition machine that deposits material on the substrate through holes in the master shadow mask and the first blocking mask.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: April 18, 2017
    Assignee: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Clarence J. Tracy, Stanislau Herasimenka
  • Patent number: 9613174
    Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: William Wu Shen, Yun-Han Lee, Chin-Chou Liu, Hsien-Hsin Lee, Chung-Sheng Yuan, Chao-Yang Yeh, Wei-Cheng Wu, Ching-Fang Chen
  • Patent number: 9606461
    Abstract: The present invention provides a measuring apparatus for measuring a position of an alignment mark formed on a substrate and including a first mark having position information in a first direction and a second mark having position information in a second direction different from the first direction, the apparatus including a detector configured to detect an image of the alignment mark, a controller configured to control movement of a stage for holding the substrate and detection by the detector, and a processor configured to obtain a position of the alignment mark whose image is detected by the detector, wherein the controller is configured to cause the detector to detect the image of the alignment mark with the stage moving in the first direction, and cause the detector to detect the image of the alignment mark with the stage moving in the second direction.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: March 28, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Tadaki Miyazaki
  • Patent number: 9599887
    Abstract: A photo mask includes a pre-alignment key used in a pre-alignment process performed in a photolithography apparatus. The pre-alignment key includes a pre-alignment pattern including a light transmitting area and a light blocking area surrounding the pre-alignment pattern. The light blocking area includes a plurality of light blocking patterns and a diffraction grating pattern separating the plurality of light blocking patterns from each other.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: March 21, 2017
    Assignee: SK HYNIX INC.
    Inventor: Byung Ho Nam
  • Patent number: 9601459
    Abstract: Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: March 21, 2017
    Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU Leuven R&D
    Inventors: Vikas Dubey, Ingrid De Wolf, Eric Beyne
  • Patent number: 9594314
    Abstract: The exposure apparatus includes a first detector, a first alignment unit, a second detector, and a second alignment unit, and a controller, wherein the controller controls the second alignment unit so that alignment of a substrate is conducted based on a detection result from detection of the mark by the second detector in a first view when alignment of the substrate can be conducted by the first alignment unit at a prescribed alignment accuracy, and controls the second alignment unit so that alignment of the substrate is conducted based on a detection result from detection of the mark by the second detector in a second view that is wider than the first view when alignment of the substrate cannot be conducted by the first alignment unit at the prescribed alignment accuracy.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: March 14, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Takashi Ogura
  • Patent number: 9568831
    Abstract: A lithographic or exposure apparatus has a projection system and a controller. The projection system includes a stationary part and a moving part. The projection system is configured to project a plurality of radiation beams onto locations on a target. The locations are selected based on a pattern. The controller is configured to control the apparatus to operate in a first mode or a second mode. In the first mode the projection system delivers a first amount of energy to the selected locations. In the second mode the projection system delivers a second amount of energy to the selected locations. The second amount of energy is greater than the first amount of energy.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: February 14, 2017
    Inventors: Patricius Aloysius Jacobus Tinnemans, Arno Jan Bleeker
  • Patent number: 9559266
    Abstract: The invention relates to an illumination device (1) specifically a packaged LED (2), which is embedded in a casing body leaving the bottom side of the LED (2) exposed; on the bottom side, a contacting element (7) is vacuum deposited onto the LED (2), which contacting element protrudes laterally above the LED (2) and allows on a macroscopic level for an electric contacting of the LED (2), namely by connection of flat surfaces, such as welding.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: January 31, 2017
    Assignee: OSRAM GMBH
    Inventors: Ralph Wirth, Axel Kaltenbacher
  • Patent number: 9543223
    Abstract: A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated in the first layer and corresponding ones of the subset of second overlay marks generated in the second layer.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: January 10, 2017
    Assignee: Qoniac GmbH
    Inventor: Boris Habets
  • Patent number: 9529271
    Abstract: The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chuan Wang, Burn Jeng Lin, Jaw-Jung Shin, Pei-Yi Liu, Shy-Jay Lin
  • Patent number: 9523910
    Abstract: The present invention relates to a nanoimprint lithography method.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: December 20, 2016
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sebastien Pauliac, Stefan Landis
  • Patent number: 9442392
    Abstract: A method of processing first and second semiconductor wafers is provided. Each of the first and second semiconductor wafers has a first layer and a second layer over the first layer. A first lithographic process is performed on the first layer over the first semiconductor wafer using a first inter-field correction and a first intra-field correction. An overlay error of the first lithographic process is determined. A second inter-field correction and a second intra-field correction are computed based on the first inter-field correction, the first intra-field correction, and the measured overlay error. A second lithographic process is performed on the second layer over the second semiconductor wafer, based on the second inter-field correction and the second intra-field correction.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: September 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Di Tsen, Yi-Ping Hsieh, Chen-Yen Huang, Shin-Rung Lu, Jong-I Mou
  • Patent number: 9442370
    Abstract: An imprinting method of this disclosure includes supplying an imprint material on a substrate having a pattern including a mark on the substrate formed thereon; bringing a mold having a pattern including a mark on the mold into contact with the imprint material; curing the imprint material in a state in which the mold is in contact therewith; and forming a pattern including the mark on the imprint material, and characterized in that an optical system configured to form an image of the mark on the imprint material and an image of the mark on the substrate are used to detect the mark on the imprint material and the mark on the substrate after the space between the substrate and the mold has been increased until the mark on the mold is positioned out of a focal depth of the optical system, thereby obtaining a relative positional deviation between the pattern on the substrate and the pattern on the imprint material.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: September 13, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroshi Sato, Mitsuru Hiura
  • Patent number: 9442393
    Abstract: A projection exposure tool for microlithography for imaging mask structures of an image-providing substrate onto a substrate to be structured includes a measuring apparatus configured to determine a relative position of measurement structures disposed on a surface of one of the substrates in relation to one another in at least one lateral direction with respect to the substrate surface and to thereby simultaneously measure a number of measurement structures disposed laterally offset in relation to one another.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: September 13, 2016
    Assignee: Carl Zeiss SMT GmbH
    Inventors: Jochen Hetzler, Aksel Goehnermeier
  • Patent number: 9410897
    Abstract: The present invention provides a film edge detecting method and a film edge detecting device. The film edge detecting method is used for detecting a film edge of a film layer formed on a substrate, the film layer comprises a patterned film layer, the method includes: forming at least one scale pattern in the patterned film layer, a film edge of the patterned film layer corresponding to an edge of the scale pattern; obtaining a patterned film edge indication value of the edge of the scale pattern; and obtaining a second distance, which is a distance between the film edge of the non-patterned film layer and a corresponding edge of the substrate, based on the non-patterned film edge indication value and a preset reference value of the corresponding edge of the substrate.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: August 9, 2016
    Assignees: BOE Technology Group Co., Ltd., Beijing BOE Display Technology Co., Ltd.
    Inventors: Shoukun Wang, Huibin Guo, Yuchun Feng, Liangliang Li, Xiaoxiang Zhang, Zongjie Guo
  • Patent number: 9411222
    Abstract: A photo-mask for use in extreme ultraviolet (EUV) lithography, in which the photo-mask has low coefficient of thermal expansion and high specific stiffness.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: August 9, 2016
    Assignee: Zygo Corporation
    Inventor: Marc Tricard
  • Patent number: 9400434
    Abstract: An exposure apparatus includes a controller configured to control scanning of an original holding unit and a substrate holding unit to expose a first pattern forming area onto a plurality of second pattern forming areas formed in advance on the substrate. The first pattern forming area is superimposed on the plurality of second pattern forming areas. An original may include the first pattern forming area in plural. The controller is configured to change the operation of the original holding unit or the substrate holding unit among the plurality of second pattern forming areas based on a state of the second pattern forming areas or a state of the first pattern forming areas while the first pattern forming areas are scanning-exposed onto the plurality of second pattern forming areas in a single scanning between the original holding unit and the substrate holding unit.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: July 26, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tsutomu Takenaka, Kazuhiko Mishima
  • Patent number: 9390926
    Abstract: Embodiments described herein relate to apparatus and methods of thermal processing. More specifically, apparatus and methods described herein relate to laser thermal treatment of semiconductor substrates by increasing the uniformity of energy distribution in an image at a surface of a substrate.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: July 12, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jiping Li, Aaron Muir Hunter, Bruce E. Adams, Kim Vellore, Samuel C. Howells, Stephen Moffatt
  • Patent number: 9377680
    Abstract: Provided is an integrated circuit (IC) testline layout. The layout has a device boundary and a main pattern boundary inside the device boundary. The layout includes at least one main pattern inside the main pattern boundary. The layout further includes a plurality of dummy patterns in a region that is between the main pattern boundary and the device boundary. The plurality of dummy patterns is printable in a photolithography process and is arranged in a ring with a uniform spacing between two adjacent dummy patterns.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Fan Chen, Tung-Heng Hsieh, Chin-Shan Hou, Yu-Bey Wu
  • Patent number: 9373183
    Abstract: Systems, methods, and devices for reducing an occlusion in an image are described herein. For example, one or more embodiments include a method including providing image information from a first image taken from a light field camera, analyzing image information from multiple sub-aperture images extracted from the image information of the first image to separate foreground and background appearance information, creating a mask of an occlusion based on the separated foreground and background appearance information, and rendering a second, modified image where the mask has been applied to reduce the occlusion in the modified image.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: June 21, 2016
    Assignee: Honeywell International Inc.
    Inventor: Scott McCloskey
  • Patent number: 9364856
    Abstract: A method of coating a workpiece is provided. In the method, a coating device is provided. The coating device includes a transparent covering plate and an ultraviolet light source device. The workpiece is placed in the coating device. Coating material is injected into the coating device to coat the workpiece. The coating material is ultraviolet light curable material. The ultraviolet light source device emits ultraviolet light and the ultraviolet light passes through the transparent covering plate to cure the coating material on the workpiece. The workpiece is taken out of the coating device.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: June 14, 2016
    Assignee: ScienBiziP Consulting(Shenzhen) Co., Ltd.
    Inventors: Feng-Yuen Dai, Jih-Chen Liu, Hung-Lien Yeh, Han-Lung Lee, Shun-Chi Tseng, Hung-Chun Ma
  • Patent number: 9366637
    Abstract: A method for establishing distortion properties of an optical system in a microlithographic measurement system is provided. The optical system has at least one pupil plane, in which the distortion properties of the optical system are established on the basis of measuring at least one distortion pattern, which the optical system generates when imaging a predetermined structure in an image field. The distortion properties of the optical system are established on the basis of a plurality of measurements of distortion patterns, in which these measurements differ from one another in respect of the intensity distribution present in each case in the pupil plane.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: June 14, 2016
    Assignee: Carl Zeiss SMS GmbH
    Inventor: Mario Laengle
  • Patent number: 9360773
    Abstract: A mark detecting method of detecting a notch as a mark formed on the outer circumference of a wafer held on a holding table. The mark detecting method includes the steps of index-rotating the holding table to image at least three points on the outer circumference of the wafer and to thereby detect the coordinates at the three points on the outer circumference of the wafer, calculating the center of the wafer from the coordinates at the three points, centering the wafer with respect to the holding table, and continuously rotating the holding table through 360° to image the whole of the outer circumference of the wafer by using a minimum imaging area corresponding to the outer circumference of the wafer and to thereby detect the angle where the notch is located.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: June 7, 2016
    Assignee: Disco Corporation
    Inventor: Nobuyuki Fukushi
  • Patent number: 9354527
    Abstract: In an overlay displacement amount measuring method according to an embodiment, a temperature distribution of a substrate during a pattern forming process and a temperature distribution of the substrate during a measuring process for measuring a positional displacement amount between patterns on the substrate by an electron microscope are measured. An expansion/contraction amount of the substrate between two processes is calculated based upon the two temperature distributions, and the positional displacement amount is corrected based upon the expansion/contraction amount. An overlay displacement amount between the pattern and a pattern formed on a layer different from the pattern is measured by an optical measuring apparatus, and the overlay displacement amount is corrected based upon the corrected positional displacement amount.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: May 31, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidenori Sato, Nobuhiro Komine
  • Patent number: 9355964
    Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Chou, Sheng-Chau Chen, Chun-Wei Chang, Kai-Chun Hsu, Chih-Yu Lai, Wei-Cheng Hsu, Hsiao-Hui Tseng, Shih Pei Chou, Shyh-Fann Ting, Tzu-Hsuan Hsu, Ching-Chun Wang, Yeur-Luen Tu, Dun-Nian Yaung
  • Patent number: 9329033
    Abstract: Aspects of the present disclosure describe systems and methods for calibrating a metrology tool by using proportionality factors. The proportionality factors may be obtained by measuring a substrate under different measurement conditions. Then calculating the measured metrology value and one or more quality merits. From this information, proportionality factors may be determined. Thereafter the proportionality factors may be used to quantify the inaccuracy in a metrology measurement. The proportionality factors may also be used to determine an optimize measurement recipe. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 3, 2016
    Assignee: KLA-Tencor Corporation
    Inventors: Eran Amit, Dana Klein, Guy Cohen, Amir Widmann, Nimrod Shuall, Amnon Manassen, Nuriel Amir
  • Patent number: 9329488
    Abstract: The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: May 3, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chuan Wang, Shy-Jay Lin, Pei-Yi Liu, Jaw-Jung Shin, Burn Jeng Lin
  • Patent number: 9291916
    Abstract: A substrate is loaded onto a substrate support of a lithographic apparatus, after which the apparatus measures locations of substrate alignment marks. These measurements define first correction information allowing the apparatus to apply a pattern at one or more desired locations on the substrate. Additional second correction information is used to enhance accuracy of pattern positioning, in particular to correct higher order distortions of a nominal alignment grid. The second correction information may be based on measurements of locations of alignment marks made when applying a previous pattern to the same substrate. The second correction information may alternatively or in addition be based on measurements made on similar substrates that have been patterned prior to the current substrate.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: March 22, 2016
    Assignee: ASML Netherlands B.V.
    Inventors: Stefan Cornelis Theodorus Van Der Sanden, Richard Johannes Franciscus Van Haren, Hubertus Johannes Gertrudus Simons, Remi Daniel Marie Edart, Xiuhong Wei, Irina Lyulina, Michael Kubis
  • Patent number: 9291903
    Abstract: The present invention provides a method of forming a detection mark from line patterns formed on a substrate, including a first step of deciding a first region for forming the detection mark on the substrate, and a second region which surrounds the first region and in which formation of the detection mark is forbidden, and a second step of projecting, onto the substrate by a projection optical system, patterns including a first cut pattern for partially cutting the line pattern in the first region to form a plurality of mark elements, and a removal pattern for removing the line pattern in the second region, and forming the detection mark including the plurality of mark elements.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: March 22, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Koichiro Tsujita
  • Patent number: 9275919
    Abstract: The present invention discloses a test method for monitoring the stability of process and a test module device thereof. The test module device comprises: a substrate, a certain number of the first metal wires, a certain number of the second metal wires, an insulating block is disposed between the adjacent first metal wires. The method comprises: a preconfigured value of the test current in the test module is provided in the process; the multiple test module devices are provided. The present invention adopts a method adopting an offset to set the upper metal wire and lower metal wire in the test module instead of regular equal interval setting. Consequently, the safety zone of the overlay in the process can be determined. The present invention can monitor the stability of the process.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: March 1, 2016
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventor: YuYu Zhou
  • Patent number: 9261798
    Abstract: A substrate stage is used in a lithographic apparatus. The substrate stage includes a substrate table constructed to hold a substrate and a positioning device for in use positioning the substrate table relative to a projection system of the lithographic apparatus. The positioning device includes a first positioning member mounted to the substrate table and a second positioning member co-operating with the first positioning member to position the substrate table. The second positioning member is mounted to a support structure. The substrate stage further comprises an actuator that is arranged to exert a vertical force on a bottom surface of the substrate table at a substantially fixed horizontal position relative to the support structure.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: February 16, 2016
    Assignee: ASML Netherlands B.V.
    Inventors: Yang-Shan Huang, Theodorus Petrus Maria Cadee
  • Patent number: 9262577
    Abstract: A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks. The method identifies, as a safe independent node, any independent node not closer than a threshold distance from any other independent nodes in another odd loop of the layout. The layout is modified, if the circuit patterns in the layout include any odd loop without any safe independent node, so that that after the modifying, each odd loop has at least one safe independent node.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huang-Yu Chen, Tsong-Hua Ou, Ken-Hsien Hsieh, Chin-Hsiung Hsu
  • Patent number: 9256121
    Abstract: The general inventive concepts relate to the field of display technology, and provide a mask plate and a method for producing a substrate mark to increase the accuracy of the production of a substrate mark, and decrease the difficulty in monitoring products and the production cost. An exemplary mask plate comprises: a display region mask part; at least one pair of test mark mask parts, a test mark mask part being located on either side of the display region mask part and their positions being opposite to each other; and a protection mark mask part correspondingly disposed on the outside of each test mark mask part relative to the display region mask part, wherein the pattern outline of the protection mark mask part is larger than that of the test mark mask part.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: February 9, 2016
    Assignees: Boe Technology Group Co., Ltd., Chengdu Boe Optoelectronics Technology Co., Ltd.
    Inventors: Xiaodan Wei, Xingqiang Zhang, Wei Zhao, Hongxu Yan
  • Patent number: 9244365
    Abstract: According to one embodiment, a method for measuring pattern misalignment, includes: a first step obtaining image data; a second step specifying a measurement region; a third step calculating a first shift amount (x1, y1); a fourth step determining, after calculating the first shift amount, a first distribution; a fifth step executing a plurality of times the second step, the third step, and the fourth step; a seventh step calculating a second shift amount (x2, y2); an eighth step determining, after calculating the second shift amount, a second distribution; a ninth step executing a plurality of times the sixth step, the seventh step, and the eighth step; and a tenth step calculating a difference (x2?x1, y2?y1) between the second pattern misalignment and the first pattern misalignment.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: January 26, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yosuke Okamoto, Yoshinori Hagio
  • Patent number: 9184136
    Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first surface and a second surface opposite the first surface, forming an alignment key and a connection contact that penetrate a portion of the semiconductor substrate and extend from the first surface toward the second surface, forming a first circuit on the first surface of the semiconductor substrate such that the first circuit is electrically connected to the connection contact, recessing the second surface of the semiconductor substrate to form a third surface exposing the alignment key and the connection contact, and forming a second circuit on the third surface of the semiconductor substrate such that the second circuit is electrically connected to the connection contact.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: November 10, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jiyoung Kim, Daeik Kim, Kang-Uk Kim, Nara Kim, Jemin Park, Kyuhyun Lee, Hyun-Woo Chung, Gyoyoung Jin, HyeongSun Hong, Yoosang Hwang
  • Patent number: 9158210
    Abstract: At a time of aligning a thin plate-shaped work of which both front and rear surfaces are subjected to work, a deflection caused at a central portion of the thin plate-shaped work is corrected and the thin plate-shaped work is controlled to be parallel state with respect to a photomask.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: October 13, 2015
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventor: Eriko Inoue
  • Patent number: 9152118
    Abstract: A sheet conveying apparatus includes a sheet conveying unit that conveys a sheet including a drive roller, a driven roller, and a rotary encoder provided on a rotational axle of one of the drive roller and the driven roller; a conveying amount measuring unit that measures a conveying amount of the sheet; a first detection unit positioned downstream of the sheet conveying unit, the first detection unit being positioned apart from the drive roller and the driven roller not to overlap with the drive roller and the driven roller in the conveying direction; a second detection unit positioned upstream of the sheet conveying unit; and a conveying distance calculation unit that calculates a conveying distance of the sheet based on the measured result by the conveying amount measuring unit and the detected results detected by the first detection unit and the second detection unit.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: October 6, 2015
    Assignee: RICOH COMPANY, LTD.
    Inventors: Makoto Nakura, Takuro Kamiya, Shingo Takai, Naoto Ueda, Satoshi Ueda, Akira Kobashi, Koichi Kudo
  • Patent number: 9136223
    Abstract: Methods for forming an alignment mark and the resulting mark are disclosed. Embodiments may include forming a first shape having rotational symmetry; forming a second shape; and forming an alignment mark by combining the first shape and one or more of the second shape, wherein the alignment mark has rotational symmetry.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: September 15, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guoxiang Ning, Soon Yoeng Tan, Seok Yan Poh, Paul Ackmann
  • Patent number: 9128388
    Abstract: A method of focus measurement of the embodiment irradiates exposure light from a first direction and projects first and second line-and-space patterns on a substrate. Further, exposure light is irradiated from a second direction and third and fourth line-and-space patterns are projected on the substrate. By measuring a distance between the first and third line-and-space patterns on the substrate, a sum of a dislocated amount caused by dislocation of focus and an overlap dislocation amount between the first and third line-and-space patterns is calculated as a first dislocated amount. Further, by measuring a distance between the second and fourth line-and-space patterns on the substrate, an overlap dislocation amount between the second and fourth line-and-space patterns is calculated as a second dislocation amount. Further, based on the first and second dislocation amounts, the focus dislocation amount is calculated.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: September 8, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobuhiro Komine
  • Patent number: 9128385
    Abstract: The embodiments described herein relate to methods, devices, and systems for masking a substrate using a photomasking process. An adaptive photomask configured to generate a photomasking pattern in accordance with dimensions of a surface feature on substrate is described. The adaptive photomask can be used to create customized photomask patterns for individual substrates. Methods and devices described herein can be used in manufacturing processes where similar parts having slight differences due to built-in tolerances are manufactured. Methods and a devices described herein can also be used in manufacture processes involving masking of three-dimensional portions of a part. A photomasking system that includes a translational mechanism for scanning a substrate surface is described.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: September 8, 2015
    Assignee: Apple Inc.
    Inventor: Napthaneal Yuen Tan
  • Patent number: 9127934
    Abstract: Embodiments of the invention discloses a space imaging overlay inspection method and an array substrate; the method comprises: forming a thin film having a space imaging overlay mark by photolithography; when the thin film is a transparent thin film, performing a color developing treatment on the space imaging overlay mark on the transparent thin film, so as to make the space imaging overlay mark appear in a non-transparent color; and conducting a space imaging overlay inspection between the transparent thin film and an adjacent thin film by using the space imaging overlay mark appear appearing in the non-transparent color. In the method, by conducting the color developing treatment to the space imaging overlay mark on the transparent thin film and then conducting positioning, the space imaging overlay mark can be positioned quickly and accurately, thus alignment condition between two photolithography procedures can be detected swiftly and effectively.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: September 8, 2015
    Assignee: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiaohui Jiang, Jian Guo
  • Patent number: 9086574
    Abstract: A compressed print having one or more compressed images of a symbol is disclosed. The compressed images are formed on an image forming surface under a lenticular sheet. The lenticular sheet has a plurality of lenticules and each of the compressed images has a plurality of image elements formed under a lenticule. Each of the image elements is corresponding to a different portion of the symbol. The lenticules are designed to be so small that the compressed image formed under each of the lenticules is not discernible when a viewer looks at the compressed print at a normal viewing distance. As such, the miniaturized compressed images of the symbol can be used as an identification tag, hidden in the compressed print.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: July 21, 2015
    Assignee: 3DV Co., Ltd.
    Inventor: Kwok Wah Allen Lo
  • Patent number: 9082798
    Abstract: Even in case that a wafer is so greatly deviated that a peripheral portion of the wafer cannot be detected, position determination of the wafer can be performed without inflicting a damage on the wafer. The wafer peripheral portion, which is a target, is detected based on output images from a plurality of imaging units disposed along a peripheral portion shape of the wafer (step S210), and a wafer position deviation correcting step (step S220) or a rough correcting step (step 230) is performed according to the number of the imaging units capable of detecting the wafer peripheral portion. In case that the wafer peripheral portion cannot be detected by all the imaging units, a wafer position adjusting step (step 240) for moving the wafer is performed in a position adjusting direction acquired by a combination of the output images by each imaging unit.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: July 14, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Takehiro Shindo
  • Patent number: 9081287
    Abstract: One embodiment relates to a method of measuring overlay errors for a programmable pattern, area-imaging electron beam lithography apparatus. Patterned cells of an overlay measurement target array may be printed in swaths such that they are superposed on patterned cells of a first (base) array. In addition, the overlay array may have controlled-exposure areas distributed within the swaths. The superposed cells of the overlay and base arrays are imaged. The overlay errors are then measured based on distortions between the two arrays in the image data. Alternatively, non-imaging methods, such as using scatterometry, may be used. Another embodiment relates to a method for correcting overlay errors for an electron beam lithography apparatus. Overlay errors for a pattern to be printed are determined based on within-swath exposure conditions. The pattern is then pre-distorted to compensate for the overlay errors. Other embodiments, aspects and features are also disclosed.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: July 14, 2015
    Assignee: KLA-Tencor Corporation
    Inventors: Walter D. Mieher, Allen Carroll
  • Patent number: 9057947
    Abstract: The invention relates to the technical field of an alignment method, and discloses a method for aligning substrate and mask, including: firstly forming at least one set of alignment marks on a mask plate; selecting a certain number of large-size substrates as sample substrates; forming a plurality of sets of alignment marks on each sample substrate using the mask plate and the at least one set of alignment marks formed thereon to divide the sample substrate into a plurality of sub-substrate areas; and then performing mask process on the respective sample substrates, accurate alignment for each sub-substrate area can be realized by means of the plurality of sets of alignment marks on the sample substrate, and one sub-substrate area can be accurately aligned by means of at least two sets of alignment marks formed on the sample substrate.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: June 16, 2015
    Assignees: BOE Technology Group Co., Ltd., Beijing BOE Display Technology Co., Ltd.
    Inventors: Guangming Lu, Chaoqin Xu, Kiyong Kim, Ziqing Zhou, Xiangnan Yun, Liping Luo