Including Control Feature Responsive To A Test Or Measurement Patents (Class 430/30)
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Patent number: 11940737Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.Type: GrantFiled: May 7, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu, Wei-Ti Hsu, Jui-Ping Chuang, Tzong-Sheng Chang, Kuei-Shun Chen, Meng-Wei Chen
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Patent number: 11921436Abstract: A lithography system is provided with: a measurement device measuring position information of marks on a substrate held in a first stage; and an exposure apparatus on a second stage, the substrate for which the position information measurement for the marks has been completed, performs alignment measurement to measure position information for part of marks selected from among the marks on the substrate, and performs exposure. The measurement device measures position information of marks on the substrate to obtain higher-degree components of correction amounts of an arrangement of divided areas, and the exposure apparatus measures position information of a small number of marks on the substrate to obtain lower-degree components of the correction amounts of the arrangement of the divided areas and exposes the plurality of divided areas while controlling the position of the substrate by using the obtained lower-degree components and the higher-degree components obtained by the measurement device.Type: GrantFiled: June 29, 2022Date of Patent: March 5, 2024Assignee: NIKON CORPORATIONInventor: Yuichi Shibazaki
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Patent number: 11902813Abstract: A measurement result receiving apparatus receives measurement results transmitted from a plurality of measuring devices, the measurement results obtained by conducting a measurement at a predetermined sampling interval according to a reference clock of each measuring device. The measurement result receiving apparatus includes a receiving section that receives the measurement results from the plurality of measuring devices; and a sampling interval converting section that converts the measurement results into measurement values associated with a common sampling interval.Type: GrantFiled: August 7, 2019Date of Patent: February 13, 2024Assignee: ADVANTEST CORPORATIONInventors: Takashi Fujisaki, Kazuhiro Shibano, Kenji Nishikawa
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Patent number: 11899367Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.Type: GrantFiled: December 12, 2022Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Shih-Ming Chang, Wen Lo, Chun-Hung Liu, Chia-Hua Chang, Hsin-Wei Wu, Ta-Wei Ou, Chien-Chih Chen, Chien-Cheng Chen
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Patent number: 11887898Abstract: A method of monitoring a semiconductor process includes the following steps. A process parameter is set to a first condition. A first process is performed to form a first film layer on a first wafer. The first film layer does not cover a wafer edge region of the first wafer. The first wafer having the first film layer is photographed by an image capturing device to obtain a first wafer image. Image recognition is performed to the first wafer image to obtain first data. Whether a position of the first film layer is offset is determined according to the first data.Type: GrantFiled: March 24, 2020Date of Patent: January 30, 2024Assignee: Winbond Electronics Corp.Inventors: Chien-Yen Liu, Cheng-Chieh Shen, Chung-Hsin Lai, Chen-Wei Liao
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Patent number: 11881357Abstract: A multilayer capacitor includes: a body including a stack structure in which a first internal electrode and a second internal electrode are stacked on each other interposing a dielectric layer therebetween; and first and second external electrodes disposed on the body to be respectively connected to the first internal electrode and the second internal electrode. One of the first internal electrode and the second internal electrode includes a recess portion disposed in one surface thereof, and providing a deviation in a distance between the first and second internal electrodes, TD indicates a thickness of a portion of the dielectric layer, based on a portion positioned on the one surface and not in the recess portion, TR indicates a recession depth of a portion positioned on the one surface and recessed by the recess portion, and (TR/TD) is greater than zero and less than (½).Type: GrantFiled: March 23, 2022Date of Patent: January 23, 2024Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Tae Ho Yun, Su Bong Jang, Sang Jong Lee
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Patent number: 11860551Abstract: A method for detecting a rare stochastic defect, the method may include searching for a rare stochastic defect in a dense pattern of a substrate, wherein the rare stochastic defect is (a) of nanometric scale, (b) appears in a functional pattern of the substrate with a defect density that is below 10?9, and (c) appears in the dense pattern with a defect density that is above 10?7; wherein the dense pattern is a dense representation of the functional pattern that differs from the functional pattern by at least one out of (a) a distance between features of the dense pattern, and (b) a width of the features of the dense pattern; and estimating the occurrence of the rare stochastic defect within the functional pattern based on an outcome of the searching.Type: GrantFiled: August 13, 2021Date of Patent: January 2, 2024Assignee: Applied Materials Israel Ltd.Inventor: Guy Cohen
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Patent number: 11862495Abstract: The present invention relates to a monitor wafer measuring method and measuring apparatus. The monitor wafer measuring method comprises the following steps: fixing a product wafer, the product wafer having several alignment marks and product measuring sites corresponding respectively to the alignment marks; determining the product measuring sites according to the alignment marks; and placing a monitor wafer, a projection of the monitor wafer in a vertical direction being aligned with and coinciding with the product wafer. The present application can reduce or even eliminate positional errors of the monitor wafer during a measurement process, such that product-level measuring position accuracy can be achieved for the monitor wafer and further, the measuring machine itself and process changes can be monitored in a better way.Type: GrantFiled: June 16, 2021Date of Patent: January 2, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: He Zhu
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Patent number: 11852967Abstract: A method for making a IC is provided, including: identifying, in a schematic, first and second edge elements, which edge elements including devices whose layout patterns are configured to conform to a first layout grid; identifying all the elements between the first and second edge elements, at least one of the identified elements including a device whose layout pattern is configured to conform to a second layout grid that is finer than the first layout grid; and calculating a spatial quantity of a combined layout pattern of the identified elements between the first and second edge elements to determine whether the combined layout pattern conforms to the first layout grid.Type: GrantFiled: March 23, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Hao Chen, Hui-Yu Lee, Jui-Feng Kuan, Chien-Te Wu
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Patent number: 11823922Abstract: A substrate inspection apparatus includes: a storage configured to store inspection image data obtained from a captured image of a periphery of a substrate on which a film is formed, and an inspection recipe; an edge detector configured to detect a target edge as an edge of an inspection target film on the basis of the inspection image data stored in the storage by using the inspection recipe stored in the storage; a periphery calculator configured to calculate a position of a theoretical periphery of the substrate; and a width calculator configured to calculate a width between the theoretical periphery of the substrate and the target edge on the basis of position data of the theoretical periphery of the substrate obtained by the periphery calculator and position data of the target edge obtained by the edge detector.Type: GrantFiled: February 16, 2023Date of Patent: November 21, 2023Assignee: TOKYO ELECTRON LIMITEDInventors: Akiko Kiyotomi, Masato Hosaka, Tadashi Nishiyama, Kazuya Hisano
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Patent number: 11825641Abstract: The invention discloses a pattern layout of an active region and a forming method thereof. The feature of the present invention is that in the sub-pattern unit, an appropriate active area pattern is designed according to the bit line pitch (BLP) and the word line pitch (WLP), the active area pattern is a stepped pattern formed by connecting a plurality of rectangular patterns in series, and the active area pattern is arranged along a first direction, the angle between the first direction and the horizontal direction is A. In addition, according to the angle A, the shortest distance (P) between adjacent stepped patterns, the length and width of sub-pattern units, etc., The positions of some stepped active area patterns are adjusted, so that the distance between multiple active area patterns can be consistent when being repeatedly arranged, thereby improving the uniformity of overall pattern distribution.Type: GrantFiled: May 4, 2021Date of Patent: November 21, 2023Inventor: Yifei Yan
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Patent number: 11809091Abstract: A substrate processing apparatus which processes includes a thermal processor that performs thermal processing on the substrate; an imager that images the substrate; and a controller that executes adjustment processing of adjusting conditions of processing on the substrate.Type: GrantFiled: July 10, 2020Date of Patent: November 7, 2023Assignee: Tokyo Electron LimitedInventors: Masahide Tadokoro, Masashi Enomoto, Kentaro Yamamura
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Patent number: 11796917Abstract: In a method of pattern formation information including a pattern size on a reticle is received. A width of an EUV radiation beam is adjusted in accordance with the information. The EUV radiation beam is scanned on the reticle. A photo resist layer is exposed with a reflected EUV radiation beam from the reticle. An increase of intensity per unit area of the EUV radiation beam on the reticle after the adjusting the width is greater when the width before adjustment is W1 compared to an increase of intensity per unit area of the EUV radiation beam on the reticle after the adjusting the width when the width before adjustment is W2 when W1>W2.Type: GrantFiled: December 13, 2021Date of Patent: October 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi Yang, Tsung-Hsun Lee, Jian-Yuan Su, Ching-Juinn Huang, Po-Chung Cheng
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Patent number: 11782352Abstract: A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.Type: GrantFiled: July 26, 2022Date of Patent: October 10, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Jie Lee, Shih-Chun Huang, Shih-Ming Chang, Ken-Hsien Hsieh, Yung-Sung Yen, Ru-Gun Liu
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Patent number: 11783110Abstract: Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include inputting a desired pattern to be formed on a substrate; determining an initial mask pattern from the desired pattern for the substrate; optimizing the initial mask pattern for wafer quality using a VSB exposure system; and outputting the optimized mask pattern. Methods for fracturing a pattern to be exposed on a surface using VSB lithography include inputting an initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by the union of the initial pattern with locations on the grid; merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots.Type: GrantFiled: July 30, 2021Date of Patent: October 10, 2023Assignee: D2S, Inc.Inventors: Akira Fujimura, P. Jeffrey Ungar, Nagesh Shirali
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Patent number: 11774850Abstract: A method of disposing a substrate on a holding unit using a pattern forming apparatus which forms a pattern on the substrate, the pattern forming apparatus comprising: a stage, the holding unit removably attached to the stage and configured to suck and hold the substrate, an optical system, and configured to detect an alignment mark of the substrate from a suction surface side of the substrate, the optical system having plural optical elements, and a detection unit configured to detect a reference mark for measuring a position of a detection field of the optical system, the method comprising: detecting a position of the reference mark, and disposing the substrate on the holding unit using the detected position of the reference mark so that the alignment mark of the substrate detected from the suction surface side of the substrate by the optical system is disposed in the detection field.Type: GrantFiled: October 2, 2020Date of Patent: October 3, 2023Assignee: Canon Kabushiki KaishaInventor: Naoki Funabashi
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Patent number: 11762297Abstract: Embodiments provide point-of-use blending of photoresist rinse solutions for patterned photoresists. Disclosed methods and systems form different mitigation solutions for multiple different photoresists through point-of-use variable blending of a mitigation solution with deionized water and/or other chemistries to adjust the formulation of the solution just prior to dispense within a process chamber. For one example embodiment, different surfactant rinse solutions are used for different photoresists, such as different extreme ultraviolet photoresists. In addition, the level of reactive components, the level of nonreactive components, or both within a mitigation solution can be adjusted using this point-of-use blending to provide an adjusted mitigation solution. The ability to make point-of-use adjustments to the solution chemistry just before dispense on a microelectronic workpiece, such as a semiconductor wafer, improves interactions between the adjusted mitigation solution and the patterned photoresist.Type: GrantFiled: November 5, 2019Date of Patent: September 19, 2023Assignee: Tokyo Electron LimitedInventors: Lior Huli, Naoki Shibata
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Patent number: 11763057Abstract: A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.Type: GrantFiled: June 25, 2021Date of Patent: September 19, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Ta Lu, Chi-Ming Tsai
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Patent number: 11756789Abstract: The present disclosure provides an apparatus for manufacturing a semiconductor structure. The apparatus includes a stage, an optical transceiver over the stage, configured to obtain a first profile of a first surface of a substrate, an acoustic transceiver over the stage, configured to obtain a second profile of a top surface of a photo-sensitive layer over the substrate, wherein the stage is adapted to be displaced based on the first profile and the second profile.Type: GrantFiled: December 23, 2021Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yung-Yao Lee, Wen-Chih Wang
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Patent number: 11733615Abstract: Disclosed is a method for selecting a structure for focus monitoring. The method comprises: simulating a Bossung response with focus of a focus dependent parameter, for one or more different structures; and selecting a structure for focus monitoring in a manufacturing process based on the results of said simulating step. The simulating step may be performed using a computational lithography simulation.Type: GrantFiled: December 5, 2019Date of Patent: August 22, 2023Assignee: ASML Netherlands B.V.Inventors: Frank Staals, Christoph Rene Konrad Cebulla Hennerkes
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Patent number: 11726398Abstract: A method for inspecting a reticle including a reflective layer on a reticle substrate is provided. The method may include loading the reticle on a stage, cooling the reticle substrate to a temperature lower than a room temperature, irradiating a laser beam to the reflective layer on the reticle substrate, receiving the laser beam using a photodetector to obtain an image of the reflective layer, and detect a particle defect on the reflective layer or a void defect in the reflective layer based on the image of the reflective layer.Type: GrantFiled: July 27, 2022Date of Patent: August 15, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Seulgi Kim, Hyonseok Song, Inyong Kang, Kangwon Lee, JuHyoung Lee, Eunsik Jang
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Patent number: 11720088Abstract: The subject matter herein provides for AI-based prediction of production defects in association with a production system, such as a semiconductor manufacturing machine. In one embodiment, a method begins by receiving production data from the production system. The production data typically comprises non-homogeneous machine parameters and maintenance data, quality test data, and product and process data. Using the production data, a neural network is trained to model an operation of a given machine in the production system. Preferably, the training involves multi-task learning, transfer learning (e.g., using knowledge obtained with respect to a machine of the same type as the given machine), and a combination of multi-task learning and transfer learning. Once the model is trained, it is associated with the given machine operating environment, wherein it is used to provide quality assurance predictions.Type: GrantFiled: March 25, 2022Date of Patent: August 8, 2023Assignee: LYNCEUS SASInventors: David Meyer, Guglielmo Montone
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Patent number: 11721637Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes bonding structure arranged directly between a first substrate and a second substrate. The first substrate includes a first transparent material and a first alignment mark. The first alignment mark is arranged on an outer region of the first substrate and also includes the first transparent material. The first alignment mark is defined by surfaces of the first substrate that are arranged between an uppermost surface of the first substrate and a lowermost surface of the first substrate. The second substrate includes a second alignment mark on an outer region of the second substrate. The second alignment mark directly underlies the first alignment mark, and the bonding structure is arranged directly between the first alignment mark and the second alignment mark.Type: GrantFiled: May 27, 2020Date of Patent: August 8, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Xin-Hua Huang, Ping-Yin Liu
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Patent number: 11704463Abstract: Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.Type: GrantFiled: March 31, 2021Date of Patent: July 18, 2023Assignee: Lam Research CorporationInventors: Ye Feng, Marcus Musselman, Andrew D. Bailey, III, Mehmet Derya Tetiker, Saravanapriyan Sriraman, Yan Zhang, Julien Mailfert
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Patent number: 11705304Abstract: A multi-beam apparatus for observing a sample with high resolution and high throughput and in flexibly varying observing conditions is proposed. The apparatus uses a movable collimating lens to flexibly vary the currents of the plural probe spots without influencing the intervals thereof, a new source-conversion unit to form the plural images of the single electron source and compensate off-axis aberrations of the plural probe spots with respect to observing conditions, and a pre-beamlet-forming means to reduce the strong Coulomb effect due to the primary-electron beam.Type: GrantFiled: July 12, 2021Date of Patent: July 18, 2023Assignee: ASML Netherlands B.V.Inventors: Shuai Li, Weiming Ren, Xuedong Liu, Juying Dou, Xuerang Hu, Zhongwei Chen
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Patent number: 11693542Abstract: The present invention comprises a novel user interface for a darkroom process timer and film processor. The user interface provides all necessary functionality for operating a programmable timer designed to time a sequence of multiple processing steps corresponding to a darkroom process. The necessary functionality includes: a means of specifying a time for a step, a means of specifying an agitation technique for a step, a means of specifying an operating temperature for a step, a means of starting the timer, a means of stopping the timer, a means of resetting the timer, a means of selecting a step, a means of signaling alarms, and a means of relaying instructions to the user.Type: GrantFiled: September 23, 2022Date of Patent: July 4, 2023Inventor: Derek Lluisma
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Patent number: 11692948Abstract: A method of inspection for defects on a substrate, such as a reflective reticle substrate, and associated apparatuses. The method includes performing the inspection using inspection radiation obtained from a high harmonic generation source and having one or more wavelengths within a wavelength range of between 20 nm and 150 nm. Also, a method including performing a coarse inspection using first inspection radiation having one or more first wavelengths within a first wavelength range; and performing a fine inspection using second inspection radiation having one or more second wavelengths within a second wavelength range, the second wavelength range comprising wavelengths shorter than the first wavelength range.Type: GrantFiled: January 8, 2019Date of Patent: July 4, 2023Assignee: ASML NETHERLANDS B.V.Inventors: Nitish Kumar, Richard Quintanilha, Markus Gerardus Martinus Maria Van Kraaij, Konstantin Tsigutkin, Willem Marie Julia Marcel Coene
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Patent number: 11686890Abstract: A transmissive optical element may include a substrate. The transmissive optical element may include a first anti-reflectance structure for a particular wavelength range formed on the substrate. The transmissive optical element may include a second anti-reflectance structure for the particular wavelength range formed on the first anti-reflectance structure. The transmissive optical element may include a third anti-reflectance structure for the particular wavelength range formed on the second anti-reflectance structure. The transmissive optical element may include at least one layer disposed between the first anti-reflectance structure and the second anti-reflectance structure or between the second anti-reflectance structure and the third anti-reflectance structure.Type: GrantFiled: September 30, 2020Date of Patent: June 27, 2023Assignee: Lumentum Operations LLCInventors: John Michael Miller, Gonzalo Wills
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Patent number: 11682114Abstract: A metrology system for obtaining a measurement representative of a thickness of a layer on a substrate includes a camera positioned to capture a color image of at least a portion of the substrate. A controller is configured to receive the color image from the camera, store a predetermined path in a coordinate space of at least two dimension including a first color channel and a second color channel, store a function that provides a value representative of a thickness as a function of a position on the predetermined path, determine a coordinate of a pixel in the coordinate space from color data in the color image for the pixel, determine a position of a point on the predetermined path that is closest to the coordinate of the pixel, and calculate a value representative of a thickness from the function and the position of the point on the predetermined path.Type: GrantFiled: April 27, 2021Date of Patent: June 20, 2023Assignee: Applied Materials, Inc.Inventor: Dominic J. Benvegnu
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Patent number: 11651936Abstract: A charged particle beam apparatus includes: a specimen chamber; a specimen holder that is disposed in the specimen chamber; a specimen exchange chamber that is connected to the specimen chamber; a transporting mechanism that transports a specimen between the specimen chamber and the specimen exchange chamber; a first temperature sensor that measures a temperature of the specimen holder; a second temperature sensor that measures a temperature of the transporting mechanism; and a control unit. The control unit: calculates a temperature difference between the specimen holder and the transporting mechanism based on the temperature of the specimen holder and the temperature of the transporting mechanism when the control unit has received an instruction to transport a specimen; determining whether the temperature difference is a threshold or more; and stopping transportation of a specimen when the control unit has determined that the temperature difference is the threshold or more.Type: GrantFiled: December 15, 2021Date of Patent: May 16, 2023Assignee: JEOL Ltd.Inventors: Naoki Fujimoto, Izuru Chiyo
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Patent number: 11639901Abstract: A test structure for use in metrology measurements of a sample pattern formed by periodicity of unit cells, each formed of pattern features arranged in a spaced-apart relationship along a pattern axis, the test structure having a test pattern, which is formed by a main pattern which includes main pattern features of one or more of the unit cells and has a symmetry plane, and a predetermined auxiliary pattern including at least two spaced apart auxiliary features located within at least some of those features of the main pattern, parameters of which are to be controlled during metrology measurements.Type: GrantFiled: October 11, 2021Date of Patent: May 2, 2023Assignee: NOVA LTDInventors: Gilad Barak, Oded Cohen, Igor Turovets
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Patent number: 11635699Abstract: Methods for training a process model and determining ranking of simulated patterns (e.g., corresponding to hot spots). A method involves obtaining a training data set including: (i) a simulated pattern associated with a mask pattern to be printed on a substrate, (ii) inspection data of a printed pattern imaged on the substrate using the mask pattern, and (iii) measured values of a parameter of the patterning process applied during imaging of the mask pattern on the substrate; and training a machine learning model for the patterning process based on the training data set to predict a difference in a characteristic of the simulated pattern and the printed pattern. The trained machine learning model can be used for determining a ranking of hot spots. In another method a model is trained based on measurement data to predict ranking of the hot spots.Type: GrantFiled: December 4, 2019Date of Patent: April 25, 2023Assignee: ASML NETHERLANDS B.V.Inventors: Youping Zhang, Maxime Philippe Frederic Genin, Cong Wu, Jing Su, Weixuan Hu, Yi Zou
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Patent number: 11630394Abstract: Disclosed is a method for lithographically producing a target structure on a non-planar initial structure by exposing a photoresist by means of a lithography beam. In the inventive method, the topography of a surface of the non-planar initial structure is detected. A test parameter for the lithography beam is used and an interaction of the lithography beam with the initial structure and the resultant change in the lithography beam and/or the target structure to be produced are determined. A correction parameter for the lithography beam is determined such that the change in the lithography beam and/or the target structure to be produced that is caused by the interaction of the lithography beam with the initial structure is reduced. The desired target structure on the initial structure is produced by exposing the photoresist by means of the lithography beam using the correction parameter.Type: GrantFiled: September 10, 2021Date of Patent: April 18, 2023Assignee: Karlsruhe Institute of TechnologyInventors: Christian Koos, Tobias Hoose, Philipp Dietrich, Matthias Blaicher, Maria Laura Gödecke, Nicole Lindenmann
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Patent number: 11626304Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.Type: GrantFiled: February 18, 2021Date of Patent: April 11, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzu-Cheng Lin, Y. Y. Peng, Jerry Wang, Kewei Zuo, Chien Rhone Wang
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Patent number: 11624981Abstract: Computer implemented methods and computer program products have instructions for generating transfer functions that relate segments on lithography photomasks to features produced by photolithography and etching using such segments. Such methods may be characterized by the following elements: (a) receiving after development inspection metrology results produced from one or more first test substrates on which resist was applied and patterned using a set of design layout segments; (b) receiving after etch inspection metrology results produced from one or more second test substrates which were etched after resist was applied and patterned using said set of design layout segments; and (c) generating the transfer function using the set of design layout segments together with corresponding after development inspection metrology results and corresponding after etch inspection metrology results.Type: GrantFiled: April 8, 2019Date of Patent: April 11, 2023Assignee: Lam Research CorporationInventors: Saravanapriyan Sriraman, David M. Fried
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Patent number: 11618183Abstract: A process for the production of a fibre-composite material, the process including the following steps: a) a fibre bundle is conducted over at least one deflection bar having radially circumferential rounded elevations, thus being expanded; b) the expanded fibre bundle is subsequently drawn into an impregnation chamber; c) a melt is applied to the expanded fibre bundle; and d) the fibre bundle impregnated with melt is drawn through a take-off die at the end of the apparatus, and a corresponding device, which achieves very good impregnation quality.Type: GrantFiled: April 19, 2016Date of Patent: April 4, 2023Assignee: Evonik Operations GmbHInventors: Mark Reinhard Berlin, Udo Sondermann
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Patent number: 11609506Abstract: A method for in-situ wave front detection within an inspection system is disclosed. The method includes generating light with a light source and directing the light to a stage-level reflective mask grating structure disposed on a mask stage. The method includes directing light reflected from the stage-level reflective structure to a detector-level mask structure disposed in a plane of a detector and then collecting, with an optical element, light reflected from the detector-level mask structure. The method includes forming a pupil image on the detector and laterally shifting the stage-level reflective mask, with the mask stage, across a grating period of the stage-level reflective mask grating structure to provide phase reconstruction for lateral shearing interferometry. The method includes selectively impinging light reflected from the optical element on the one or more sensors of the detector.Type: GrantFiled: April 18, 2022Date of Patent: March 21, 2023Assignee: KLA CorporationInventor: Markus Mengel
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Patent number: 11580289Abstract: A method for determining a patterning device pattern. The method includes obtaining (i) an initial patterning device pattern having at least one feature, and (ii) a desired feature size of the at least one feature, obtaining, based on a patterning process model, the initial patterning device pattern and a target pattern for a substrate, a difference value between a predicted pattern of the substrate image by the initial patterning device and the target pattern for the substrate, determining a penalty value related the manufacturability of the at least one feature, wherein the penalty value varies as a function of the size of the at least one feature, and determining the patterning device pattern based on the initial patterning device pattern and the desired feature size such that a sum of the difference value and the penalty value is reduced.Type: GrantFiled: October 29, 2019Date of Patent: February 14, 2023Assignee: ASML Netherlands B.V.Inventors: Roshni Biswas, Rafael C. Howell, Cuiping Zhang, Ningning Jia, Jingjing Liu, Quan Zhang
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Patent number: 11579537Abstract: According to one embodiment, a pattern inspection method includes detecting a region of a photomask having a pattern that differs from a corresponding design, acquiring an exposure focus shift information including an exposure focus shift amount of a portion of a substrate corresponding to the detected region of the photomask. The exposure focus shift amount for the detected region is acquired from the exposure focus shift information, and then a pass/fail determination for the detected region is performed based on an estimated pattern to be formed on the substrate.Type: GrantFiled: February 24, 2021Date of Patent: February 14, 2023Assignee: Kioxia CorporationInventors: Keiko Morishita, Kosuke Takai
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Patent number: 11561477Abstract: A method including: obtaining data based an optical proximity correction for a spatially shifted version of a training design pattern; and training a machine learning model configured to predict optical proximity corrections for design patterns using data regarding the training design pattern and the data based on the optical proximity correction for the spatially shifted version of the training design pattern.Type: GrantFiled: September 5, 2018Date of Patent: January 24, 2023Assignee: ASML Netherlands B.V.Inventors: Jing Su, Yen-Wen Lu, Ya Luo
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Patent number: 11561481Abstract: Techniques for using open frame (E0) exposures for lithographic tool track/cluster monitoring are provided. In one aspect, a method for monitoring a lithographic process includes: performing open frame exposures E0 of at least one wafer coated with a photoresist using a photolithography tool; baking and developing the at least one wafer; performing a defect inspection of the at least one wafer to generate a haze map; grouping haze data from the haze map; and analyzing the haze data to identify a maximum E0 response dose E?.Type: GrantFiled: July 20, 2020Date of Patent: January 24, 2023Assignee: International Business Machines CorporationInventors: Cody J. Murray, Ekmini Anuja De Silva, Christopher Frederick Robinson, Luciana Meli
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Patent number: 11550228Abstract: A lithography apparatus is provided. The lithography apparatus includes a wafer stage configured to secure a semiconductor wafer and having a plurality of electrodes. The lithography apparatus also includes an exposure tool configured to perform an exposure process by projecting an extreme ultraviolet (EUV) light on the semiconductor wafer. The lithography apparatus further includes a controller configured to control power supplied to the electrodes to have a first adjusted voltage during the exposure process for a first group of exposure fields on the semiconductor wafer so as to secure the semiconductor wafer to the wafer stage. The first adjusted voltage is in a range from about 1.6 kV to about 3.2 kV.Type: GrantFiled: March 26, 2021Date of Patent: January 10, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Kuan Wu, Po-Chung Cheng, Li-Jui Chen, Chih-Tsung Shih
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Patent number: 11531279Abstract: A method for correcting misalignments is provided. An alignment for each device of a group of devices mounted on a substrate is determined. An alignment error for the group of devices mounted on the substrate is determined based on the respective alignment for each device. One or more correction factors are calculated based on the alignment error. The alignment error is corrected based on the one or more correction factors.Type: GrantFiled: August 20, 2021Date of Patent: December 20, 2022Assignee: Onto Innovation Inc.Inventors: Elvino da Silveira, Keith F. Best, Wayne Fitzgerald, Jian Lu, Xin Song, J. Casey Donaher, Christopher J. McLaughlin
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Patent number: 11517941Abstract: The substrate processing method includes a hydrophilization step of hydrophilizing a surface of a substrate, a processing liquid supplying step of supplying a processing liquid to the hydrophilized surface of the substrate, a processing film forming step in which the processing liquid supplied to the surface of the substrate is solidified or cured to form a processing film on the surface of the substrate, and a peeling step in which a peeling liquid is supplied to the surface of the substrate to peel the processing film from the surface of the substrate. The peeling step includes a penetrating hole forming step in which the processing film is partially dissolved in the peeling liquid to form a penetrating hole in the processing film.Type: GrantFiled: March 23, 2021Date of Patent: December 6, 2022Inventors: Katsuya Akiyama, Yukifumi Yoshida
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Patent number: 11520237Abstract: The present disclosure, in some embodiments, relates to a photolithography tool. The photolithography tool includes a source configured to generate electromagnetic radiation. A dynamic focal system is configured to provide the electromagnetic radiation to a plurality of different vertical positions over a substrate stage. The plurality of different vertical positions include a first position having a first depth of focus and a second position having a second depth of focus that is below the first depth of focus and that vertically overlaps the first depth of focus.Type: GrantFiled: May 5, 2021Date of Patent: December 6, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jun-Yih Yu, De-Fang Huang, De-Chen Tseng, Jia-Feng Chang, Li-Fang Hsu
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Patent number: 11467484Abstract: A method for inspecting a reticle including a reflective layer on a reticle substrate is provided. The method may include loading the reticle on a stage, cooling the reticle substrate to a temperature lower than a room temperature, irradiating a laser beam to the reflective layer on the reticle substrate, receiving the laser beam using a photodetector to obtain an image of the reflective layer, and detect a particle defect on the reflective layer or a void defect in the reflective layer based on the image of the reflective layer.Type: GrantFiled: February 25, 2020Date of Patent: October 11, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Seulgi Kim, Hyonseok Song, Inyong Kang, Kangwon Lee, JuHyoung Lee, Eunsik Jang
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Patent number: 11467509Abstract: A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.Type: GrantFiled: March 29, 2021Date of Patent: October 11, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Jie Lee, Shih-Chun Huang, Shih-Ming Chang, Ken-Hsien Hsieh, Yung-Sung Yen, Ru-Gun Liu
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Patent number: 11468222Abstract: A method, includes, in part, defining a continuous signal, defining a threshold value, calibrating the continuous signal and the threshold value from measurements made on edges of one or more patterns on a mask and corresponding edges of the patterns on a wafer, convolving the continuous signal with a kernel to form a corrected signal, and establishing, by a processor, a probability of forming an edge at a point along the corrected signal in accordance with a difference between the value of the corrected signal at the point and the calibrated threshold value. The kernel is calibrated using the same measurements made on the patterns' edges.Type: GrantFiled: February 22, 2021Date of Patent: October 11, 2022Assignee: Synopsys, Inc.Inventors: Yudhishthir Prasad Kandel, Lawrence S. Melvin, III
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Patent number: 11454887Abstract: Disclosed is a method and associated inspection apparatus for measuring a characteristic of interest relating to a structure on a substrate. The inspection apparatus uses measurement radiation comprising a plurality of wavelengths. The method comprises performing a plurality of measurement acquisitions of said structure, each measurement acquisition being performed using measurement radiation comprising a different subset of the plurality of wavelengths, to obtain a plurality of multiplexed measurement signals. The plurality of multiplexed measurement signals are subsequently de-multiplexed into signal components according to each of said plurality of wavelengths, to obtain a plurality of de-multiplexed measurement signals which are separated according to wavelength.Type: GrantFiled: August 30, 2019Date of Patent: September 27, 2022Assignee: ASML Netherlands B.V.Inventor: Nitesh Pandey
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Patent number: 11442366Abstract: A device manufacturing method, the method including: obtaining a measurement data time series of a plurality of substrates on which an exposure step and a process step have been performed; obtaining a status data time series relating to conditions prevailing when the process step was performed on at least some of the plurality of substrates; applying a filter to the measurement data time series and the status data time series to obtain filtered data; and determining, using the filtered data, a correction to be applied in an exposure step performed on a subsequent substrate.Type: GrantFiled: May 7, 2018Date of Patent: September 13, 2022Assignee: ASML Netherlands B.V.Inventors: Rizvi Rahman, Hakki Ergün Cekli, Cëdric Dësirë Grouwstra