Abstract: A silicon wafer for an electronic component, having an epitaxially grown silicon layer on a carrier substrate and the silicon layer is removed as a silicon wafer from the carrier substrate, in which at least one p-dopant and at least one n-dopant are introduced into the silicon layer during the epitaxial growth. The dopants are introduced into the silicon layer such that the silicon layer is formed having an electrically active p-doping and an electrically active n-doping, each greater than 1×1014 cm?3.

Abstract: The disclosure provides improved processing of optical data by identifying anomalous signals in the electrical data representing the optical data. The improved processing can also include modifying the identified anomalous signal data to provide a truer representation of the optical data. The disclosed processing can be used by various systems and apparatuses for processing spectral data corresponding to the optical data. The improved processing can be used to improve the monitoring of semiconductor processes and, therefore, improve the overall semiconductor processes. In one example, a method of processing spectral data includes: (1) receiving temporally separated spectral data samples, and (2) identifying one or more anomalous signals in an intermediate one of the temporally separated spectral data samples based on at least one preceding and at least one subsequent ones of the spectral data samples.

Abstract: In some examples, a wafer bow measurement system comprises a measurement unit including: a wafer support assembly to impart rotational movement to a measured wafer supported in the measurement unit; an optical sensor; a calibration standard to calibrate the optical sensor; a linear stage actuator to impart linear direction of movement to the optical sensor; a wafer centering sensor to determine a centering of the measured wafer supported in the measurement unit; and a wafer alignment sensor to determine an alignment of the measured wafer supported in the measurement unit.

Abstract: An apparatus for manufacturing a display device and a method of manufacturing the display device are provided. The apparatus for manufacturing the display device includes: a mounting unit, on which a display substrate may be arranged; an inspection unit movably arranged on the mounting unit and configured to inspect whether or not an organic encapsulation layer of the display substrate is defective; and a repair unit movably arranged on the mounting unit and configured to supply an organic material to a defective portion of the organic encapsulation layer, or to remove at least a portion of the defective portion of the organic encapsulation layer.

Abstract: Apparatus and methods relating to DNA sequencing are provided. In one embodiment, a DNA sequencing device includes a nanochannel having a width that is approximately 0.3 nm to approximately 20 nm. A pair of electrodes having portions exposed to the nanochannel may form a tunneling current electrode (TCE) with an electrode gap of approximately 0.1 nm to approximately 2 nm, and more particularly about 0.3 nm to about 1 nm. In one embodiment, at least one of the pair of electrodes is formed as a suspended electrode. An actuator may be associated with the suspended electrode to displace it relative to the other electrode. In various embodiments, the nanochannel and/or the electrodes may be formed using thermal reflow processes to reduce the size of such features.

Abstract: A method of performing an ion implantation process using a beam-line ion implanter, including disposing a substrate on a platen, analyzing the substrate using metrology components, communicating data relating to the analysis of the substrate to a feedforward controller, processing the data using a predictive model executed by the feedforward controller to compensate for variations in the substrate and to compensate for variations in components of the beam-line ion implanter based on historical data collected from previous implantation operations, and using output from the predictive model to adjust operational parameters of the beam-line ion implanter.

Abstract: A method for analyzing a wafer map using a wafer map analyzer includes generating first wafer maps each displaying characteristics of a first wafer for a corresponding channel of a plurality of channels. The first wafer maps are auto-encoded together to extract a first feature. The method also includes determining whether the first feature is a valid pattern, classifying the type of the first feature based on unsupervised learning when the first feature is a valid pattern and extracting a representative image of features classified into the same type as the first feature.

Abstract: A distributed inductance integrated field effect transistor (FET) structure, comprising a plurality of FETs. Each FET comprises a plurality of source regions, a gate region having a plurality of gate fingers extending from a gate bus bar, a drain region having a plurality of drain finger extending from a drain bus bar between the plurality of gate fingers, wherein the gate region controls current flow in a conductive channel between the drain region and source region. A first distributed inductor connects the gate regions of adjacent ones of the plurality of FETs; and a second distributed inductor connects the drain regions of adjacent ones of the plurality of FETs.

Abstract: An impedance adjustment device includes a variable capacitor unit. A microcomputer changes the capacitance value of the variable capacitor unit by switching PIN diodes included in n capacitor circuits on or off separately. Thus, the impedance on the plasma generator side when viewed from a high frequency power supply is adjusted. When changing the capacitance value of the variable capacitor unit to a target capacitance value, the microcomputer changes the capacitance value. When a predetermined period passes after the change of the capacitance value, the microcomputer changes the capacitance value again.

Abstract: A strain gauge includes a flexible substrate; a functional layer formed of a metal, an alloy, or a metal compound, on one surface of the substrate; and a resistor formed of material including at least one from among chromium and nickel, on one surface of the functional layer.

Abstract: An example integrated circuit die includes: lower level conductor layers, lower level insulator layers between the lower level conductor layers, lower level vias extending vertically through the lower level insulator layers, upper level conductor layers overlying the lower level conductor layers, upper level insulator layers between and surrounding the upper level conductor layers, upper level vias; at least two scribe seals arranged to form a vertical barrier extending vertically from the semiconductor substrate to a passivation layer at an upper surface of the integrated circuit die; and at least one opening extending vertically through one of the at least two scribe seals and extending through: the upper level conductor layers, the upper level via layers, the lower level conductor layers, and the lower level via layers.

Abstract: In one embodiment, a method of forming a semiconductor device may include forming a sense resistor to receive a high voltage signal and form a sense signal that is representative of the high voltage signal. An embodiment of the sense resistor may optionally be formed overlying a polysilicon resistor. The method may also have an embodiment that may include forming a plurality of capacitors in parallel to portions of the sense resistor wherein the plurality of capacitors are connected together in series.

Abstract: An electronic device includes: a support member that has a metallic placement surface joined to the conductive bonding layer, and a metallic sealing surface provided on an outer side of the placement surface in an in-plane direction of the placement surface to adjoin the placement surface and to surround the placement surface; and a resin member, which is a synthetic resin molded article, joined to the sealing surface and covering the electronic component. The sealing surface includes a rough surface having a plurality of laser irradiation marks having a substantially circular shape. The rough surface includes a first region and a second region. The second region has a higher density of the laser irradiation marks in the in-plane direction than the first region.

Abstract: There is provided a substrate processing apparatus including a process chamber defined at least by a reaction tube and a furnace opening part provided at a lower portion of the reaction tube; a nozzle provided at the furnace opening part and extending from the furnace opening part to an inside of the reaction tube; a gas supply system provided at an upstream side of the nozzle; a blocking part provided at a boundary between the gas supply system and the nozzle; and a controller configured to control the gas supply system and the blocking part such that the blocking part co-operates with the gas supply system to supply gases into the process chamber through the nozzle.

Abstract: Embodiments disclosed herein generally relate to a method, system, and non-transitory computer readable medium for classifying an outlier in time series data collected by a sensor positioned in a substrate processing chamber. The client device receives time series data from the sensor positioned in the substrate processing chamber. The client device converts the time series data to a bounded uniform signal. The client device identifies signal sub-segments that do not match an expected behavior. The client device classifies the identified sub-segments that do not match the expected behavior.

Abstract: In one example, an apparatus comprises a backplane to attach an array of light emitting diodes (LED), the backplane comprising an array of display driver circuits, each display driver circuit of the array of display driver circuits corresponding to an LED of the array of LEDs and comprising: a current driver circuit configured to supply to a current to the corresponding LED; a control signal generator circuit configured to supply a driver control signal to the current driver circuit to control the current; and one or more monitor circuits controllable to provide access to at least one of: the current, or an internal voltage of at least one of the current driver circuit or the control signal generator circuit.

Abstract: In one embodiment, the present disclosure is directed to a method of impedance matching where an RF source is providing at least two non-zero pulse levels. For each of the at least two pulse levels, at a regular time interval, a control unit determines a parameter-related value that is based on a parameter related to the load, and repeatedly detects which of the at least two non-zero pulse levels is being provided by the RF source. Upon detecting one of the at least two non-zero pulse levels, for the detected pulse level, the control unit measures the parameter related to the load to determine a measured parameter value, determines the parameter-related value based on the measured parameter value, and alters the at least one EVC to provide the match configuration, the match configuration based on the parameter-related value.

Abstract: A method for controlling a processing apparatus used in a semiconductor manufacturing process to form a structure on a substrate, the method including: obtaining a relationship between a geometric parameter of the structure and a performance characteristic of a device including the structure; and determining a process setting for the processing apparatus associated with a location on the substrate, wherein the process setting is at least partially based on an expected value of the geometric parameter of the structure when using the processing setting, a desired performance characteristic of the device and an expected physical yield margin or defect yield margin associated with the location on the substrate.

Abstract: A first resistivity value and a correlation function relating thickness of a conductive layer having the first resistivity value to a signal from an in-situ monitoring system are stored. A second resistivity value for a conductive layer on a substrate is received. A sequence of signal values that depend on thickness of the conductive layer is received from an in-situ electromagnetic induction monitoring system that monitors the substrate during polishing. A sequence of thickness values is generated based on the sequence of signal values and the correlation function. For at least some thickness values of the sequence of thickness values adjusted thickness values are generated that compensate for variation between the first resistivity value and the second resistivity value to generate a sequence of adjusted thickness values. A polishing endpoint is detected or an adjustment for a polishing parameter is determined based on the sequence of adjusted thickness values.

Abstract: A method of polishing a layer on the substrate at a polishing station includes the actions of monitoring the layer during polishing at the polishing station with an in-situ monitoring system to generate a plurality of measured signals for a plurality of different locations on the layer; generating, for each location of the plurality of different locations, an estimated measure of thickness of the location, the generating including processing the plurality of measured signals through a neural network; and at least one of detecting a polishing endpoint or modifying a polishing parameter based on each estimated measure of thickness.

Abstract: An iterative etch process includes a plurality of cycles performed in a successive manner on a substrate. Each cycle of the plurality of cycles includes a deposition phase and an activation phase. The deposition phase is performed before the activation phase in each cycle. The deposition phase is defined as a plasma-based process to enable removal of a particular material from a surface of the substrate. The activation phase is defined as a plasma-based process to remove the particular material from the surface of the substrate. One or more feedback control signals are acquired during the iterative etch process, correlated to a condition of the substrate, and analyzed to determine the condition of the substrate. One or more process parameters of the iterative etch process is/are adjusted based on the condition of the substrate as determined by analyzing the one or more feedback control signals.

Abstract: A plasma processing apparatus with improved yield, adapted to include a vacuum container, a processing chamber disposed inside thereof, and in which a plasma is formed, a sample table disposed in the processing chamber and on which a sample is placed, two electrodes which have a film shape, disposed within the sample table, and to which power for attracting the sample is supplied so that different polarities are formed, a coiled portion in which two power supply lines are wound in parallel around the same axis, and a bypass line which connects the two power supply lines between the coiled portion and the two electrodes and has a capacitor.

Abstract: A method of detecting undesired surface effects while lasing a semiconductor during a laser marking, (dicing, fuse cutting or otherwise) process. A detection device is placed near the site of semiconductor lasing to detect erroneous laser markings resulting in the undesired surface effects. Upon identifying such a condition, lasing may be interrupted in-process.

Abstract: A digital circuit includes logic circuitry formed by logic gates. Each logic gate includes a p-channel MOSFET and an n-channel MOSFET. A body bias generator circuit applies an n-body bias voltage to the n-body bias nodes of the p-channel MOSFETs and applies a p-body bias voltage to the p-body bias nodes of the n-channel MOSFETs. The body bias generator circuit operates in: a first mode to apply a ground supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply a positive supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage; and a second mode to apply the positive supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply the ground supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage.

Abstract: Provided are process control methods and process control systems. The method includes performing a deposition process on a lot defined by a group of a plurality of wafers, performing a measurement process on the lot to obtain a measured value with respect to at least one wafer among the plurality of wafers, producing a target value of a factor of a process condition in the deposition process by using a difference between the measured value and a reference value, and providing an input value of the factor with respect to a subsequent lot based on the target value. The operation of providing the input value of the factor includes obtaining a previous target value of the factor previously produced with respect to at least one previous lot, and providing a weighted average of the previous target value and the target value as the input value.

Abstract: A method of manufacturing a silicon wafer is provided that includes extracting an n-type silicon ingot over an extraction time period from the a silicon melt comprising n-type dopants; adding p-type dopants to the silicon melt over at least part of the extraction time period, thereby compensating an n-type doping in the n-type silicon ingot by 10% to 80%; slicing the silicon ingot; forming hydrogen related donors in the silicon wafer by irradiating the silicon wafer with protons; and annealing the silicon wafer subsequent to the forming of the hydrogen related donors in the silicon wafer.

Abstract: An interlayer insulating film is disposed on a LOCOS oxide film covering an n-type drift region of a JFET. A polysilicon resistor having a spiral planar shape is disposed in the interlayer insulating film. A spiral wire in an outermost circumference of the polysilicon resistor is covered by a source electrode wire that extends on the interlayer insulating film. An end of the polysilicon resistor is electrically connected to a drain electrode wire. A ground terminal wire and a voltage division terminal wire are electrically connected to a spiral wire farther on an inner circumference side by one or more wires than the spiral wire. A portion farther on an inner circumference side than the spiral wire is used as a resistive element, and voltage for an input pad of the JFET is thereby divided to be taken out as a potential of the voltage division terminal wire.

Abstract: The present invention is directed to circuits, systems, and methods to quickly to quench an arc that may form between high voltage electrodes associated with an ion source to shorten the duration of the arc and mitigate non-uniform ion implantations. In one example, an arc detection circuit for detecting an arc in an ion implantation system includes an analog-to-digital converter (ADC) and an analysis circuit. The ADC is configured to convert a sensing current indicative of a current being supplied to an electrode in the ion implantation system to a digital current signal that quantifies the sensing current. The analysis circuit is configured to analyze the digital current signal to determine if the digital current signal meets threshold parameter value and in response to the digital current signal meeting the threshold parameter value, provide an arc detection signal to a trigger control circuit that activates an arc quenching mechanism.

Abstract: Methods and circuits for monitoring circuit degradation include measuring degradation in a set of on-chip test oscillators that vary according to a quantity that influences a first type of degradation. A second type of contribution to the measured degradation is determined by extrapolating from the measured degradation for the plurality of test oscillators. The second type of contribution is subtracted from the measured degradation at a predetermined value of the quantity to determine the first type of degradation for devices represented by the predetermined value.

Abstract: There is provided an MEMS device in which a first substrate provided with a driving element and a second substrate protecting the driving element are bonded to each other with an adhesive, in which the driving element is formed inside the space surrounded by the adhesive between the first substrate and the second substrate, an open hole which communicates with the space and the outside of the adhesive is formed on the adhesive, and an end of the outside of the open hole is provided to be with an end of the first substrate and an end of the second substrate.

Abstract: Methods for manufacturing a display device are provided. A representative method includes: providing a thin film transistor (TFT) substrate having a plurality of sub-pixel locations and a plurality of TFTs corresponding to the plurality of sub-pixel locations; providing a carrier substrate supporting a plurality of light emitting diodes (LEDs), wherein each of the plurality of LEDs has a first electrical contact and a second electrical contact; transferring the plurality of LEDs from the carrier substrate to the TFT substrate, with at least two of the plurality of LEDs being disposed at one of the plurality of sub-pixel locations; and fixing positions of the plurality of LEDs with respect to the TFT substrate. The method also may include: determining that a first LED of the plurality of LEDs is defective; and electrically isolating the first electrical contact of first LED from a first electrode of the display device.

Abstract: Systems and methods for controlling directionality of ion flux at an edge region within a plasma chamber are described. One of the systems includes a radio frequency (RF) generator that is configured to generate an RF signal, an impedance matching circuit coupled to the RF generator for receiving the RF signal to generate a modified RF signal, and a plasma chamber. The plasma chamber includes an edge ring and a coupling ring located below the edge ring and coupled to the first impedance matching circuit to receive the modified RF signal. The coupling ring includes an electrode that generates a capacitance between the electrode and the edge ring to control the directionality of the ion flux upon receiving the modified RF signal.

Abstract: A calibration device for a network analyzer with several ports provides a calibration circuit, which is connected in each case via a terminal port respectively to one of the several ports of the network analyzer. A first transistor and a second transistor are connected in series to each terminal port. In this context, both transistors are connected by their common connection to the terminal port. The first transistor and/or the second transistor is operated as an adjustable load.

Abstract: A method includes varying spacing between at least one of a source region or a drain region and a well contact region to create a group of configurations. The method further includes determining an effect of latchup on each configuration.

Abstract: In an approach to determining reliability test strategy, one or more computer processors receive a volume forecast for manufacturing one or more products. The one or more computer processors receive information describing the one or more products. The one or more computer processors retrieve reliability test requirements associated with the one or more products. The one or more computer processors retrieve reliability test capability of one or more reliability test vendors. The one or more computer processors determine, based, at least in part, on the volume forecast, the information describing the one or more products, the reliability test requirements, and the reliability test capability of the one or more reliability test vendors, a reliability test strategy.

Abstract: A mechanism is provided for forming a nanodevice. A reservoir is filled with a conductive fluid, and a membrane is formed to separate the reservoir in the nanodevice. The membrane includes an electrode layer having a tunneling junction formed therein. The membrane is formed to have a nanopore formed through one or more other layers of the membrane such that the nanopore is aligned with the tunneling junction of the electrode layer. The tunneling junction of the electrode layer is narrowed to a narrowed size by electroplating or electroless deposition. When a voltage is applied to the electrode layer, a tunneling current is generated by a base in the tunneling junction to be measured as a current signature for distinguishing the base. When an organic coating is formed on an inside surface of the tunneling junction, transient bonds are formed between the electrode layer and the base.

Abstract: A method for matching the impedance of the output impedance of a high-frequency power supply arrangement to the impedance of a plasma load includes, in a first impedance matching mode, matching the impedance of the output impedance of the high-frequency power supply arrangement by changing the frequency of the high-frequency signal produced. If the frequency is outside a specified frequency range, in a second impedance matching mode the impedance of the output impedance of the high-frequency power supply arrangement is matched by mechanically or electrically modifying a circuit which is arranged downstream of the high-frequency signal producer.

Abstract: A mechanism is provided for forming a nanodevice. A reservoir is filled with a conductive fluid, and a membrane is formed to separate the reservoir in the nanodevice. The membrane includes an electrode layer having a tunneling junction formed therein. The membrane is formed to have a nanopore formed through one or more other layers of the membrane such that the nanopore is aligned with the tunneling junction of the electrode layer. The tunneling junction of the electrode layer is narrowed to a narrowed size by electroplating or electroless deposition. When a voltage is applied to the electrode layer, a tunneling current is generated by a base in the tunneling junction to be measured as a current signature for distinguishing the base. When an organic coating is formed on an inside surface of the tunneling junction, transient bonds are formed between the electrode layer and the base.

Abstract: In a disclosed embodiment, a method for tiling selected vias in a semiconductor device having a plurality of vias comprises generating a layout database for the semiconductor device; creating zones around the plurality of vias; measuring density of covering metal in each zone; selecting a low density zone as being a zone that has a metal density less than a threshold metal density; and adding at least one tiling feature on a metal layer above the plurality of vias in the low density zone so that metal density of the low density zone increases to at least the same as the threshold metal density.

Abstract: A method of chemical mechanical polishing a substrate includes polishing a metal layer on the substrate at a polishing station, monitoring thickness of the metal layer during polishing at the polishing station with an eddy current monitoring system, and controlling pressures applied by a carrier head to the substrate during polishing of the metal layer at the polishing station based on thickness measurements of the metal layer from the eddy current monitoring system to reduce differences between an expected thickness profile of the metal layer and a target profile, wherein the metal layer has a resistivity greater than 700 ohm Angstroms.

Abstract: A method of controlling polishing includes polishing a substrate at a first polishing station, monitoring the substrate with a first eddy current monitoring system to generate a first signal, determining an ending value of the first signal for an end of polishing of the substrate at the first polishing station, determining a first temperature at the first polishing station, polishing the substrate at a second polishing station, monitoring the substrate with a second eddy current monitoring system to generate a second signal, determining a starting value of the second signal for a start of polishing of the substrate at the second polishing station, determining a gain for the second polishing station based on the ending value, the starting value and the first temperature, and calculating a third signal based on the second signal and the gain.

Abstract: In one aspect, a method of controlling polishing includes receiving a measurement of an initial thickness of a conductive film on a first substrate prior to polishing the first substrate from an in-line or stand-alone monitoring system, polishing one or more substrates in a polishing system, the one or more substrates including the first substrate, during polishing of the one or more substrates, monitoring the one or more substrates with an eddy current monitoring system to generate a first signal, determining a starting value of the first signal for a start of polishing of the first substrate, determining a gain based on the starting value and the measurement of the initial thickness, for at least a portion of the first signal collected during polishing of at least one substrate of the one or more substrates, and calculating a second signal based on the first signal and the gain.

Abstract: A semiconductor device, such as a semiconductor die, is disclosed including embedded temperature sensors for scanning the junction temperature, Tj, at one or more locations of the semiconductor die while the die is operating. Once a temperature of a hot spot is detected that is above a temperature specified for the die or package containing the die, the die/package may be discarded. Alternatively, the functionality of the die may be altered in a way that reduces the temperature of the hot spots.

Abstract: Methods and apparatus relating to FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.

Abstract: The use of ion sensitive field effect transistor (ISFET) to detect methylated nucleotides in a DNA sample is described. A method of detecting methylated nucleotides in a DNA sample may include the steps of treating a sample of DNA with a reagent which discriminates between methylated and non-methylated nucleotides to provide treated DNA, amplifying the treated DNA and optionally sequencing the amplified DNA. An ISFET is used to monitor the addition of one or more dNTPs in the strand extension reactions during the amplification and/or sequencing step. Suitable apparatus is also provided.

Abstract: A method for determining the structure of a transistor having at least one first layer including GaN, one second layer including AlxGa1-xN disposed on the first layer, and one fourth layer including a metal or an alloy disposed on the second layer. The method includes setting the layer thickness of the second layer, setting the aluminum content x of the second layer, producing at least the second layer and the first layer, determining the surface potential of formula (I) and/or the charge carrier density n, and/or the charge carrier motility ? after producing the second layer and the first layer, and selecting the material of the fourth layer as a function of the at least one measurement result.

Abstract: Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.

Abstract: The present invention is directed to methods for tailoring the work function of electrodes in organic electronics using interfacial modifiers comprising functionalized semiconducting polymers and/or small molecules.

Abstract: This solar cell module (10) is manufactured by connecting in series with a wiring material (15) multiple solar cells including at least two types of solar cells (11A, 11B) having different electrode structures, and covering the same with a first protective member (12) and a second protective member (13). This solar cell is manufactured by producing a photoelectric conversion unit, measuring characteristic values of the photoelectric conversion unit, selecting electrode structure on the basis of said characteristic values, and forming an electrode on the photoelectric conversion unit.

Abstract: A method of manufacturing a nitride semiconductor device, the nitride semiconductor device having an input terminal, a drain terminal, a gate terminal, and an output terminal, includes a burn-in step in which the nitride semiconductor device is heated while inputting an RF signal to the input terminal, applying a drain voltage to the drain terminal, and applying a gate voltage to the gate terminal. The burn-in step is continued until the nitride semiconductor device exhibits a decrease in gate current.