Abstract: A semiconductor device having a substrate, a dielectric layer, a polycrystalline silicon (“poly”) resistor, a drain, and a source is disclosed. After implantation, the poly resistor may have a lateral doping profile with two peaks, one near each edge of the poly resistor, and a trough near the middle of the poly resistor. Such a doping profile can allow the poly resistor to have a resistance that is insensitive to small variations in critical dimension of the poly resistor. The resistance of the poly resistor may be determined by the doping dose of the tilted implant used to form the poly resistor. The tilted implant may be used to form the drain and the source of a transistor substantially simultaneously as forming the poly resistor.

Abstract: A lift device and a lift system are provided, which comprises: a carrying mechanism including a guiding hole; a lift pin passing through inside the guiding hole; a carrying base, which is connected to the lift pin, wherein when the carrying base is moved upward, the lift pin is moved upward and inside the guiding hole; and a magnetic control device, which is used to send a magnetic control signal, so as to move the lift pin downward. By the lift pin being moved downward and magnetically sucked, a bad process problem and a break risk can be avoided.

Abstract: In an example, a single damascene structure is formed by, for example, providing a dielectric layer, forming a void in the dielectric layer, and forming a portion of a first two-terminal resistive memory cell and a portion of a second two-terminal resistive memory cell within the void. The portions of the two-terminal resistive memory cells may be vertically stacked within the void.

Abstract: According to the present invention, a metal nanoparticle dispersion suitable to multiple layered coating by jetting in the form of fine droplets is prepared by dispersing metal nanoparticles having an average particle size of 1 to 100 nm in a dispersion solvent having a boiling point of 80° C. or higher in such a manner that the volume percentage of the dispersion solvent is selected in the range of 55 to 80% by volume and the fluid viscosity (20° C.) of the dispersion is chosen in the range of 2 mPa·s to 30 mPa·s, and then when the dispersion is discharged in the form of fine droplets by inkjet method or the like, the dispersion is concentrated by evaporation of the dispersion solvent in the droplets in the course of flight, coming to be a viscous dispersion which can be applicable to multi-layered coating.

Abstract: An LED device is disclosed in which an LED chip is encapsulated in a encapsulant. The LED device includes an LED chip mounted on a support and electrically connected and an encapsulant encapsulating the LED chip, wherein the encapsulant is a transparent amorphous solid made of a metal oxide, and the solid contains as a major component at least one metal oxide selected from the group consisting of Al2O3, MgO, ZrO, La2O3, CeO, Y2O3, Eu2O3, and ScO.

Abstract: Disclosed herein is a semiconducting nanoparticle comprising a one-dimensional semiconducting nanoparticle having a first end and a second end; where the second end is opposed to the first end; and two first endcaps, one of which contacts the first end and the other of which contacts the second end respectively of the one-dimensional semiconducting nanoparticle; where the first endcap that contacts the first end comprises a first semiconductor and where the first endcap extends from the first end of the one-dimensional semiconducting nanoparticle to form a first nanocrystal heterojunction; where the first endcap that contacts the second end comprises a second semiconductor; where the first endcap extends from the second end of the one-dimensional semiconducting nanoparticle to form a second nanocrystal heterojunction; and where the first semiconductor and the second semiconductor are chemically different from each other.

Abstract: The present invention relates to an organic light emitting display device which can prevent a light compensation layer from cracking and a method for fabricating the same.

Abstract: Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.

Abstract: Memory cells of a memory device including a variable resistance material have a cavity between the memory cells. Electronic systems include such memory devices. Methods of forming a memory device include providing a cavity between memory cells of the memory device.

Abstract: An infrared energy oxidizing and/or curing process includes an infrared oxidation zone having an infrared energy source operable to emit infrared energy that oxidizes a conductive thin film deposited or established on a glass substrate to establish a light transmissive or transparent conductive thin film for manufacturing of a touch panel. Optionally, the infrared energy curing process provides an in-line infrared energy curing process that oxidizes the conductive thin film on the glass substrate as the glass substrate is moved past the infrared energy source. Optionally, the infrared energy curing process bonds a thick film silver frit electrode pattern to the conductively coated glass substrate. Optionally, the infrared energy curing process reduces the transparent conductive thin film.

Abstract: A method for the production of a contact structure of a semiconductor component comprises the masking of at least one side of a semiconductor substrate with a coating and the partial removal thereof in at least one pre-determined region.

Abstract: A semiconductor chip module having high degree of freedom in assignment of a circuit to each semiconductor chip and in position of a connection terminal of each semiconductor chip is provided. The present invention relates to a semiconductor chip module in which a plurality of semiconductor chips, each provided on the side face thereof with a part of a connection terminal coupled with a circuit pattern formed on the front face, have been stacked and bonded. Connection terminal portions on the side faces of the respective semiconductor chips are interconnected by a wiring pattern. The connection terminal on the semiconductor chip is led from the front face to the side face and formed by applying spraying of a conductive material in a mist state.

Abstract: A method for fabricating a touch sensor panel is disclosed. The method includes providing a substrate for the touch sensor panel, depositing a conductive material layer on a top surface of the substrate, depositing a metal layer on top of the conductive material layer, affixing a resist to a first area of the metal layer, the resist also adapted to serve as a passivation layer during passivation, removing metal from the metal layer outside of the first area; and performing passivation on the substrate while leaving the affixed resist intact.

Abstract: A method for producing an electronic component of a VQFN (very thin quad flat pack no-lead) design includes the following method steps: anchoring at least one integrated circuit element on a sacrificial substrate; contact-connecting the at least one integrated circuit element to the sacrificial substrate with formation of contact-connecting points on the sacrificial substrate; forming an encapsulation on a top side of the sacrificial substrate, the at least one anchored integrated circuit element being mounted on the top side of the sacrificial substrate; removing the sacrificial substrate, thereby uncovering a portion of the contact-connecting points on the underside of the encapsulation.

Abstract: In some aspects, a method of fabricating a memory cell is provided that includes fabricating a steering element above a substrate, and fabricating a reversible-resistance switching element coupled to the steering element by fabricating a carbon nano-tube (“CNT”) seeding layer by depositing a silicon-germanium layer above the substrate, patterning and etching the CNT seeding layer, and selectively fabricating CNT material on the CNT seeding layer. Numerous other aspects are provided.

Abstract: A method of fabricating a multi-chip package structure is provided. In the method, a number of cavities are formed on a predetermined cutting line of a first wafer by partly removing the first wafer and a first metal layer. Conductive walls of a first circuit layer are electrically connected to a cut cross-section of the first metal layer exposed by the cavities. In addition, conductive bumps of a second wafer or a chip are pressed into a cover layer and electrically connected to the first circuit layer. The first metal layer is then patterned to form a second circuit layer having a number of second pads. Next, the first wafer and the second wafer are cut along the predetermined cutting line to form a number of separated multi-chip package structures.

Abstract: A method for separating a semiconductor wafer into chips includes the steps of sandwiching a soluble spacer between a wafer and a substrate to form a laminate, etching the wafer into a plurality of chips attached on the spacer, positioning the laminate in a chamber of an apparatus in a way that the etched wafer faces a stage of the apparatus, and introducing a solvent into the chamber to dissolve the soluble spacer so as to facilitate the chips to be supported on the stage.

Abstract: A resistive memory device is provided. The resistive memory device includes a bottom electrode, a resistance-variable layer, and a top electrode. The resistance-variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance-variable layer. The resistance-variable layer includes a conductive polymer layer that reacts with the top electrode to form an oxide layer.

Abstract: A nonvolatile memory device includes a plurality of component memory layers stacked on one another. Each of the plurality of component memory layers includes a first wiring, a second wiring provided non-parallel to the first wiring, and a stacked structure unit provided between the first wiring and the second wiring. The stacked structure unit has a memory layer and a rectifying element. The rectifying element has a Schottky junction formed on an interface between an electrode and an oxide semiconductor. The electrode includes a metal and the oxide semiconductor includes a metal.

Abstract: A circuit board has a curved portion provided in at least one side of an external shape thereof. An external connecting terminal is provided on a first main surface of the circuit board. A semiconductor element is mounted on a second main surface of the circuit board. A first wiring network is provided in a region except the terminal region on the first main surface. A second wiring network is provided on the second main surface. Distance from the side including the curved portion to the first wiring network is larger than distance from at least one of the other sides to the first wiring networks, and distance from the side including the curved portion to the second wiring network is larger than distance from at least one of the other sides to the second wiring networks.

Abstract: The present invention provides a method of manufacturing a nano-array electrode with a controlled nano-structure by filling a compound having an electron-accepting structure or an electron donating structure into the fine pores of an anodic-oxide porous alumina film obtained by anodically oxidizing aluminum in electrolyte. The spaces defined between the nano-arrays formed of the compound by removing the alumina film are filled with a compound having an electron-donating structure if the nano-arrays have an electron-accepting structure and a compound having an electron-accepting structure if the nano-arrays have an electron-donating structure. A high-performance, high-efficiency photoelectric converting device comprising a nano-array electrode manufactured by the method is also disclosed.

Abstract: A first passive ferroelectric memory element comprising a first electrode system and a second electrode system, wherein said first electrode system is at least partly insulated from said second electrode system by an element system comprising at least one ferroelectric element, wherein said first electrode system is a conductive surface, or a conductive layer; wherein said second electrode system is an electrode pattern or a plurality of isolated conductive areas in contact with, for read-out or data-input purposes only, a plurality of conducting pins isolated from one another.

Abstract: A semiconductor device includes an insulating layer on a substrate, a first electrode in the insulating layer having a first upper surface and a second upper surface, a second electrode in the insulating layer spaced apart from the first electrode by a first distance and having a third upper surface and a fourth upper surface, the third upper surface being disposed at a substantially same level as the first upper surface, and the fourth upper surface being disposed at a substantially same level as the second upper surface, a first phase change material pattern covering a part of the first upper surface of the first electrode, and a second phase change material pattern covering a part of the third upper surface of the second electrode, wherein an interface region between the second phase change pattern and the second electrode is spaced apart from an interface region between the first phase change pattern and the first electrode by a second distance greater than the first distance.

Abstract: A device includes a first semiconductor chip and a second semiconductor chip which are connected to each other in an electrically conductive manner via a bonding wire, the bonding wire having a contact to the first semiconductor chip at a first contact point and having a contact to the second semiconductor chip at a second contact point, and the device including a further bonding wire which has a further first contact point and a further second contact point, a maximum distance between the bonding wire and a direct connecting line between the first and second contact points perpendicular to the connecting line being greater than a further maximum distance between the further bonding wire and a further connecting line between the further first contact point and the further second contact point perpendicular to the further connecting line.

Abstract: A nano-elastic memory device and a method of manufacturing the same. The nano-elastic memory device may include a substrate, a plurality of lower electrodes arranged in parallel on the substrate, a support unit formed of an insulating material to a desired or predetermined thickness on the substrate having cavities that expose the lower electrodes, a nano-elastic body extending perpendicular from a surface of the lower electrodes in the cavities, and a plurality of upper electrodes formed on the support unit and perpendicularly crossing the lower electrodes over the nano-elastic bodies.

Abstract: This publication discloses a method for forming electrically conducting structures on a substrate. According to the method nanoparticles containing conducting or semiconducting material are applied on the substrate in a dense formation and a voltage is applied over the nanoparticles so as to at least locally increase the conductivity of the formation. According to the invention, the voltage is high enough to cause melting of the nanoparticles in a breakthrough-like manner. With the aid of the invention, small-linewidth structures can be created without high-precision lithography.

Abstract: During fabrication of single-walled carbon nanotube transistor devices, a porous template with numerous parallel pores is used to hold the single-walled carbon nanotubes. The porous template or porous structure may be anodized aluminum oxide or another material. A gate region may be provided one end or both ends of the porous structure. The gate electrode may be formed and extend into the porous structure.

Abstract: An electrical generator includes a substrate, a semiconductor piezoelectric structure having a first end and an opposite second end disposed adjacent to the substrate, a first conductive contact and a second conductive contact. The structure bends when a force is applied adjacent to the first end, thereby causing an electrical potential difference to exist between a first side and a second side of the structure. The first conductive contact is in electrical communication with the first end and includes a material that creates a Schottky barrier between a portion of the first end of the structure and the first conductive contact. The first conductive contact is also disposed relative to the structure in a position so that the Schottky barrier is forward biased when the structure is deformed, thereby allowing current to flow from the first conductive contact into the first end.

Abstract: Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.

Abstract: Provided is an electronic device, a field effect transistor having the electronic device, and a method of manufacturing the electronic device and the field effect transistor. The electronic device includes: a substrate; a first electrode and a second electrode which are formed in parallel to each other on the substrate, each of the first electrode and the second electrode comprising two electrode pads separated from each other and a heating element that connect the two electrode pads; a catalyst metal layer formed on the heating element of the first electrode; and a carbon nanotube connected to the second electrode by horizontally growing from the catalyst metal layer; wherein the heating elements are separated from the substrate by etching the substrate under the heating elements of the first and the second electrodes.

Abstract: Disclosed is a method for annealing a silicon thin film in a substrate in which an insulation layer and the silicon thin film are subsequently formed. The method includes heating or preheating the silicon thin film within a temperature range at which the substrate is not transformed during the process so as to generate an intrinsic carrier therein, thereby lowering a resistance to a value at which Joule heating is possible; and applying an electric field to the preheated silicon thin film so as to induce Joule heating by means of movement of the carrier, thereby conducting crystallization, eliminating crystal defects, and ensuring crystal growth. When using the method, Joule heating is selectively induced to a-Si thin film, a-Si/Poly-Si thin film or a Poly-Si thin film according to the preheating condition, thereby making a Poly-Si thin film of good quality within a very short time without damaging the substrate.

Abstract: A method is provided for forming a Pr0.3Ca0.7MnO3 (PCMO) thin film with crystalline structure-related memory resistance properties. The method comprises: forming a PCMO thin film with a first crystalline structure; and, changing the resistance state of the PCMO film using pulse polarities responsive to the first crystalline structure. In one aspect the first crystalline structure is either amorphous or a weak-crystalline. Then, the resistance state of the PCMO film is changed in response to unipolar pulses. In another aspect, the PCMO thin film has either a polycrystalline structure. Then, the resistance state of the PCMO film changes in response to bipolar pulses.

Abstract: A probe of a scanning probe microscope having a sharp tip and an increased electric characteristic by fabricating a planar type of field effect transistor and manufacturing a conductive carbon nanotube on the planar type field effect transistor. To achieve this, the present invention provides a method for fabricating a probe having a field effect transistor channel structure including fabricating a field effect transistor, making preparations for growing a carbon nanotube at a top portion of a gate electrode of the field effect transistor, and generating the carbon nanotube at the top portion of the gate electrode of the field effect transistor.

Abstract: The invention provides for a nonvolatile memory cell comprising a heater layer in series with a phase change material, such as a chalcogenide. Phase change is achieved in chalcogenide memories by thermal means. Concentrating thermal energy in a relatively small volume assists this phase change. In the present invention, a layer in a pillar-shaped section of a memory cell is etched laterally, decreasing its cross-section. In this way the cross section of the contact area between the heater layer and the phase change material is reduced. In preferred embodiments, the laterally etched layer is the heater layer or a sacrificial layer. In a preferred embodiment, such a cell can be used in a monolithic three dimensional memory array.

Abstract: An aspect of the present invention is a method for forming a plurality of thin-film devices. The method includes coarsely patterning at least one thin-film material on a flexible substrate and forming a plurality of thin-film elements on the flexible substrate with a self-aligned imprint lithography (SAIL) process.

Abstract: An electrical connection terminal of an embedded chip and a method for fabricating the same are disclosed. An insulating layer is provided on a circuit board integrated with a chip and has a plurality of first openings for exposing a conductive pad of the chip. A first metal layer is formed on the conductive pad, and a conductive layer if formed on surfaces of the first metal layer, the insulating layer and the first openings. A patterned resist layer is formed on the conductive layer and has a plurality of second openings for exposing a part of the conductive layer corresponding to the condictive pad of the chip. A second metal layer is formed on the exposed part of the conductive layer by an electroplating process. Thus, the fabrication of conductive structure of the conductive pad of the ship and build-up of conductive circuits on the circuit board are integrated simultaneously.

Abstract: The invention relates to an FBGA arrangement, comprising a substrate on which at least one chip is chip-bonded face-down, which has a central row of bonding pads connected to contact islands (landing pads) on the substrate by a bonding channel in the substrate via wire bridges, which substrate, for its part, is provided with soldering balls—arranged in an array—for contact connection to a printed circuit board, and the contact islands and the soldering balls being connected to one another via a rewiring of the substrate. The preferred embodiment of the invention is intended to provide an FBGA arrangement which supports the center pad row technology and at the same time has low electrical parasitics.

Abstract: A method of detecting contamination on a backside of a semiconductor wafer includes the steps of positioning the backside of the wafer in contact with a detection surface of a contaminant sensor, and detecting deformation of the detection surface of the contaminant sensor. The contaminant sensor may be incorporated into a fabrication device such as a wafer handling device, or can be utilized in the construction of a stand-alone device. An apparatus for detecting contamination on the backside of a semiconductor wafer is also disclosed.

Abstract: A current-controlling device comprising a first conductor, a second conductor, and a tunneling barrier comprising a first insulating layer between the first conductor and the second conductor. The tunneling barrier electrically isolates the first conductor from the second conductor. At least one mobile charge is positionable within the tunneling barrier. The device also includes a gate, wherein a voltage applied to the gate with respect to the substrate (or with respect to a second gate formed on or in the substrate) modulates or moves the mobile charge to a position between the first conductor and the second conductor within the tunneling barrier, thus deforming the shape of the energy barrier between the first conductor and the second conductor. The deformation can cause a current to flow between the conductors when a voltage is present between them due to quantum mechanical tunneling.

Abstract: Methods and apparatus of forming a semiconductor device using pedestals and sidewalls. The pedestals and sidewalls may provide an etch stop and/or a diffusion barrier during manufacture of a semiconductor device. Processes of forming diode connected vertical cylindrical field effect devices are disclosed to exemplify the use of the pedestals and/or sidewalls. A system for forming the pedestals and sidewalls is described.

Abstract: A wall film monitoring system includes first and second microwave mirrors in a plasma processing chamber each having a concave surface. The concave surface of the second mirror is oriented opposite the concave surface of the first mirror. A power source is coupled to the first mirror and configured to produce a microwave signal. A detector is coupled to at least one of the first mirror and the second mirror and configured to measure a vacuum resonance voltage of the microwave signal. A control system is connected to the detector that compares a first measured voltage and a second measured voltage and determines whether the second voltage exceeds a threshold value. A method of monitoring wall film in a plasma chamber includes loading a wafer in the chamber, setting a frequency of a microwave signal output to a resonance frequency, and measuring a first vacuum resonance voltage of the microwave signal.

Abstract: An optoelectronic semiconductor package device includes a semiconductor chip, an insulative housing and a conductive trace, wherein the chip includes an upper surface and a lower surface, the upper surface includes a light sensitive cell and a conductive pad, the insulative housing includes a first single-piece non-transparent insulative housing portion that contacts the lower surface and is spaced from the light sensitive cell and a second transparent insulative housing portion that contacts the first housing portion and the light sensitive cell, and the conductive trace extends outside the insulative housing and is electrically connected to the pad inside the insulative housing.

Abstract: A method and apparatus for forming a micro tip for a micro probe utilized in testing semiconductor integrated circuit devices. A thick oxide layer is deposited upon a substrate initially to form the micro tip. The micro tip for the micro probe can be defined from the thick oxide layer upon the substrate through a plurality of subsequent semiconductor manufacturing operations performed upon the substrate and layers thereof. A plurality of micro tips can be mass produced and efficiently utilized in association with increasingly smaller sizes of semiconductor integrated circuit devices.

Abstract: A plurality of fixed contacts and signal lines are provided on a fixed substrate. A movable contact which is closed or opened with the fixed contacts is provided on a movable substrate opposed to the fixed substrate. A film thickness of the fixed contacts is made to be smaller than that of the signal lines so that the movable contact is set in a concave portion constituted by the fixed contacts when the fixed contacts, and the movable contact are closed and the signal lines are linearly connected.

Abstract: Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as “latent masking”, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as “simultaneous multi-level etching (SMILE)”, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as “delayed LOCOS”, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes.

Abstract: Method and apparatus for sensing the displacements of micromachined devices and sensors. The method is referred to as the enhanced modulated integrative differential optical sensing (EMIDOS). The target micromachined proof-mass, for which displacements are measured, includes a grid of slits. The émicromachined device is bonded to a CMOS chip containing a matching photodiodes array and their readout electronics. The grid is aligned with the photodiodes. An illumination source, such as an LED, is then mounted above the méicromachiend device.

Abstract: An interactive information device for use as a touch panel, touch screen, digitizer panel, or pen-input device, and a method for making such a device includes a first, transparent, electrically conductive layer supported by the rigid substrate, a flexible, transparent substrate at least partially aligned with the rigid substrate and having a second, transparent, electrically conductive layer on a surface thereof, the second conductive layer being spaced from the first conductive layer. A plurality of transparent insulating spacer members/dots are positioned on one or both of the conductive layers to allow the conductive layers to engage when the flexible substrate is pressed. The spacer members/dots comprise polymeric material including at least some inorganic material, and more preferably, comprise organic-inorganic nanocomposites having an index of refraction optically matched to the transparent, electrically conductive layer on which they are positioned.

Abstract: A method for making a build-up package of a semiconductor die and a structure formed from the same. A copper foil with conductive columns is bonded to an encapsulated die by thermal compression, between thereof there is a pre-curing dielectric film sandwiched. The dielectric film is cured to form a dielectric layer of a die build-up package and the copper foil on the dielectric layer is etched to form the conductive traces. At least one conductive column in one of the dielectric layers is vertically corresponding to one of conductive column in the adjacent dielectric layer.

Abstract: A controller module for a semiconductor manufacturing device wherein the controller module has a plurality of controllers comprises a control box disposed at an outside of the semiconductor manufacturing device wherein each of the plurality of controllers is separately installed into the control box, and a movable control box support wherein the control box is loaded on the control box support and slides on the control box support.

Abstract: The invention relates to a device and method for the deposition of in particular, crystalline layers on one or several, in particular, equally crystalline substrates in a process chamber, by means of reaction gases which are fed to the process chamber where they react pyrolytically. The process chamber has a first wall and a second wall, lying opposite the first. The first wall is provided with at least one heated substrate holder, to which at least one reaction gas is led by means of a gas inlet device. According to the invention, a premature decomposition of source gases and a local oversaturation of the gas flow with decomposition products may be avoided, whereby the gas inlet device is liquid cooled.