Including Adhesive Bonding Step Patents (Class 438/118)
  • Patent number: 11939494
    Abstract: A technical problem to be achieved by the present disclosure is to provide an adhesive resin composition for a conductor, which contains inorganic fillers having different average particle diameters and has enhanced thermal conductivity as a result of controlling the content of the inorganic fillers, and an adhesive film for a semiconductor produced using the same.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: March 26, 2024
    Assignee: LG CHEM, LTD.
    Inventors: Jong Min Jang, Byoung Ju Choi, Kwang Joo Lee, Yu Lin Sun
  • Patent number: 11942460
    Abstract: Semiconductor devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device is an assembly that includes a package substrate having a front side and a backside opposite the front side. A controller die with a first longitudinal footprint can be attached to the front side of the package substrate. A passive electrical component is also attached to the front side of the package substrate. A stack of semiconductor dies can be attached to the controller die and the passive electrical component. The stack of semiconductor dies has a second longitudinal footprint greater than the first longitudinal footprint in at least one dimension. The controller die and the passive electrical component are positioned at least partially within the second longitudinal footprint, thereby at least partially supporting the stack of semiconductor dies.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Hong Wan Ng, Kelvin Tan Aik Boo, Chin Hui Chong, Hem P. Takiar, Seng Kim Ye
  • Patent number: 11935805
    Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: April 12, 2023
    Date of Patent: March 19, 2024
    Assignee: Intel Corporation
    Inventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
  • Patent number: 11936164
    Abstract: A light emitting device includes a wiring substrate, a light emitting element array that includes a first side surface and a second side surface facing each other, and a third side surface and a fourth side surface connecting the first side surface and the second side surface to each other and facing each other, the light emitting element array being provided on the wiring substrate, a driving element that is provided on the wiring substrate on the first side surface side and drives the light emitting element array, a first circuit element and a second circuit element that are provided on the wiring substrate on the second side surface side to be arranged in a direction along the second side surface, and a wiring member that is provided on the third side surface side and the fourth side surface side and extends from a top electrode of the light emitting element array toward an outside of the light emitting element array.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: March 19, 2024
    Assignee: FUJIFILM Business Innovation Corp.
    Inventors: Kazuhiro Sakai, Daisuke Iguchi, Takeshi Minamiru, Yoshinori Shirakawa, Tomoaki Sakita, Tsutomu Otsuka
  • Patent number: 11932111
    Abstract: A rectifier and a vehicle AC generator that can suppress the cost, the rectification loss, and the leakage current from increasing are provided. A rectifier is configured in such a way that in each of n sets, one of a positive electrode side semiconductor device and a negative electrode side semiconductor device is a MOSFET, in such a way that in at least one of the n sets, the other one of the positive electrode side semiconductor device and the negative electrode side semiconductor device is a specific diode, and in such a way that the specific diode is a Schottky barrier diode or a MOS diode, which is a MOSFET whose drain terminal and gate terminal are short-circuited.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: March 19, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinichiro Minami, Katsuya Tsujimoto, Keiichi Komurasaki, Shingo Inoue
  • Patent number: 11894282
    Abstract: Disclosed herein are vented lids for integrated circuit (IC) packages, as well as related methods and devices. For example, in some embodiments, an IC package may include a package substrate, a lid, and a die between the package substrate and the lid. A vent may extend between the interior surface and the exterior surface of the lid, and the vent may at least partially overlap the die.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: February 6, 2024
    Assignee: Intel Corporation
    Inventors: Zhimin Wan, Sergio Antonio Chan Arguedas, Peng Li, Chandra Mohan Jha, Aravindha R. Antoniswamy, Cheng Xu, Junnan Zhao, Ying Wang
  • Patent number: 11894317
    Abstract: A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device, a second electronic device, a first underfill, a second underfill and a stiff bonding material. The first electronic device and the second electronic device are disposed on the wiring structure, and are electrically connected to each other through the wiring structure. The first underfill is disposed in a first space between the first electronic device and the wiring structure. The second underfill is disposed in a second space between the second electronic device and the wiring structure. The stiff bonding material is disposed in a central gap between the first electronic device and the second electronic device. The stiff bonding material is different from the first underfill and the second underfill.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: February 6, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Po-Hsien Ke, Teck-Chong Lee, Chih-Pin Hung
  • Patent number: 11869823
    Abstract: Methods and structures for manufacturing one or more System in a Package (SiP) devices, where the functionality of a packaged SiP device may be modified by additional components.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: January 9, 2024
    Assignee: OCTAVO SYSTEMS LLC
    Inventors: Michael Kenneth Conti, Christopher Lloyd Reinert, Masood Murtuza
  • Patent number: 11854888
    Abstract: An embodiment disclosed herein includes a method of dicing a wafer comprising a plurality of integrated circuits. In an embodiment, the method comprises forming a mask above the semiconductor wafer, and patterning the mask and the semiconductor wafer with a first laser process. The method may further comprise patterning the mask and the semiconductor wafer with a second laser process, where the second laser process is different than the first laser process. In an embodiment, the method may further comprise etching the semiconductor wafer with a plasma etching process to singulate the integrated circuits.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: December 26, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Jungrae Park, Zavier Zai Yeong Tan, Karthik Balakrishnan, James S. Papanu, Wei-Sheng Lei
  • Patent number: 11840648
    Abstract: Disclosed is a semiconductor device manufacturing method, including a preparation step of preparing a laminated body in which a supporting member, a temporary fixation material layer that generates heat upon absorbing light, and a semiconductor member are laminated in this order, and a separation step of irradiating the temporary fixation material layer in the laminated body with incoherent light and thereby separating the semiconductor member from the supporting member.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: December 12, 2023
    Assignee: RESONAC CORPORATION
    Inventors: Emi Miyazawa, Tsuyoshi Hayasaka, Takashi Kawamori, Shinichiro Sukata, Yoshihito Inaba, Keisuke Nishido
  • Patent number: 11830854
    Abstract: Methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. In an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Yi Chuang, Hou-Yu Chen, Kuan-Lun Cheng
  • Patent number: 11784172
    Abstract: A method includes bonding a capacitor die to a device die. The device die includes a first semiconductor substrate, active devices at a surface of the first semiconductor substrate, a plurality of low-k dielectric layers, a first dielectric layer over and contacting a top low-k dielectric layer in the plurality of low-k dielectric layers, and a first plurality of bond pads in the first dielectric layer. The capacitor die includes a second dielectric layer bonding to the first dielectric layer, a second plurality of bond pads in the second dielectric layer and bonding to the first plurality of bond pads, and a capacitor electrically coupled to the second plurality of bond pads. After the capacitor die is bonded to the device die, an aluminum-containing pad is formed over the capacitor die and electrically coupled to the device die. A polymer layer is formed over the aluminum-containing pad.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING HSINCHU, CO., LTD.
    Inventors: Chen-Hua Yu, Chung-Hao Tsai, Chuei-Tang Wang, Chieh-Yen Chen
  • Patent number: 11784105
    Abstract: A semiconductor device includes: a circuit member including a planar portion; a terminal portion formed above the front surface of the planar portion of the circuit member and parallel to the planar portion; a semiconductor element which has an upper surface located below an upper surface of the terminal portion and is formed on the front surface of the planar portion of the circuit member; a resin layer arranged on the semiconductor element and having first openings through which the semiconductor element is exposed; a conductive layer arranged on the resin layer, including an upper surface located above the upper surface of the terminal portion, and joined to the semiconductor element through the first openings; and a sealing member including an upper surface parallel to the planar portion and integrally sealing the circuit member, the semiconductor element, the resin layer, the conductive layer, and part of the terminal portion.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: October 10, 2023
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hodaka Rokubuichi, Seiki Hiramatsu, Shota Morisaki, Shinya Yano
  • Patent number: 11769758
    Abstract: A light emitting device includes a backplane, an array of light emitting diodes attached to a front side of the backplane, a transparent conductive layer contacting front side surfaces of the light emitting diodes, an optical bonding layer located over a front side surface of the transparent conductive layer, a transparent cover plate located over a front side surface of the optical bonding layer, and a black matrix layer including an array of openings therethrough, and located between the optical bonding layer and the transparent cover plate.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: September 26, 2023
    Assignee: NANOSYS, INC.
    Inventor: Brian Kim
  • Patent number: 11764066
    Abstract: A peeling method for peeling off a substrate provided over a front surface of a support plate through a peel layer from the support plate after dividing the substrate into a plurality of small pieces, the peeling method comprising: a first holding step of holding the support plate by a first holding unit; a dividing step of causing a cutting blade to cut into the substrate, or applying a laser beam of such a wavelength as to be absorbed in the substrate to the substrate, along division lines set on the substrate, to divide the substrate into the plurality of small pieces; a start point region forming step of blowing a fluid to the peel layer exposed at an end portion of a small piece among the plurality of small pieces, to form a start point region which will serve as a start point when peeling off the small piece from the support plate; a second holding step of holding the small piece by a second holding unit; and a peeling step of relatively moving the first holding unit and the second holding unit in direc
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: September 19, 2023
    Assignee: DISCO CORPORATION
    Inventor: Katsuhiko Suzuki
  • Patent number: 11742291
    Abstract: Some embodiments relate to a semiconductor structure including a method for forming a semiconductor structure. The method includes forming a lower conductive structure within a first dielectric layer over a substrate. An upper dielectric structure is formed over the lower conductive structure. The upper dielectric structure comprises sidewalls defining an opening over the lower conductive structure. A first liner layer is selectively deposited along the sidewalls of the upper dielectric structure. A conductive body is formed within the opening and over the lower conductive structure. The conductive body has a bottom surface directly overlying a middle region of the lower conductive structure. The first layer is laterally offset from the middle region of the lower conductive structure by a non-zero distance.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: August 29, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiu-Wen Hsueh, Chii-Ping Chen, Neng-Jye Yang, Ya-Lien Lee, An-Jiao Fu, Ya-Ching Tseng
  • Patent number: 11710682
    Abstract: A semiconductor device includes: a first electrode terminal; a second electrode terminal; a semiconductor element having an electrode on one surface connected to one surface of the first electrode terminal; a wire that connects an electrode on the other surface of the semiconductor element and the second electrode terminal; and a resin portion formed of an insulator covering the semiconductor element, a part of the second electrode terminal, and the one surface of the first electrode terminal, wherein a chamfered portion is formed on at least one of end portions where the first electrode terminal and the second electrode terminal face each other.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: July 25, 2023
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Hisato Michikoshi
  • Patent number: 11705695
    Abstract: A light emitting device includes a wiring substrate, a light emitting element array that includes a first side surface and a second side surface facing each other, and a third side surface and a fourth side surface connecting the first side surface and the second side surface to each other and facing each other, the light emitting element array being provided on the wiring substrate, a driving element that is provided on the wiring substrate on the first side surface side and drives the light emitting element array, a first circuit element and a second circuit element that are provided on the wiring substrate on the second side surface side to be arranged in a direction along the second side surface, and a wiring member that is provided on the third side surface side and the fourth side surface side and extends from a top electrode of the light emitting element array toward an outside of the light emitting element array.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: July 18, 2023
    Assignee: FUJIFILM Business Innovation Corp.
    Inventors: Kazuhiro Sakai, Daisuke Iguchi, Takeshi Minamiru, Yoshinori Shirakawa, Tomoaki Sakita, Tsutomu Otsuka
  • Patent number: 11699631
    Abstract: Semiconductor device includes circuit substrate, first semiconductor die, thermal interface material, package lid. First semiconductor die is disposed on and electrically connected to circuit substrate. Thermal interface material is disposed on first semiconductor die at opposite side of first semiconductor die with respect to circuit substrate. Package lid extends over first semiconductor die and is bonded to the circuit substrate. Package lid includes roof, footing, and island. Roof extends along first direction and second direction perpendicular to first direction. Footing is disposed at peripheral edge of roof and protrudes from roof towards circuit substrate along third direction perpendicular to first direction and second direction. Island protrudes from roof towards circuit substrate and contacts thermal interface material on first semiconductor die. Island is disconnected from footing along second direction.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: July 11, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Shen Yeh, Po-Yao Lin, Hui-Chang Yu, Shyue-Ter Leu, Shin-Puu Jeng
  • Patent number: 11694897
    Abstract: Disclosed herein are methods for backside wafer dopant activation using a high-temperature ion implant. In some embodiments, a method may include forming a semiconductor device atop a first main side of a substrate, and performing a high-temperature ion implant to a second main side of the substrate, wherein the first main side of the substrate is opposite the second main side of the substrate. The method may further include performing a second ion implant to the second main side of the substrate to form a collector layer.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: July 4, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Wei Zou
  • Patent number: 11676913
    Abstract: A semiconductor package includes a substrate. A first semiconductor chip is disposed on the substrate and is electrically connected to the substrate. The first semiconductor chip comprises a first sidewall extending in a first direction, a second sidewall extending in a second direction that crosses the first direction, and a third sidewall disposed between the first sidewall and the second sidewall and configured to connect the first sidewall and the second sidewall. The third sidewall has a curved surface shape. A second semiconductor chip is disposed on the first semiconductor chip and is electrically connected to the first semiconductor chip.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: June 13, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Eun-Kyoung Choi
  • Patent number: 11676939
    Abstract: A package includes a first molding material, a lower-level device die in the first molding material, a dielectric layer over the lower-level device die and the first molding material, and a plurality of redistribution lines extending into the first dielectric layer to electrically couple to the lower-level device die. The package further includes an upper-level device die over the dielectric layer, and a second molding material molding the upper-level device die therein. A bottom surface of a portion of the second molding material contacts a top surface of the first molding material.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Wei Chen, Jie Chen
  • Patent number: 11664338
    Abstract: A mechanism is described for facilitating stretchable and self-healing solders in microelectronics manufacturing environments. An apparatus of embodiments, as described herein, includes one or more solders associated with a microelectronics component, where the one or more solders contain a liquid metal and are wrapped in an encapsulation material. The apparatus further includes a substrate coupled to the one or more solders.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: May 30, 2023
    Inventor: Anwar A. Mohammed
  • Patent number: 11659665
    Abstract: A connection structure-embedded substrate includes: a printed circuit board including a plurality of first insulating layers of which at least one has a cavity provided therein, a plurality of first wiring layers disposed as at least one of an outer portion and an inner portion of the plurality of first insulating layers, and a first build-up insulating layer disposed on an upper surface of the plurality of first insulating layers; and a connection structure at least partially disposed in the cavity. The first build-up insulating layer is disposed in the cavity, and each of a lower surface of the connection structure and a lower surface of the cavity is in contact with at least a portion of the first build-up insulating layer, respectively.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: May 23, 2023
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ho Hyung Ham, Won Seok Lee, Jae Sung Sim
  • Patent number: 11655142
    Abstract: A method of manufacturing a sensor device comprising: configuring a moulding support structure and a packaging mould so as to provide predetermined pathways to accommodate a moulding compound, the moulding support structure defining a first notional volume adjacent a second notional volume. An elongate sensor element and the moulding support structure are configured so that the moulding support structure fixedly carries the elongate sensor element and the elongate sensor element resides substantially in the first notional volume and extends towards the second notional volume, the elongate sensor element having an electrical contact electrically coupled to another electrical contact disposed within the second notional volume. The moulding support structure carrying (102) the elongate sensor element is disposed within the packaging mould (106).
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: May 23, 2023
    Assignee: MELEXIS TECHNOLOGIES NV
    Inventor: Appolonius Jacobus Van Der Wiel
  • Patent number: 11640954
    Abstract: A semiconductor package structure includes a plurality of first dies spaced from each other, a molding layer between the first dies, a second die over the plurality of first dies and the molding layer, and an adhesive layer between the plurality of first dies and the second die, and between the molding layer and the second die. A first interface between the adhesive layer and the molding layer and a second interface between the adhesive layer and the plurality of first dies are at different levels.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: May 2, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jeng-Nan Hung, Chun-Hui Yu, Kuo-Chung Yee, Yi-Da Tsai, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh
  • Patent number: 11614592
    Abstract: Photonic devices and methods of manufacture are provided. In embodiments a fill material and/or a secondary waveguide are utilized in order to protect other internal structures such as grating couplers from the rigors of subsequent processing steps. Through the use of these structures at the appropriate times during the manufacturing process, damage and debris that would otherwise interfere with the manufacturing process of the device or operation of the device can be avoided.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: March 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Chih-Hsuan Tai, Hua-Kuei Lin, Tsung-Yuan Yu, Min-Hsiang Hsu
  • Patent number: 11617263
    Abstract: A method for manufacturing a circuit board embeds a portion of an outer circuit layer in an outer dielectric layer which increases contact area between the outer circuit layer and the outer dielectric layer, improving adhesion between the outer circuit layer and the outer dielectric layer, and reducing a thickness of the outer circuit substrate, thereby reducing the overall thickness of the finished circuit board.
    Type: Grant
    Filed: May 31, 2021
    Date of Patent: March 28, 2023
    Assignees: Avary Holding (Shenzhen) Co., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., GARUDA TECHNOLOGY CO., LTD.
    Inventors: Lin-Jie Gao, Yong-Chao Wei
  • Patent number: 11615972
    Abstract: A system for transfer of a plurality of die from a die source to a receive substrate is provided. The system includes a die source including a plurality of die, the plurality of die being coupled to a carrier. The system also includes a receive substrate to receive the plurality of die from the die source. The receive substrate includes a die catch material for receiving the plurality of die from the die source, the die catch material being reusable. The system also includes a laser source for providing energy to interact with a die release material to transfer the plurality of die from the die source to the receive substrate.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: March 28, 2023
    Inventors: Thomas Colosimo, Tao-Hua Lee, Ting-Chia Huang
  • Patent number: 11610835
    Abstract: An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: March 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Li-Ling Liao, Ming-Chih Yew, Chia-Kuei Hsu, Shu-Shen Yeh, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11610858
    Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming an insulation layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device to the insulation layer and a portion of the plurality of bond pads through hybrid bonding.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: March 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Fa Chen, Chen-Hua Yu
  • Patent number: 11562985
    Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a processor, an array of SRAM cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of DRAM cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer in are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: January 24, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Jun Liu, Weihua Cheng
  • Patent number: 11557491
    Abstract: A method of forming an assembly is provided. The method includes attaching a packaged semiconductor device to a substrate. An isolation structure is formed and located between the packaged semiconductor device and the substrate. An underfill material is dispensed between the packaged semiconductor device and the substrate. The isolation structure prevents the underfill material from contacting a first conductive connection formed between the packaged semiconductor device and the substrate.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: January 17, 2023
    Assignee: NXP B.V.
    Inventors: Leo van Gemert, Peter Joseph Hubert Drummen
  • Patent number: 11545435
    Abstract: Some features pertain to a substrate that includes a first portion of the substrate including a first plurality of metal layers, a second portion of the substrate including a second plurality of metal layers, and a plurality of insulating layers configured to separate the first plurality of metal layers and the second plurality of metal layers. A first plurality of posts and a plurality of interconnects are coupled together such that the first plurality of posts and the plurality of interconnects couple the first portion of the substrate to the second portion of the substrate.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: January 3, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Kuiwon Kang, Zhijie Wang, Hong Bok We
  • Patent number: 11545369
    Abstract: An electronic component includes a lead frame; a semiconductor chip arranged above the lead frame; and a connection layer sequence arranged between the lead frame and the semiconductor chip, wherein the connection layer sequence includes a first intermetallic layer including gold and indium or gold, indium and tin, a second intermetallic layer including indium and a titanium compound, indium and nickel, indium and platinum or indium and titanium, and a third intermetallic layer including indium and gold.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: January 3, 2023
    Assignee: OSRAM OLED GmbH
    Inventors: Mathias Wendt, Andreas Weimar
  • Patent number: 11538735
    Abstract: In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: December 27, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Rong Chun, Kuo Lung Pan, Pei-Hsuan Lee, Chien Ling Hwang, Yu-Chia Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chen-Hua Yu
  • Patent number: 11538783
    Abstract: A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower structure.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: December 27, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeonggi Jin, Solji Song, Taehwa Jeong, Jinho Chun, Juil Choi, Atsushi Fujisaki
  • Patent number: 11527456
    Abstract: A power module is provided with reduced power and gate loop inductance. The power module may be configured in a multi-layer manner with one or more organic substrates.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: December 13, 2022
    Assignee: UT-Battelle, LLC
    Inventors: Emre Gurpinar, Md Shajjad Chowdhury
  • Patent number: 11527467
    Abstract: According to the various aspects, a multi-chip semiconductor package includes a package substrate, an interconnect frame extending beyond a first side edge of the package substrate, the interconnect frame including a bottom surface positioned over and coupled to a top surface of the package substrate, a first semiconductor device positioned at least partially over and coupled to the interconnect frame, and a second semiconductor device positioned on the bottom surface of the interconnect frame alongside of the package substrate. The interconnect frame further includes a redistribution layer and a frame construct layer, and a plurality of vias coupled to the redistribution layer, with the frame construct layer further includes a recessed area, and the first semiconductor device is positioned in the recessed area.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: December 13, 2022
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Seok Ling Lim, Jackson Chung Peng Kong, Jenny Shio Yin Ong, Kooi Chi Ooi
  • Patent number: 11502015
    Abstract: Semiconductor package includes interposer, dies, encapsulant. Each die includes active surface, backside surface, side surfaces. Backside surface is opposite to active surface. Side surfaces join active surface to backside surface. Encapsulant includes first material and laterally wraps dies. Dies are electrically connected to interposer and disposed side by side on interposer with respective backside surfaces facing away from interposer. At least one die includes an outer corner. A rounded corner structure is formed at the outer corner. The rounded corner structure includes second material different from first material. The outer corner is formed by backside surface and a pair of adjacent side surfaces of the at least one die. The side surfaces of the pair have a common first edge. Each side surface of the pair does not face other dies and has a second edge in common with backside surface of the at least one die.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: November 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Wei Shen, Sung-Hui Huang, Shang-Yun Hou, Kuan-Yu Huang
  • Patent number: 11462452
    Abstract: A chip package structure including a chip, a stress buffer layer, a first insulating layer, a redistribution layer, a second insulating layer, and a solder ball is provided. The chip has an active surface, a back surface and a peripheral surface. The stress buffer layer covers the active surface and the peripheral surface, and the first insulating layer is disposed on the back surface. A bottom surface of the stress buffer layer is aligned with the back surface of the chip. The redistribution layer is electrically connected to the chip through an opening of the stress buffer layer. The second insulating layer covers the stress buffer layer and the redistribution layer. The solder ball is disposed in a blind hole of the second insulating layer and electrically connected to the redistribution layer. A top surface of the solder ball protrudes from an upper surface of the second insulating layer.
    Type: Grant
    Filed: January 24, 2021
    Date of Patent: October 4, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Pu-Ju Lin, Kai-Ming Yang, Cheng-Ta Ko
  • Patent number: 11450642
    Abstract: A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: September 20, 2022
    Assignee: Infineon Technologies AG
    Inventors: Edmund Riedl, Wu Hu Li, Alexander Heinrich, Ralf Otremba, Werner Reiss
  • Patent number: 11424203
    Abstract: A semiconductor module includes: a semiconductor device; a bonding layer that is arranged on the semiconductor device, contains nickel or copper, and is electrically connected to the semiconductor device; a solder portion containing gold, disposed on the bonding layer; and a protective layer disposed directly on the bonding layer, covering an outer peripheral edge of the bonding layer.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: August 23, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yasuaki Hozumi
  • Patent number: 11404344
    Abstract: A heat spreading plate is suitable to be a top cover of a chip package structure. The heat spreading plate includes a main body and an isolating frame. The main body includes a plurality of metal sheets which are arranged spaced apart from one another totally and capable of thermally connecting different working chips mounted within the chip package structure, respectively. A gap is formed between any two neighboring ones of the metal sheets to completely separate them. The isolating frame surrounds the outer edges of the metal sheets and fills into the gaps for fixedly holding the metal sheets together. One surface of the isolating frame is formed with a plurality of hollow recesses, and each of the metal sheets is exposed outwards from one of the hollow recesses.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: August 2, 2022
    Assignee: Jentech Precision Industrial Co., LTD.
    Inventor: Chun-Ta Yeh
  • Patent number: 11393720
    Abstract: A method for separating semiconductor dies of a semiconductor die assembly comprises depositing a first coating on a first surface of the assembly. The assembly comprises a die wafer having a plurality of semiconductor dies and first and second surfaces. A first portion of the die wafer and the first coating is removed between adjacent semiconductor dies to form trenches having an intermediate depth in the die wafer between first and second surfaces such that die corners are formed on either side of the trenches. A protective coating is deposited on the first surface of the die assembly to cover the die corners, trenches and at least a portion of the first coating. The first coating is selectively removed such that portions of the protective coating covering die corners and trenches remain on the die wafer. Adjacent semiconductor dies are separated and the protective coating remains covering the die corners.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Po Chih Yang
  • Patent number: 11367667
    Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: June 21, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Hong Wan Ng, Choon Kuan Lee, David J. Corisis, Chin Hui Chong
  • Patent number: 11367995
    Abstract: An electronic device according to a present disclosure includes a semiconductor substrate, a chip, and a connection part. The chip has a different thermal expansion rate from that of the semiconductor substrate. The connection part includes a porous metal layer for connecting connection pads that are arranged on opposing principle surfaces of the semiconductor substrate and the chip.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: June 21, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Takashi Imahigashi, Kaoru Tanaka, Masashi Miyazaki
  • Patent number: 11335614
    Abstract: In an electric component embedded structure, a first electrode terminal provided on a first main surface includes an intra-area terminal, and the intra-area terminal is electrically connected to an overlap portion of an overlap wiring in a formation area of an electric component. Accordingly, a decrease in mounting area of the electric component embedded structure is achieved. The intra-area terminal can be electrically connected to a second electrode terminal provided on a second main surface via a first via-conductor, the overlap wiring, and a second via-conductor. The intra-area terminal is connected to a wiring (an overlap wiring) of a first insulating layer without additionally providing a rewiring layer causing an increase in thickness, and the increase in thickness is curbed, whereby a decrease in size of the electric component embedded structure is achieved.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: May 17, 2022
    Assignee: TDK CORPORATION
    Inventors: Takaaki Morita, Kenichi Yoshida, Mitsuhiro Tomikawa
  • Patent number: 11328978
    Abstract: A device package and a method of forming a device package are described. The device package has dies disposed on a substrate, and one or more layers with a high thermal conductivity, referred to as the highly-conductive (HC) intermediate layers, disposed on the dies on the substrate. The device package further includes a lid with legs on an outer periphery of the lid, a top surface, and a bottom surface. The legs of the lid are attached to the substrate with a sealant. The bottom surface of the lid is disposed over the one or more HC intermediate layers and the one or more dies on the substrate. The device package may also include thermal interface materials (TIMs) disposed on the HC intermediate layers. The TIMs may be disposed between the bottom surface of the lid and one or more top surfaces of the HC intermediate layers.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Feras Eid, Johanna M. Swan, Sergio Chan Arguedas, John J. Beatty
  • Patent number: 11315821
    Abstract: A processing method for a wafer includes the steps of forming a frame unit having a ring-shaped frame, providing a resin sheet, fixing the resin sheet, which covers the wafer at its front side, at its outer peripheral edge, on the ring-shaped frame, forming through-holes in the resin sheet, holding the frame unit on a side of the resin sheet under suction on a holding surface to fix the ring-shaped frame, applying a laser beam to the wafer to form modified layers inside the wafer, and separating the resin sheet. In the holding step, the adhesive tape is suctioned under a negative pressure acting from the holding surface via through-holes while the front side of the wafer is prevented by the resin sheet from being suctioned on the holding surface.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: April 26, 2022
    Assignee: DISCO CORPORATION
    Inventor: Jinyan Zhao