Emitter Dip Prevention Or Utilization Patents (Class 438/346)
  • Patent number: 8653627
    Abstract: A semiconductor crystal having a recombination-inhibiting semiconductor layer of a second conductive type that is disposed in the vicinity of the surface between a base contact region and emitter regions and that separates the semiconductor surface having a large number of surface states from the portion that primarily conducts the positive hole electric current and the electron current. Recombination is inhibited, and the current amplification factor is thereby improved and the ON voltage reduced.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: February 18, 2014
    Assignee: Honda Motor Co., Ltd.
    Inventor: Ken-ichi Nonaka
  • Patent number: 8460994
    Abstract: A semiconductor crystal includes a recombination-inhibiting semiconductor layer (17) of a second conductive type that is disposed in the vicinity of the surface between a base contact region (16) and emitter regions (14) and that separates the semiconductor surface having a large number of surface states from the portion that primarily conducts the positive hole electric current and the electron current. Recombination is inhibited, and the current amplification factor is thereby improved and the ON voltage reduced.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: June 11, 2013
    Assignee: Honda Motor Co., Ltd.
    Inventor: Ken-ichi Nonaka
  • Patent number: 8021951
    Abstract: Provided is a semiconductor device including: a silicon substrate; at least two trenches spaced apart from each other, being in parallel with each other, and being formed by vertically etching the silicon substrate from a surface thereof; an electrically insulating film for burying therein at least bottom surfaces of the trenches; a base region formed in a region of the silicon substrate located between the two trenches; and an emitter region and a collector region formed on portions of side surfaces of the trenches, respectively, the portions of the sides located above the insulating film and formed in the base region.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: September 20, 2011
    Assignee: Seiko Instruments Inc.
    Inventor: Kazuhiro Tsumura
  • Patent number: 6773978
    Abstract: Methods are disclosed for manufacturing semiconductor devices with silicide metal gates, wherein a single-step anneal is used to react a metal such as cobalt or nickel with substantially all of a polysilicon gate structure while source/drain regions are covered. A second phase conductive metal silicide is formed consuming substantially all of the polysilicon and providing a substantially uniform work function at the silicide/gate oxide interface.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: August 10, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Paul Raymond Besser, Eric Paton, James Pan
  • Patent number: 6616786
    Abstract: The invention is directed to a returnable plastic crate provided on at least one surface with an ink only label that is removable without destructive treatment of the said surface, said label being adhered to said at least one surface by an activated adhesive layer.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: September 9, 2003
    Assignee: Heineken Technical Services B.V.
    Inventors: Patrick Johannes Blom, Erwin Anton Rosens, Thomas Lynn Brandt, Daniel Nathaniel Wilkens
  • Patent number: 6420238
    Abstract: Described in the disclosure is a method for fabricating high-capacitance capacitive elements that are integrated in a semiconductor substrate. First a dielectric layer is formed over the surface of the substrate and a metal layer is deposited thereon. The metal layer is patterned and etched to form lower plates of the capacitive elements, as well as to form interconnection pads. Then, an intermediate dielectric layer is deposited on the lower plates and interconnection pads, and over the entire exposed surface of the substrate. Following that, a sacrificial conductive layer is deposited onto the intermediate dielectric layer, and the upper plates of the capacitive elements are formed out of the sacrificial conductive layer. Then, an upper dielectric layer is formed over the entire semiconductor, and openings are formed in this layer for the upper plates and the interconnection pads.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: July 16, 2002
    Assignee: STMicroelectronics S.r.l.
    Inventors: Sebastiano Ravesi, Antonello Santangelo