Abstract: A method of fabricating a semiconductor device includes performing an optical proximity correction (OPC) operation on a design pattern of a layout, and forming a photoresist pattern on a substrate, using a photomask which is manufactured with the layout corrected by the OPC operation. The OPC operation includes generating a target pattern based on the design pattern, performing a first OPC operation, based on the target pattern, to generate a first correction pattern, measuring a target error by comparing a first simulation image of the first correction pattern with the target pattern, generating a retarget pattern from the target pattern, based on the target error, and performing a second OPC operation, based on the retarget pattern, to generate a second correction pattern.

Abstract: An imprint method of molding an imprint material on a shot region of a substrate using a mold, includes aligning the shot region and the mold in a state where the imprint material and a pattern region of the mold are in contact with each other; and curing the imprint material by irradiating the imprint material with curing light after the aligning. The aligning is controlled so as to include an overlap period during which a period during which deformation light used to deform the shot region is applied to the substrate through the imprint material and a period during which polymerization light used to increase a viscosity of the imprint material is applied to the imprint material overlap each other. The polymerization light to be applied to the imprint material is controlled in accordance with the deformation light to be applied to the imprint material during the overlap period.

Abstract: Systems and methods for semiconductor adaptive testing using inline defect part average testing are configured to receive a plurality of inline defect part average testing (I-PAT) scores from an I-PAT system, where the plurality of I-PAT scores is generated by the I-PAT system based on semiconductor die data for a plurality of semiconductor dies, where the semiconductor die data includes characterization measurements for the plurality of semiconductor dies, where each I-PAT score of the plurality of I-PAT scores represents a weighted defectivity determined by the I-PAT system based on a characterization measurement of a corresponding semiconductor die of the plurality of semiconductor dies; apply one or more rules to the plurality of I-PAT scores during a dynamic decision-making process; and generate one or more adaptive tests for at least one semiconductor die of the plurality of semiconductor dies based on the dynamic decision-making process.

Abstract: A method for determining a correction for an apparatus used in a process of patterning substrates, the method including: obtaining a group structure associated with a processing history and/or similarity in fingerprint of to be processed substrates; obtaining metrology data associated with a plurality of groups within the group structure, wherein the metrology data is correlated between the groups; and determining the correction for a group out of the plurality of groups by applying a model to the metrology data, the model including at least a group-specific correction component and a common correction component.

Abstract: A substrate processing apparatus includes a holder having thereon an attraction surface configured to attract a substrate and including, as multiple regions in which attracting pressures for attracting the substrate are controlled independently, a first region having a circular shape and a second region having an annular shape and disposed at an outside of the first region in a diametrical direction; multiple attracting pressure generators configured to independently generate the attracting pressures respectively in the multiple regions forming the attraction surface; multiple attracting pressure adjusters configured to independently adjust the attracting pressures respectively generated by the attracting pressure generators; and a controller configured to control the multiple attracting pressure generators and the multiple attracting pressure adjusters. The controller generates different attracting pressures in at least a part of the first region and in at least a part of the second region.

Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A first depth parameter (t) of the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on the first depth parameter (t).

Abstract: Panel level packaging (PLP) with high accuracy and high scalability is disclosed. The PLP includes dies bonded face down onto an alignment carrier configured with die bond regions. Pre-bond and post bond inspection are performed at the carrier level to ensure accurate bonding of the dies to the carrier.

Abstract: A multilayer light emitting device having a plurality of low Si—H bonding dielectric layers is disclosed for improved p-GaN contact performance. Improved p-side contact resistance is provided using one or more bonding, via or passivation layers in a multilayer light emitting structure by the use of processes and dielectric materials and precursors that provide dielectric layers with a hydrogen content of less than 13 at. %.

Abstract: Indexes having local features are automatically selected from sensor data of a plurality of sensors. Sensor data of the plurality of sensors, each associated with the plurality of indexes, is partitioned into a plurality of blocks. A principal component analysis is applied to the sensor data of each of the partitioned blocks and a plurality of principal components are extracted from each of the blocks. A migration distance evaluation unit extracts, from two different blocks, two principal components that form a principal component pair, and calculates a migration distance between each of the principal components regarding the extracted principal component pair. A migration factor index detection unit detects, as a migration factor index, an index among the plurality of indexes configuring the principal components having a large migration distance among the migration distances between each of the principal components calculated by the migration distance evaluation unit.

Abstract: Embodiments of this disclosure include a method of processing a substrate that includes etching a first dielectric material formed on a substrate that is disposed on a substrate supporting surface of a substrate support assembly disposed within a processing region of a plasma processing chamber. The etching process may include delivering a process gas to the processing region, wherein the process gas comprises a first fluorocarbon containing gas and a first process gas, delivering, by use of a radio frequency generator, a radio frequency signal to a first electrode to form a plasma in the processing region, and establishing, by use of a first pulsed-voltage waveform generator, a first pulsed voltage waveform at a biasing electrode disposed within the substrate support assembly.

Abstract: An ink jet process is used to deposit a material layer to a desired thickness. Layout data is converted to per-cell grayscale values, each representing ink volume to be locally delivered. The grayscale values are used to generate a halftone pattern to deliver variable ink volume (and thickness) to the substrate. The halftoning provides for a relatively continuous layer (e.g., without unintended gaps or holes) while providing for variable volume and, thus, contributes to variable ink/material buildup to achieve desired thickness. The ink is jetted as liquid or aerosol that suspends material used to form the material layer, for example, an organic material used to form an encapsulation layer for a flat panel device. The deposited layer is then cured or otherwise finished to complete the process.

Abstract: A method of making a semiconductor device is provided for depositing, patterning, and developing photoresist (1703, 1704) on an underlying layer located on a backside of a wafer having a frontside on which an integrated circuit die are formed over a shared wafer semiconductor substrate and arranged in a grid, thereby forming a patterned photoresist mask with a unique set of one or more openings which are used to selectively etch the underlying layer to form, on each integrated circuit die, a unique die mark identifier pattern of etched openings in the underlying layer corresponding to the unique set of one or more openings in the patterned photoresist mask (1705), where the patterned photoresist mask is removed (1706) from the backside of the wafer before singulating the wafer to form a plurality of integrated circuit devices (1708) which each include a unique die marking.

Abstract: An object of the present invention is to provide a plasma processing method capable of removing complex depositions of metal and non-metal deposited in a processing chamber by etching processing of a wafer to reduce generation of particle due to the depositions, in a plasma processing method for plasma-etching the wafer such as a semiconductor substrate. According to the present invention, there is provided a plasma processing method for plasma-etching a sample in a processing chamber and plasma-cleaning the inside of the processing chamber, the method comprising: an etching step for plasma-etching a predetermined number of the samples; a metal removing step of removing a deposited film containing a metal element by using a plasma after the etching step; and a non-metal removing step of removing the deposited film containing the non-metal element by using a plasma different from the plasma in the metal removing step, in which the metal removing step and the non-metal removing step are repeated twice or more.

Abstract: Described herein is a technique capable of optimizing a timing of a maintenance process. According to one aspect of the technique of the present disclosure, there is provided a method of manufacturing a semiconductor device including: (a) transferring a substrate from a storage container storing one or more substrates including the substrate to a process chamber, and performing a substrate processing; (b) receiving maintenance reservation information of the process chamber; and (c) continuously performing the substrate processing after the maintenance reservation information is received in (b) until the substrate processing in the process chamber related to the maintenance reservation information is completed, and setting the process chamber to a maintenance enable state after the substrate processing is completed by stopping the one or more substrates from being transferred into the process chamber.

Abstract: Described herein is a technique capable of optimizing a timing of a maintenance process. According to one aspect of the technique of the present disclosure, there is provided a method of manufacturing a semiconductor device including: (a) transferring a substrate from a storage container storing one or more substrates including the substrate to a process chamber, and performing a substrate processing; (b) receiving maintenance reservation information of the process chamber; and (c) continuously performing the substrate processing after the maintenance reservation information is received in (b) until the substrate processing in the process chamber related to the maintenance reservation information is completed, and setting the process chamber to a maintenance enable state after the substrate processing is completed by stopping the one or more substrates from being transferred into the process chamber.

Abstract: A wafer-level system-in-package (WLSiP) package structure is provided. The WLSiP package structure includes a device wafer, an adhesive layer, and a plurality of second chips. The device wafer includes a first front surface having a plurality of first chips integrated therein and a first back surface opposing the first front surface. The adhesive layer is formed on the first front surface of the device wafer and the adhesive layer includes a plurality of through-holes exposing the first front surface. The plurality of second chips are bonded to the device wafer, and the plurality of second chips are bonded with the adhesive layer to cover the plurality of first through-holes in a one-to-one correspondence.

Abstract: A substrate support assembly comprises a plurality of zones, a chuck comprising a ceramic body, and an additional assembly bonded to a lower surface of the chuck. The additional assembly comprises a second body and a plurality of temperature sensors disposed in or on the second body, wherein each zone of the plurality of zones includes at least one of the plurality of temperature sensors. A plurality of spatially tunable heating elements are disposed a) in or on the ceramic body or b) in or on the second body.

Abstract: A method for manufacturing an SOI wafer by performing a sacrificial oxidation treatment and reducing a thickness of an SOI layer of the SOI wafer, in which: the SOI wafer on which the sacrificial oxidation treatment is performed has a film thickness distribution with a one-way sloping shape; a thermal oxidation in the sacrificial oxidation treatment is performed by combining a non-rotating oxidation and a rotating oxidation, using a vertical heat treatment furnace; whereby a thermal oxide film having an oxide film thickness distribution with a one-way sloping shape canceling the film thickness distribution with a one-way sloping shape of the SOI layer, is formed on a surface of the SOI layer; and by removing the formed thermal oxide film, an SOI wafer having an SOI layer whose film thickness distribution with a one-way sloping shape has been resolved is manufactured.

Abstract: A substrate stacking apparatus that stacks first and second substrates on each other, by forming a contact region where the first substrate held by a first holding section and the second substrate held by a second holding section contact each other, at one portion of the first and second substrates, and expanding the contact region from the one portion by releasing holding of the first substrate by the first holding section, wherein an amount of deformation occurring in a plurality of directions at least in the first substrate differs when the contact region expands, and the substrate stacking apparatus includes a restricting section that restricts misalignment between the first and second substrates caused by a difference in the amount of deformation. In the substrate stacking apparatus above, the restricting section may restrict the misalignment such that an amount of the misalignment is less than or equal to a prescribed value.

Abstract: An epitaxy substrate and a method of manufacturing the same are provided. The epitaxy substrate includes a device substrate and a handle substrate. The device substrate has a first surface and a second surface opposite to each other, and a bevel disposed between the first and the second surfaces. The handle substrate is bonded to the second surface of the device substrate, wherein the oxygen content of the device substrate is less than the oxygen content of the handle substrate, and a bonding angle greater than 90° is between the bevel of the device substrate and the handle substrate.

Abstract: A method including evaluating, with respect to a parameter representing remaining uncertainty of a mathematical model fitting measured data, one or more mathematical models for fitting measured data and one or more measurement sampling schemes for measuring data, against measurement data across a substrate, and identifying one or more mathematical models and/or one or more measurement sampling schemes, for which the parameter crosses a threshold.

Abstract: In a substrate transportation method, a first movement process is provided for moving a camera to a position above a predetermined region where a peripheral edge of a substrate is supposed to be located in a state where the substrate is lifted by pins protruding beyond a mounting table while a transfer mechanism that has received an instruction for starting an unloading of the substrate mounted on the mounting table is moving to the mounting table. Further, a first image capturing process is provided for controlling the camera moved in the first movement process to capture an image of the predetermined region, and a first detection process is provided for detecting a positional displacement and/or a tilting of the substrate lifted by the pins based on the image captured by the camera in the first image capturing process.

Abstract: A method of electrical device manufacturing that includes measuring a first plurality of dimensions and electrical performance from back end of the line (BEOL) structures; and comparing the first plurality of dimensions with a second plurality of dimensions from a process assumption model to determine dimension variations by machine vision image processing. The method further includes providing a plurality of scenarios for process modifications by applying machine image learning to the dimension variations and electrical variations in the in line electrical measurements from the process assumption model. The method further includes receiving production dimension measurements and electrical measurements at a manufacturing prediction actuator. The at least one of the dimensions or electrical measurements received match one of the plurality of scenarios the manufacturing prediction actuator using the plurality of scenarios for process modifications effectuates a process change.

Abstract: In a lithographic process in which a series of substrates are processed in different contexts, object data (such as performance data representing overlay measured on a set of substrates that have been processed previously) is received. Context data represents one or more parameters of the lithographic process that vary between substrates within the set. By principal component analysis or other statistical analysis of the performance data, the set of substrates are partitioned into two or more subsets. The first partitioning of the substrates and the context data are used to identify one or more relevant context parameters, being parameters of the lithographic process that are observed to correlate most strongly with the first partitioning. The lithographic apparatus is controlled for new substrates by reference to the identified relevant context parameters. Embodiments with feedback control and feedforward control are described.

Abstract: Disclosed a substrate liquid processing apparatus including: a liquid processing section configured to process a substrate with a processing liquid; a processing liquid supply section configured to supply the processing liquid; a diluent supply section configured to supply a diluent for diluting the processing liquid; a controller configured to control the diluent supply section; a concentration detection unit configured to detect a concentration of the processing liquid; and an atmospheric pressure detection unit configured to detect an atmospheric pressure.

Abstract: Heat treatment is performed on a dummy wafer with halogen lamps or the like to perform dummy treatment of adjusting the temperature of in-chamber structures including a susceptor and the like. A dummy recipe for the dummy treatment is prepared in advance, and a maximum value and a minimum value each being a threshold for the number of times of dummy treatment are set. After the dummy treatment is started, the number of times of dummy treatment is counted. Comparison determination between the number of times of dummy treatment at the time point when carriers storing semiconductor wafers each to be a product are transported in to a heat treatment apparatus and the set maximum value and minimum value is performed. In this manner, the timing of the end of the dummy treatment and the start of the treatment of product wafers is adjusted.

Abstract: Systems and methods used to deliver a processing gas having a desired diborane concentration to a processing volume of a processing chamber are provided herein. In one embodiment a system includes a borane concentration sensor. The borane concentration sensor includes a body and a plurality of windows. Here, individual ones of the plurality of windows are disposed at opposite ends of the body and the body and the plurality of windows collectively define a cell volume. The borane concentration sensor further includes a radiation source disposed outside of the cell volume proximate to a first window of the plurality of windows, and a radiation detector disposed outside the cell volume proximate to a second window of the plurality of windows.

Abstract: A method for producing a semiconductor chip (100) is provided, in which, during a growth process for growing a first semiconductor layer (1), an inhomogeneous lateral temperature distribution is created along at least one direction of extent of the growing first semiconductor layer (1), such that a lateral variation of a material composition of the first semiconductor layer (1) is produced. A semiconductor chip (100) is additionally provided.

Abstract: Disclosed is a method for performing a liquid processing on a substrate using an aqueous solution of a chemical agent at a predetermined concentration as a processing liquid. The method includes: storing the processing liquid in a processing liquid storage unit; and supplying an aqueous solution of the chemical agent at a different concentration from the concentration of the processing liquid to the processing liquid storage unit, discharging the processing liquid from the processing liquid storage unit so as to update the processing liquid stored in the processing liquid storage unit. The aqueous solution in a predetermined amount is supplied to the processing liquid storage unit, and the processing liquid is discharged from the processing liquid storage unit, the processing liquid containing the chemical agent in the same amount as the amount of the chemical agent contained in the aqueous solution supplied to the processing liquid storage unit.

Abstract: A system includes an image processing module configured to receive an image, captured by an imaging device, of a plasma environment within a substrate processing chamber during processing of a substrate and extract one or more features of the image indicative of a plasma sheath formed within the plasma environment during the processing of the substrate. A control module is configured to determine a plasma sheath profile based on the one or more features extracted from the image and selectively adjust at least one processing parameter related to the processing of the substrate based on the plasma sheath profile.

Abstract: The present invention provides a method for dicing a substrate on a composite film. A work piece having a support film, a frame and a substrate is provided. The substrate has a top surface and a bottom surface. The top surface of the substrate has at least one die region and at least one street region. The composite film is interposed between the substrate and the support film. Substrate material is etched from the at least one street region to expose a portion of the composite film using a substrate etch process. A first component of the composite film is etched using a first etch process. A second component of the exposed portion of the composite film is plasma etched using a second etch process.

Abstract: An apparatus for CMP includes a wafer carrier retaining a semiconductor wafer during a polishing operation, a slurry dispenser dispensing an abrasive slurry, and a temperature control system monitoring and controlling a temperature variation during the polishing operation. The temperature control system includes a temperature sensor detecting a temperature during the polishing operation and providing a signal corresponding to the temperature, a temperature controller coupled to the temperature sensor and receiving the signal from the temperature sensor, and a cooling device coupled to the temperature controller and providing a coolant to the apparatus for CMP.

Abstract: A system includes at least one tool, a storage device and a processor. The at least one tool performs semiconductor fabrication processes on at least one wafer, in which the at least one tool includes sensors. The storage device stores computer program codes. The processor executes the computer program codes in the storage device for: modeling profiles from the sensors to generate a modeling result; extracting features from the modeling result corresponding to the modeled profiles; based on the extracted features, extracting scores each representing a degree of the at least one wafer being processed by the at least one tool; and based on the extracted scores, displaying a ranking for fault detection of the at least one wafer.

Abstract: Provided are a multi-sensor device capable of implementing a pressure sensor function and an acceleration sensor function by using one housing, and a method of manufacturing the multi-sensor device. The multi-sensor device may include a lead frame, a pressure sensing element electrically connected to the lead frame and being capable of measuring a relative pressure between a first part and a second part thereof, an acceleration sensor module electrically connected to the lead frame and being capable of measuring acceleration applied to an ambient environment thereof, and a housing mounted to protect at least a part of the lead frame, the pressure sensing element, and the acceleration sensor module, including a reference medium inlet hole to apply a pressure of a reference medium to the first part, and including a target medium inlet hole to apply a pressure of a target medium to the second part.

Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A first depth parameter (t) of the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on the first depth parameter (t).

Abstract: Methods of processing a semiconductor device structure comprise cooling an electrostatic chuck (ESC) for the semiconductor device structure, which comprises tiers of alternating materials including at least one dielectric material, to a temperature of ?30° C. or less, forming an opening in the semiconductor device structure with a plasma of a gas comprising a hydrogen-based gas and a fluorine-based gas in which the hydrogen-based gas comprises between about 10 vol % and 90 vol %. Other methods of processing a semiconductor device structure comprise cooling an ESC for the semiconductor device structure to a temperature of ?30° C. or less, applying a low frequency radio frequency (RF) having a non-sinusoidal waveform to the ESC, and forming an opening in the semiconductor device structure with a generated plasma. A processing system includes an ESC, a coolant system, and a low frequency RF power source generating a non-sinusoidal waveform comprising a combination of multiple sinusoidal waveforms.

Abstract: A method of inspecting a material comprising: producing at least one eddy current excitation in a material under test; sensing said at least one eddy current excitation in the material under test; wherein the method comprises using a low cross-correlation coded spread spectrum to produce said at least one eddy current excitation, and using a correlation technique to make a determination of amplitude and phase of the sensed eddy current excitation; wherein the method further comprises using the determination to make an assessment of the material under test.

Abstract: An electron microscope device includes: a first detection means disposed at a high elevation angle for detecting electrons having relatively low energy; a second detection means disposed at a low elevation angle for detecting electrons having relatively high energy; a means for identifying, from a first image obtained from a first detector, a hole region in a semiconductor pattern within a preset region; a means for calculating for individual holes, from a second image obtained from a second detector, indexes pertaining to an inclined orientation and an inclination angle, on the basis of the distance between the outer periphery of the hole region and the hole bottom; and a means for calculating, from the results measured for the individual holes, indexes pertaining to an inclined orientation of the hole and an inclination angle of the hole as representative values for the image being measured.

Abstract: A spectroscopy method and system, the method comprising irradiating an object with a laser-accelerated particle beam and detecting photons emitted by the object as a result of the interaction between the laser-accelerated particle beam and the object. The system comprises a laser; a particle source, positioned at a distance from the object; and a spectrometer and a detector; wherein the particle source generates a laser-accelerated particle beam under irradiation by the laser; and the spectrometer and the detector detect photons emitted from the object under irradiation by the laser-accelerated particle beam.

Abstract: A wafer processing method for forming cut grooves in streets of a wafer provided with a plurality of devices includes a holding step ST1 of holding the back surface side of the wafer by a holding surface of a chuck table, a measurement step ST2 of partitioning the front surface of the wafer held by the chuck table into a plurality of regions and measuring the surface height of the streets in each of the regions, a region-basis height setting step ST3 of setting the lowest surface height in each region as the surface height of the wafer in each region, and a cutting step ST4 of forming cut grooves in the front surface of the wafer while setting, on a region basis, a tip position of a cutting blade, based on the surface height of the wafer set in the region-basis height setting step ST3.

Abstract: In a calculator in a MEMS manufacturing system, a stage control unit inclines a stage based on a stage angle 1 setting a stage inclination angle and a stage angle 2 of the inclination angle different from the stage angle 1. A stage-angle calculation unit calculates the stage inclination angles from first and second images acquired by a SEM apparatus when the stage control unit sets the stage at the stage angles 1 and 2. A 3D-data creation unit creates three-dimensional device data from a third image that is a device image acquired when the stage is set at the stage angle 1 and a fourth image that is a device image acquired when the stage is set at the stage angle 2. When the three-dimensional device data is created, a correction value calculated from the stage angles 1 and 2 and the first and second images is used.

Abstract: A processing method for a workpiece includes: a holding step of holding the workpiece by a chuck table; a groove forming step of moving the chuck table in a processing feeding direction at a first speed, and sequentially cutting a plurality of division lines extending in a first direction by a first cutting blade to form the workpiece with grooves along the division lines; a first deep-cutting step of further cutting the grooves, by a second cutting blade, to thereby deep-cut the grooves, during when the groove forming step is performed; and a second deep-cutting step of moving the chuck table in the processing feeding direction at a second speed higher than the first speed, and further cutting by the second cutting blade those of the grooves which have not been deep-cut in the first deep-cutting step, to thereby deep-cut those grooves, after the groove forming step.

Abstract: The present invention provides a method and a device for repairing semiconductor chips. The method includes providing an LED module including a circuit substrate and a plurality of light-emitting units; driving the light-emitting units by a signal generator; measuring at least one light-emitting unit by a feature detector module so as to obtain an abnormal feature and define the at least one light-emitting unit as a bad light-emitting unit having the abnormal feature; projecting a laser light source generated by a laser generating module onto the bad light-emitting unit; removing the bad light-emitting unit from the circuit substrate by a chip pick-and-place module to form a vacancy; placing a good light-emitting unit inside the vacancy by the chip pick-and-place module; and electrically connecting the good light-emitting unit to the circuit substrate. Therefore, the bad light-emitting unit is replaced by the good light-emitting unit for repairing the LED module.

Abstract: Lithography systems and methods are provided with enhanced performance based on broader utilization of the integrated metrology tool in the printing tool to handle the metrology measurements in the system in a more sophisticated and optimized way. Additional operation channels are disclosed, enabling the integrated metrology tool to monitor and/or allocate metrology measurements thereby and by a standalone metrology tool with respect to specified temporal limitations of the printing tool; to adjust and optimize the metrology measurement recipes; to provide better process control to optimize process parameters of the printing tool; as well as to group process parameters of the printing tool according to a metrology measurements landscape.

Abstract: A method for minimizing a test set for optimal coverage is disclosed. The method includes generating a first test set which is both an empty and minimal test set. Then, generating a second test set with a predetermined number of tests. Further, partitioning the second test set into a control test set and an experiment test set. Subsequently, providing a list of tests for coverage by merging the control test set with the first test set to form a merged list of sets.

Abstract: A film growth apparatus according to one aspect of the present disclosure includes: a reactor configured to perform film growth processing on a substrate; an exhaust configured to discharge an exhaust gas from the reactor to the outside; a first valve including a valving element, the first valve provided in a pipe connecting the reactor with the exhaust and configured to control a pressure of the reactor by a position of the valving element; a valving element driver configured to cause the valving element to operate; and a valve controller including a closed position storage configured to store a closed position of the valving element, an opening degree controller configured to control the position of the valving element operated by the valving element driver, and a closed position shifter configured to detect a load of the valving element driver and shift the closed position in a case where the load exceeds a predetermined reference value.

Abstract: An apparatus of a wafer processing apparatus includes at least one memory and logic, at least a portion of which is implemented in circuitry of the wafer processing apparatus including at least one processor coupled to the at least one memory. The logic may provide a 3D model of a surface of a wafer, the wafer defining a wafer plane; and modify a surface feature in a Z-direction along the surface of the wafer based on at least one of: an X-critical dimension (CD) extending along an X-direction of the wafer plane, and a Y-CD extending along a Y direction of the wafer plane.

Abstract: A method of forming semiconductor memory device including following steps. Firstly, a substrate having a memory cell region and a peripheral region is provided, and a first semiconductor layer is formed on the substrate within the periphery region. Next, an insulating layer and a second semiconductor layer are formed on the substrate, and the second semiconductor layer covers the substrate, the first semiconductor layer and the insulating layer. Then, a sacrificial layer is formed on the second semiconductor layer, wherein top surfaces of the sacrificial layer within the memory cell region and the periphery region are coplanar. Following these, a removing process is performed to remove the sacrificial layer, the second semiconductor layer and the insulating layer, to expose the first semiconductor layer. After that, a top surface of the first semiconductor layer is leveled with a top surface of the second semiconductor layer.

Abstract: A substrate processing method comprises: an execution step of executing the first processing for the plurality of substrates, and executing the second processing for the substrates having undergone the first processing; a recovery step of recovering the plurality of substrates having undergone the first processing and the second processing to the retraction chamber; a conditioning step of, after completion of the first processing for the last substrate among the plurality of substrates, loading a dummy substrate into the first processing chamber, executing the third processing for the dummy substrate, and unloading the dummy substrate from the first processing chamber; and a second execution step of, after the dummy substrate is unloaded from the first processing chamber in the conditioning step, loading the substrates recovered in the recovery step into the first processing chamber, and executing the third processing for the substrates loaded into the first processing chamber.

Abstract: A catalyst is imparted selectively to a plateable material portion 32 by performing a catalyst imparting processing on a substrate W having a non-plateable material portion 31 and the plateable material portion 32 formed on a surface thereof. Then, a hard mask layer 35 is formed selectively on the plateable material portion 32 by performing a plating processing on the substrate W. The non-plateable material portion 31 is made of SiO2 as a main component, and the plateable material portion 32 is made of a material including, as a main component, a material containing at least one of a OCHx group and a NHx group, a metal material containing Si as a main component, a material containing carbon as a main component or a catalyst metal material.