Abstract: A device includes a channel layer, a gate structure, a source/drain epitaxial structure, and a gate via. The gate structure wraps around the channel layer. The gate structure includes a gate dielectric layer and a gate electrode over the gate dielectric layer. The source/drain epitaxial structure is adjacent the gate structure and is electrically connected to the channel layer. The gate via is under the gate structure and is in contact with a bottom surface of the gate electrode.

Abstract: A microelectromechanical system device includes a substrate, a dielectric layer, an electrode, a surface modification layer and a membrane. The dielectric layer is formed on the substrate, and is formed with a cavity that is defined by a cavity-defining wall. The electrode is formed in the dielectric layer. The surface modification layer covers the cavity-defining wall, and has a plurality of hydrophobic end groups. The membrane is connected to the dielectric layer, and seals the cavity. The membrane is movable toward or away from the electrode. A method for making a microelectromechanical system device is also provided.

Abstract: A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

Abstract: According to one embodiment, a template is provided with a transferring pattern on a first surface of a substrate. The transferring pattern includes a first projecting portion that projects from the first surface with a first height and extends in a first direction along the first surface, a second projecting portion that projects from the first surface with a second height higher than the first height and extends in a second direction along the first surface, a first columnar portion that is arranged at a position overlapping with the first projecting portion and has a top surface with a third height higher than the second height as a height from the first surface, and a second columnar portion that is arranged at a position overlapping with the second projecting portion and has a top surface with the third height as a height from the first surface.

Abstract: A method for forming a patterned mask layer is provided. The method includes forming a first layer over a substrate. The method includes forming a first strip structure and a second strip structure over the first layer. The method includes forming a spacer layer conformally covering the first strip structure, the second strip structure, and the first layer. The method includes forming a block structure in the first trench. The method includes removing a first portion of the spacer layer, which is under the first trench and not covered by the block structure, and a second portion of the spacer layer, which is over the first strip structure and the second strip structure. The method includes forming a third strip structure in the second trench and the third trench. The method includes removing the block structure. The method includes removing the spacer layer.

Abstract: A photoelectric device includes a target substrate, a circuit pattern layer disposed on the target substrate, a plurality of micro photoelectric elements electrically connected to the circuit pattern layer, and a supplemental repair element electrically connected to the circuit pattern layer. The target substrate is configured with a plurality of connection positions and a repair position disposed with an offset with relative to a corresponding one of the connection positions. The offset is greater than or equal to zero. The micro photoelectric elements are individually disposed on at least a part of the connection positions of the target substrate. The supplemental repair element has an electrode disposed on the repair position of the target substrate, and the electrode is connected to the circuit pattern layer. On the target substrate, the supplemental repair element is arbitrary with respect to the micro photoelectric elements.

Abstract: A semiconductor structure includes a first metal gate structure and a second metal gate structure. The first metal gate structure includes a first high-k gate dielectric layer, a first work function metal layer over the first high-k gate dielectric layer, and a first intervening layer between the first high-k gate dielectric layer and the first work function metal layer. The second metal gate structure includes a second high-k gate dielectric layer and a second work function metal layer over the second high-k gate dielectric layer. The first work function metal layer and the second work function metal layer include a same material. A thickness of the first work function metal layer is less than a thickness of the second work function metal layer.

Abstract: A bumped solder pad and methods for adding bumps to a solder pad are provided. A substrate is provided having metal layer formed thereon and a solder pad formed from a portion of the metal layer. A surface treatment is applied to the solder pad. The surface treatment is patterned. The surface treatment is etched to produce at least one bump on the solder pad.

Abstract: A method for forming a semiconductor device includes implanting first ions and second ions into a p-type silicon carbide layer from a first main side to form an implantation layer at the first main side. The implanting is performed by plasma immersion ion implantation in which the p-type silicon carbide layer is immersed in a plasma comprising the first ions and the second ions. The first ions can be ionized aluminum atoms and the second ions are different from the first ions.

Abstract: A film forming method includes: repeatedly performing a source gas adsorption process including supplying a source gas containing a metal element to form a nitride film on a substrate in a chamber and purging a residual gas, and a nitriding process including supplying a nitriding gas onto the substrate and purging a residual gas; and supplying a hydrazine-based compound gas as a part or all of the nitriding gas.

Abstract: A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.

Abstract: An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.

Abstract: The present disclosure illustrates a method for correcting an active matrix substrate. The method includes steps: performing the broken-line inspection process to inspect whether the broken line exists on the first and second gate lines; if one first gate line is inspected to be broken, performing a source line repair-section forming process to cut off the cut portions of the second source lines disposed at two sides of a pixel electrode corresponding to a broken location of the first gate line, to form source line repair sections overlapping with the broken first gate line and the second gate line; performing a gate line repair-section forming process on the second gate line, adjacent to the broken first gate line, to cut off the cut portions of the second gate line to form a gate line repair section overlapping with the second source lines; and performing a connection process.

Abstract: The present disclosure illustrates an active matrix substrate includes pixel electrodes forming the pixels; first gate lines respectively disposed between the pixel electrodes extended in parallel to each other; first source line respectively disposed between the pixel electrodes and extended in a direction crossing the first gate lines; capacitor lines respectively disposed between the first gate lines and extended in nonparallel to from one another; switch devices respectively disposed on the pixel electrodes; second source lines respectively disposed between the pixel electrodes and extended in parallel to the first source lines; second gate lines respectively disposed between the pixel electrode and extended in parallel to the first gate lines. The first gate lines, capacitor lines, first source lines, second gate lines, capacitor lines and second source lines are not in electrical connection with each other.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a base, a seed layer, a compound semiconductor layer, a gate structure, a source structure, a drain structure, and a conductive paste. The seed layer is disposed on the base. The compound semiconductor layer is disposed on the seed layer. The gate structure is disposed on the compound semiconductor layer. The source structure and the drain structure are disposed on both sides of the gate structure. In addition, the conductive paste is disposed between the base and a lead frame, and the conductive paste extends to the side surface of the base.

Abstract: A method for manufacturing a semiconductor device includes forming a first interconnect in a first dielectric layer, and forming a second dielectric layer on the first dielectric layer. In the method, an etch stop layer is formed on the second dielectric layer, and a third dielectric layer is formed on the etch stop layer. The method also includes forming a trench in the third dielectric layer, wherein a bottom surface of the trench includes the etch stop layer. A second interconnect is formed in the trench on the etch stop layer, and a via is formed in the second dielectric layer. The via connects the second interconnect to the first interconnect.

Abstract: An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.

Abstract: A method of manufacturing a semiconductor device includes the following steps. A first patterned photoresist layer is formed on a substrate. A second patterned photoresist layer is formed on the substrate after the first patterned photoresist layer is formed, wherein the first patterned photoresist layer and the second patterned photoresist layer are arranged alternatively. A liner is formed to cover sidewalls of the first patterned photoresist layer and the second patterned photoresist layer. The present invention also provides a semiconductor device, including a plurality of pillars being disposed on a layer, wherein the layer includes first recesses and second recesses, wherein the depths of the first recesses are less than the depths of the second recesses.

Abstract: The present invention relates to a composition comprising; components a. c. and d; and optional component b. wherein, component a. is a metal compound having the structure (I), optional component b., is a polyol additive, having structure (VI), component c. is a high performance polymer additive, and component d. is a solvent. The present invention further relates to using this compositions in methods for manufacturing electronic devices through either the formation of a patterned films of high K material comprised of a metal oxide on a semiconductor substrate, or through the formation of patterned metal oxide comprised layer overlaying a semiconductor substrate which may be used to selectively etch the semiconductor substrate with a fluorine plasma.

Abstract: A semiconductor device includes a substrate, a gate structure over the substrate, gate spacers on opposite sidewalls of the gate structure, an inhibitor residue over gate structure and between the gate spacers, and source/drain structures on opposite sides of the gate structure. The inhibitor residue lines a sidewall of one of the gate spacers.

Abstract: A method of generating a layout diagram includes: generating first and second conductor shapes; generating first, second and third cap shapes correspondingly over the first and second conductor shapes; arranging a corresponding one of the second conductor shapes to be interspersed between each pair of neighboring ones of the first conductor shapes; generating first cut patterns over selected portions of corresponding ones of the first cap shapes; and generating second cut patterns over selected portions of corresponding ones of the second cap shapes. In some circumstances, the first cut patterns are designated as selective for a first etch sensitivity corresponding to the first cap shapes; and the second cut patterns are designated as selective for a second etch sensitivity corresponding to the second cap shapes.

Abstract: Some embodiments include an integrated structure having a conductive region which contains one or more elements from Group 2 of the periodic table. Some embodiments include an integrated structure which has a conductive region over and directly against a base material. The conductive region includes one or more elements from Group 2 of the periodic table, and has a pair of opposing sidewalls along a cross-section. A capping material is over and directly against the conductive region. Protective material is along and directly against the sidewalls of the protective region.

Abstract: Copper electroplating compositions which include an imidazole compound enables the electroplating of copper having uniform morphology on substrates. The composition and methods of enable copper electroplating of photoresist defined features. Such features include pillars, bond pads and line space features.

Abstract: A method includes forming a source/drain region, and in a vacuum chamber or a vacuum cluster system, preforming a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber or a vacuum cluster system without vacuum break.

Abstract: The present invention provides technology that uses current measurements to identify nucleotides and determine a nucleotide sequence in polynucleotides. The present invention calculates a modal value of a tunnel current that arises when a nucleotide or polynucleotide for analysis passes through between electrodes, and then employs the calculated modal value. The present invention accordingly enables direct rapid implementation to identify nucleotides and to determine a nucleotide sequence in a polynucleotide without marking.

Abstract: A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductive substrate, and a first contact plug formed on the semiconductive substrate. The semiconductor structure further includes a dielectric layer encircling the first contact plug. The semiconductor structure further includes a multilayer structure deposited on the dielectric layer and encircling the first contact plug. The dielectric layer produces a tensile stress pulling the first contact plug outward along a width direction. The multilayer structure produces a compressive stress that compensates for the tensile stress caused by the dielectric layer. A method of forming the semiconductor structure is also provided.

Abstract: A semiconductor device comprises a structured metal layer. The structured metal layer lies above a semiconductor substrate. In addition, a thickness of the structured metal layer is more than 100 nm. Furthermore, the semiconductor device comprises a covering layer. The covering layer lies adjacent to at least one part of a front side of the structured metal layer and adjacent to a side wall of the structured metal layer. In addition, the covering layer comprises amorphous silicon carbide.

Abstract: Various methods for detecting moisture in briefs compatible with high volume manufacturing are disclosed. The embodiments herein facilitate protection of the method of adding moisture sensing to a diaper, but could also be used to add sensing to pads and bandages. The primary design intent is optimal moisture detection and low per unit cost. Electrodes within a garment measure electrical properties of the electrodes to determine if the item has contacted moisture. The target moisture is urine, however, other sources and types of moisture can also be sensed. Additional analysis capabilities can be added by selecting particular electrodes or add materials that may react with chemical components of the moisture. Applications of the research Include monitor of incontinence using smart brief (e.g. diaper); monitor perspiration, bleeding, or failure of the protective garment; and monitoring exposure of an item to moisture, including but not limited to inanimate items.

Abstract: Multi-patterning methods are provided for use in fabricating an array of metal lines comprising metal lines with different widths. For example, patterning methods implement spacer-is-dielectric (SID)-based self-aligned double patterning (SADP) methods for fabricating an array of metal lines comprising elongated metal lines with different widths, wherein an “unblock” mask is utilized as part of the process flow to overlap mandrel assigned and non-mandrel assigned features in a given SADP pattern to define regions to unblock a metal fill (remove dielectric material between wires) in a dielectric layer between defined metal lines of an a SADP pattern thus enabling the formation of wide metal lines within any region of a pattern of elongated metal lines formed with a minimum feature width.

Abstract: A method includes receiving a substrate having a substrate feature; forming a first material layer over the substrate and in physical contact with the substrate feature; forming an etch mask over the first material layer; and applying a dynamic-angle (DA) plasma etching process to the first material layer through the etch mask to form a first material feature. Plasma flux of the DA plasma etching process has an angle of incidence with respect to a normal of the first material layer and the angle of incidence changes in a dynamic mode during the DA plasma etching process.

Abstract: A semiconductor device includes a first fin field effect transistor (FinFET) and a contact bar (source/drain (S/D) contact layer). The first FinFET includes a first fin structure extending in a first direction, a first gate structure extending in a second direction crossing the first direction, and a first S/D structure. The contact bar is disposed over the first S/D structure and extends in the second direction crossing the first S/D structure in plan view. The contact bar includes a first portion disposed over the first S/D structure and a second portion. The second portion overlaps no fin structure and no S/D structure. A width of the second portion in the first direction is smaller than a width of the first portion in the first direction in plan view.

Abstract: A structure includes a non-insulator structure, an etch stop layer, a dielectric layer, a conductive feature, and a first diffusion barrier layer. The etch stop layer is over the non-insulator structure. The dielectric layer is over the etch stop layer. The conductive feature is in the dielectric layer. The first diffusion barrier layer wraps around the conductive feature, the first diffusion barrier layer has a base portion between the non-insulator structure and the conductive feature, and the first diffusion barrier layer has a lateral extension from the base portion of the first diffusion barrier layer.

Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

Abstract: A construction of integrated circuitry comprises a structure comprising conductive material having insulative material there-above. The conductive material and the insulative material respectively have opposing sides in a vertical cross-section. A first insulating material is laterally outward of the opposing sides of the conductive material in the vertical cross-section. A second insulating material is laterally outward of the first insulating material in the vertical cross-section. The second insulating material is of different composition from that of the first insulating material. The second insulating material laterally covers a lower portion of the opposing sides of the insulative material in the vertical cross-section. The second insulating material does not laterally cover an upper portion of the opposing sides of the insulative material in the vertical cross-section. A third insulating material is laterally outward of the second insulating material in the vertical cross-section.

Abstract: An aqueous ink for inkjet printing contains silver particles having a particle size of 60 nm or less at a cumulative volume of 90%.

Abstract: According to one embodiment, a magnetic memory device includes a lower region, and a stacked structure provided on the lower region, wherein the stacked structure includes a conductive oxide layer containing boron (B), a first magnetic layer provided between the lower region and the conductive oxide layer, having a variable magnetization direction, and containing iron (Fe) and boron (B), a second magnetic layer provided between the lower region and the first magnetic layer, having a fixed magnetization direction, and containing iron (Fe) and boron (B), and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer.

Abstract: An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer on the first interlayer insulating layer.

Abstract: Provided is a cathode material for a rechargeable magnesium battery, represented by the chemical formula of Ag2SxSe1-x (0?x?1), a highly stable cathode material and a rechargeable magnesium battery including the same. The cathode material for a rechargeable magnesium battery has a higher discharge capacity and higher discharge voltage as compared to a typical commercially available cathode material, Chevrel phase, and shows excellent stability in an electrolyte for a rechargeable magnesium battery including chloride ions. In addition, after evaluating the cycle life of the cathode material, the cathode material shows an excellent discharge capacity per unit weight after 500 charge/discharge cycles, and thus is useful for a cathode material for a rechargeable magnesium battery.

Abstract: A semiconductor package includes a leadframe, having perimeter package leads and a ground voltage lead, a bottom semiconductor die flip-chip mounted to the leadframe, and a top semiconductor die. The bottom semiconductor die has a first frontside active layer with first frontside electrical contacts electrically connected to the leadframe, a first backside portion, and a buried oxide layer situated between the first frontside active layer and the first backside portion. The top semiconductor die is mounted to the first backside portion. The first frontside active layer includes a circuit electrically connected to the first backside portion by a backside electrical connection through the buried oxide layer. The first backside portion of the bottom semiconductor die is electrically connected to the ground voltage lead through a first electrical contact of the first frontside electrical contacts to minimize crosstalk.

Abstract: Disclosed are an on-chip reliability monitor and method. The monitor includes a test circuit with a test device, a reference circuit with a reference device, and a comparator circuit. The monitor periodically switches from operation in a stress mode, to operation in a test mode, and back. During each stress mode, the test device is subjected to stress conditions that emulate the operating conditions of an on-chip functional device while the reference device remains essentially unstressed. During each test mode, the comparator circuit compares a parameter of the test device to the same parameter of the reference device and outputs a status signal based on the difference between the parameters. When the status signal switches values, it is an indicator that the functional device has been subjected to a predetermined number of power-on-hours. Optionally, multiple monitors can be cascaded together to more accurately monitor stress-induced changes over time.

Abstract: A microelectronic assembly including a dielectric region, a plurality of electrically conductive elements, an encapsulant, and a microelectronic element are provided. The encapsulant may have a coefficient of thermal expansion (CTE) no greater than twice a CTE associated with at least one of the dielectric region or the microelectronic element.

Abstract: A stack for a semiconductor device and a method for making the stack are disclosed. The stack comprises a plurality of sacrificial layers in which each sacrificial layer comprises a first lattice parameter; and at least one channel layer comprising a second lattice parameter that is different from the first lattice parameter and in which each channel layer is disposed between and in contact with two sacrificial layers. The stack is formed on an underlayer in which a sacrificial layer is in contact with the underlayer. The underlayer comprises a third lattice parameter that substantially matches the lattice parameter that the plurality of sacrificial layers and the at least one channel layer would have if the plurality of sacrificial layers and the at least one channel layer were was allow to relax coherently.

Abstract: As a barrier metal film, a titanium film is formed by a sputtering process, and a titanium nitride film is formed to cover the titanium film by a CVD process. Next, the back surface of a semiconductor substrate is cleaned by spraying a cleaning chemical liquid toward the back surface thereof, and a portion of the barrier metal film located in the outer peripheral portion is removed by causing the cleaning chemical liquid to wrap around toward the surface side of the outer peripheral portion from the back surface side. Next, a tungsten film is formed to cover the barrier metal film by a CVD process.

Abstract: Bipolar wave current, is used to electrodeposit a nanocrystalline grain size. Polarity Ratio is the ratio of absolute value of time integrated amplitude of negative and positive polarity current. Grain size can be controlled in alloys of two or more components, at least one of which is a metal, and at least one of which is most electro-active, such as nickel and tungsten and molybdenum. Typically, the more electro-active material is preferentially lessened during negative current. Coatings can be layered, each having an average grain size, which can vary layer to layer and also graded through a region. Deposits can be substantially free of either cracks or voids.

Abstract: A method of forming an interconnection structure includes forming a dielectric structure over a non-insulator structure; forming a hole in the dielectric structure to expose the non-insulator structure; forming a first diffusion barrier layer into the hole in the dielectric structure using a first deposition process; forming a second diffusion barrier layer over the first diffusion barrier layer using a second deposition process that is different from the first deposition process; and forming a metal over the second diffusion barrier layer.

Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a channel layer on a substrate; forming a gate dielectric layer on the channel layer; forming a source layer near one side of the gate dielectric layer and a drain layer near another side of the gate dielectric layer; forming a bottom gate on the gate dielectric layer; forming a phase change layer on the bottom gate; and forming a top gate on the phase change layer.

Abstract: A device including a non-polarization material includes a number of layers. A first layer of silicon (100) defines a U-shaped groove having a bottom portion (100) and silicon sidewalls (111) at an angle to the bottom portion (100). A second layer of a patterned dielectric on top of the silicon (100) defines vertical sidewalls of the U-shaped groove. A third layer of a buffer covers the first layer and the second layer. A fourth layer of gallium nitride is deposited on the buffer within the U-shaped groove, the fourth layer including cubic gallium nitride (c-GaN) formed at merged growth fronts of hexagonal gallium nitride (h-GaN) that extend from the silicon sidewalls (111), wherein a deposition thickness (h) of the gallium nitride above the first layer of silicon (100) is such that the c-GaN completely covers the h-GaN between the vertical sidewalls.