Having Liquid And Vapor Etching Steps Patents (Class 438/704)
  • Patent number: 11887866
    Abstract: A supercritical processing apparatus includes an upper vessel including a first fluid hole formed in a center thereof, and a lower vessel including a second fluid hole formed in a center thereof. A space is defined between the upper and lower vessels and configured to allow a substrate to be placed therein. The upper vessel further includes a first guide portion provided at a lower portion thereof to be gradually inclined downward toward a periphery thereof from the first fluid hole.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: January 30, 2024
    Assignee: SEMES CO., LTD.
    Inventors: Jae Seong Lee, Hae Won Choi, Ki Hoon Choi, Anton Koriakin, Chan Young Heo, Do Heon Kim, Ji Soo Jeon
  • Patent number: 11871560
    Abstract: The application provides a method for manufacturing a semiconductor structure and the semiconductor structure, and relates to the technical field of semiconductors. The method for manufacturing the semiconductor structure includes: providing a base; sequentially stacking an initial conductive layer, an initial first dielectric layer, an initial first mask layer, an initial second dielectric layer, an initial second mask layer and a photoresist layer with a pattern on the base; and etching part of the initial second mask layer, part of the initial second dielectric layer and part of the initial first mask layer by taking the photoresist layer as a mask, so as to form a second dielectric layer with a trapezoidal structure which is of a structure with small top and large bottom.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Mingxia Cheng, Yang Chen
  • Patent number: 11508574
    Abstract: A semiconductor manufacturing apparatus according to an embodiment includes: a stage to have a plurality of pins to hold a semiconductor substrate having a first surface on which a film to be etched is formed and a second surface positioned on an opposite side to the first surface; a nozzle to eject a liquid chemical toward the first surface of the semiconductor substrate from above the stage; and an optical measurer to radiate light toward the second surface of the semiconductor substrate from a side of the stage during ejection of the liquid chemical, and to measure a displacement amount of the semiconductor substrate based on a state of reception of light reflected on the second surface.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: November 22, 2022
    Assignee: Kioxia Corporation
    Inventor: Hiroyasu Iimori
  • Patent number: 11424408
    Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: August 23, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Min Chou, Kuo-Chih Lai, Wei-Ming Hsiao, Hui-Ting Lin, Szu-Yao Yu, Nien-Ting Ho, Hsin-Fu Huang, Chin-Fu Lin
  • Patent number: 11410853
    Abstract: The substrate processing method includes alternately performing a plurality of times of a metal oxide layer forming process in which an oxidation fluid is supplied to a surface of the substrate and a metal oxide layer composed of a one-atom layer or a several-atom layer is formed on a surface layer of the metal layer; and a metal oxide layer removal process in which an etching solution is supplied to the surface of the substrate and the metal oxide layer is removed from the surface of the substrate. A final dissolved oxygen concentration which is a dissolved oxygen concentration in the etching solution supplied to the surface of the substrate in a final metal oxide layer removal process is lower than an initial dissolved oxygen concentration which is a dissolved oxygen concentration in the etching solution supplied to the substrate in an initial metal oxide layer removal process.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: August 9, 2022
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Ayumi Higuchi, Yuya Akanishi
  • Patent number: 11367776
    Abstract: A semiconductor device includes a source/drain pattern disposed on a substrate and a source/drain contact connected to the source/drain pattern. The source/drain contact includes a lower contact structure extending in a first direction and an upper contact structure protruding from the lower contact structure. The upper contact structure includes a first sidewall and a second sidewall facing away from each other in the first direction. The first sidewall of the upper contact structure includes a plurality of first sub-sidewalls, and each of the first sub-sidewalls includes a concave surface.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: June 21, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang-Young Lee, Jin Wook Lee
  • Patent number: 11205587
    Abstract: Embodiments of the invention are directed to an interconnect stack including a first dielectric layer, a first trench formed in the first dielectric layer, and a first liner deposited in the first trench, wherein the first liner defines a second trench. A first conductive material is in the second trench and deposited over the first dielectric layer and the first conductive material. A third trench extends through the second dielectric layer and is over the first conductive material. A bottom surface of the third trench includes at least a portion of the top surface of the first conductive material. A second liner is in the third trench, on sidewalls of the third trench, and also on the portion of the top surface of the first conductive material. The second liner functions as a cap region configured to counter electro-migration or surface migration of the first conductive material.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: December 21, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Su Chen Fan, Hemanth Jagannathan, Raghuveer R. Patlolla, Cornelius Brown Peethala
  • Patent number: 11145518
    Abstract: A selectivity can be improved in a desirable manner when etching a processing target object containing silicon carbide. An etching method of processing the processing target object, having a first region containing silicon carbide and a second region containing silicon nitride and in contact with the first region, includes etching the first region to remove the first region atomic layer by atomic layer by repeating a sequence comprising: generating plasma from a first gas containing nitrogen to form a mixed layer containing ions contained in the plasma generated from the first gas in an atomic layer of an exposed surface of the first region; and generating plasma from a second gas containing fluorine to remove the mixed layer by radicals contained in the plasma generated from the second gas.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: October 12, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Sho Kumakura, Masahiro Tabata
  • Patent number: 11131919
    Abstract: A method of removing layers of an extreme ultraviolet (EUV) pattern stack is provided. The method includes forming one or more resist templates on an upper hardmask layer. The method further includes exposing portions of the surface of the upper hardmask layer to a dry etch process to produce modified and activated surfaces. The method further includes etching the modified and activated surfaces to expose an underlying organic planarization layer.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: September 28, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yongan Xu, Zhenxing Bi, Yann Mignot, Nelson Felix, Ekmini A. De Silva
  • Patent number: 11107691
    Abstract: A method of manufacturing a semiconductor device is provided, and the method may include: preparing a semiconductor substrate constituted of a group III nitride semiconductor, a main surface of the semiconductor substrate being a c-plane; forming a grove on the main surface by dry dry-etching the main surface; and wet-etching an inner surface of the groove using an etchant to expose the c-plane of the semiconductor substrate in a wet-etched region, the etching having an etching rate to the c-plane of the semiconductor substrate that is lower than the etching rate to a plane other than the c-plane of the semiconductor substrate.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: August 31, 2021
    Assignee: DENSO CORPORATION
    Inventors: Toru Ikeda, Tomohiko Mori, Narumasa Soejima, Hideya Yamadera
  • Patent number: 11022887
    Abstract: An EUV lithographic structure and methods according to embodiments of the invention includes an EUV photosensitive resist layer disposed directly on an oxide hardmask layer, wherein the oxide hardmask layer is doped with dopant ions to form a doped oxide hardmask layer so as to improve adhesion between the EUV lithographic structure and the oxide hardmask. The EUV lithographic structure is free of a separate adhesion layer.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: June 1, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yongan Xu, Jing Guo, Ekmini A. De Silva, Oleg Gluschenkov
  • Patent number: 10964819
    Abstract: A fin field effect transistor (FinFET) device structure and method for forming the FinFET device structure are provided. The FinFET structure includes a substrate, and the substrate includes a core region and an I/O region. The FinFET structure includes a first etched fin structure formed in the core region, and a second etched fin structure formed in the I/O region. The FinFET structure further includes a plurality of gate stack structures formed over the first etched fin structure and the second etched fin structure, and a width of the first etched fin structure is smaller than a width of the second etched fin structure.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhe-Hao Zhang, Tung-Wen Cheng, Che-Cheng Chang, Yung-Jung Chang
  • Patent number: 10923360
    Abstract: In a method of etching a film having a side wall surface and a bottom surface that defines an opening, a precursor layer is formed on the film and the film is etched by a chemical species generated from a processing gas. A protection region is formed from the precursor layer by the chemical species generated from a plasma or the processing or a separate chemical species from the plasma or processing gas while the film is being etched.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: February 16, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Takayuki Katsunuma
  • Patent number: 10784117
    Abstract: A defect relieving method for a floating gate is disclosed, which includes: providing a front-end structure, including an active region, a gate oxide layer on the active region, a mask layer on the gate oxide layer, a plurality of trenches penetrating through the mask layer, the gate oxide layer, and at least part of the active region, and a filler that is filled in the trenches; performing a first etching process to remove a first thickness of the mask layer between adjacent ones of the trenches; performing a second etching process to remove a remaining thickness of the mask layer between the adjacent trenches, and reducing a width of a portion of the filler that exceeds a top surface of the gate oxide layer, thereby an opening is formed; and filling the opening with a floating gate. The method increases the diameter of the opening, thus avoiding occurrence of voids.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: September 22, 2020
    Assignee: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
    Inventors: Shengnan Huang, Qingwei Luo, Yun Li
  • Patent number: 10663624
    Abstract: A method for creating a nanostructure in a transparent substrate, including a) applying a first structure carrier layer having a defined thickness onto at least one surface of the substrate; b) forming a nanostructure in the first structure carrier layer; and c) oxidizing the first structure carrier layer.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: May 26, 2020
    Assignee: Robert Bosch GmbH
    Inventor: Stefan Pinter
  • Patent number: 10546956
    Abstract: A fin field effect transistor (FinFET) device structure and method for forming the FinFET device structure are provided. The FinFET structure includes a substrate, and the substrate includes a core region and an I/O region. The FinFET structure includes a first etched fin structure formed in the core region, and a second etched fin structure formed in the I/O region. The FinFET structure further includes a plurality of gate stack structures formed over the first etched fin structure and the second etched fin structure, and a width of the first etched fin structure is smaller than a width of the second etched fin structure.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhe-Hao Zhang, Tung-Wen Cheng, Che-Cheng Chang, Yung-Jung Chang
  • Patent number: 10332762
    Abstract: A chemical liquid supply apparatus includes a nozzle unit including a nozzle arm and an injection nozzle mounted in an end of the nozzle arm, a chemical liquid supply unit including a first chemical liquid tank accommodating a first chemical liquid and a second chemical liquid tank accommodating a second chemical liquid, and supplying the first chemical liquid and the second chemical liquid to the nozzle unit, and a mixer unit provided in the nozzle unit and discharging a process fluid by mixing the first chemical liquid and the second chemical liquid, wherein the mixer unit includes an in-line mixer mixing the first chemical liquid and the second chemical liquid that are continually injected from the chemical liquid supply unit, and a mixer pipe extending from the in-line mixer to the injection nozzle.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: June 25, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-hoo Kim, Il-sang Lee, In-gi Kim, Kyoung-hwan Kim, Hyo-san Lee, Sang-won Bae, Tae-hong Kim, Yong-jun Choi
  • Patent number: 10217840
    Abstract: Replacement metal gate structures with improved chamfered workfunction metal and self-aligned contact and methods of manufacture are provided. The method includes forming a replacement metal gate structure in a dielectric material. The replacement metal gate structure is formed with a lower spacer and an upper spacer above the lower spacer. The upper spacer having material is different than material of the lower spacer. The method further includes forming a self-aligned contact adjacent to the replacement metal gate structure by patterning an opening within the dielectric material and filling the opening with contact material. The upper spacer prevents shorting with the contact material.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10211056
    Abstract: A resist layer is applied to a metal film disposed on a semiconductor substrate, using a positive photoresist having photosensitivity to at least one wavelength. The resist layer is exposed to light including a region of the one wavelength. The exposed resist layer is developed. After the step of developing the resist layer, the metal film is subjected to wet etching with the resist layer used as a mask, in an etching apparatus. The etching apparatus is placed in an environment irradiated with a lighting apparatus that emits light with a wavelength equal to or shorter than the one wavelength cut off.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: February 19, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Nobuaki Yamanaka, Daisuke Chikamori, Yoshio Muto
  • Patent number: 10186426
    Abstract: Methods are provided for integrating atomic layer etch and atomic layer deposition by performing both processes in the same chamber or reactor. Methods involve sequentially alternating between atomic layer etch and atomic layer deposition processes to prevent feature degradation during etch, improve selectivity, and encapsulate sensitive layers of a semiconductor substrate.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: January 22, 2019
    Assignee: Lam Research Corporation
    Inventors: Keren Jacobs Kanarik, Jeffrey Marks, Harmeet Singh, Samantha Tan, Alexander Kabansky, Wenbing Yang, Taeseung Kim, Dennis M. Hausmann, Thorsten Lill
  • Patent number: 9953840
    Abstract: A substrate processing method according to the present disclosure includes: a liquid processing process of supplying a processing liquid to a substrate having a surface on which a pattern having a plurality of convex portions is formed; a drying process of removing the processing liquid existing on the surface of the substrate dry the substrate, and a separating process of separating a sticking portion between adjacent ones of the convex portions after the drying process.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: April 24, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Hiroshi Marumoto, Hisashi Kawano, Hiromi Kiyose, Mitsunori Nakamori, Kazuyuki Mitsuoka
  • Patent number: 9818643
    Abstract: The present disclosure provides an interconnect structure, including a low k dielectric layer with an air gap region and a non-air gap region. A first conductive line is positioned in the air gap region, and a second conductive line is positioned in the non-air gap region of the low k dielectric layer. A height of the first conductive line is different from a height of the second conductive line. The present disclosure also provides a method for manufacturing a semiconductor interconnect structure, including forming a photoresist layer over a hard mask layer with openings exposing a low k dielectric layer; treating a region of the low k dielectric layer to increase hydrophilicity through the openings of the hard mask layer, and removing the treated low k dielectric region to form an air gap in the air gap region.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: November 14, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chih-Yuan Ting
  • Patent number: 9708182
    Abstract: A method for producing at least one cavity within a semiconductor substrate includes dry etching the semiconductor substrate from a surface of the semiconductor substrate at at least one intended cavity location in order to obtain at least one provisional cavity. The method includes depositing a protective material with regard to a subsequent wet-etching process at the surface of the semiconductor substrate and at cavity surfaces of the at least one provisional cavity. Furthermore, the method includes removing the protective material at least at a section of a bottom of the at least one provisional cavity in order to expose the semiconductor substrate. This is followed by electrochemically etching the semiconductor substrate at the exposed section of the bottom of the at least one provisional cavity. A method for producing a micromechanical sensor system in which this type of cavity formation is used and a corresponding MEMS are also disclosed.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: July 18, 2017
    Assignee: Infineon Technologies AG
    Inventors: Andreas Behrendt, Kai-Alexander Schreiber, Sokratis Sgouridis, Martin Zgaga, Bernhard Winkler
  • Patent number: 9679935
    Abstract: An image sensor may include a device isolation structure defining a plurality of pixel regions in a substrate and a photoelectric conversion element formed in each of the pixel regions. The device isolation structure may include an insulating gapfill layer extending from an upper portion to a lower portion of the device isolation structure, a spacer provided at the upper portion of the device isolation structure and interposed between the insulating gapfill layer and the substrate, and a lower impurity region provided at the lower portion of the device isolation structure and interposed between the insulating gapfill layer and the substrate.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: June 13, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changyong Um, Byungjun Park, Jungchak Ahn
  • Patent number: 9570396
    Abstract: A semiconductor device includes a first metal layer provided above a semiconductor substrate, an interlayer insulating film provided above the first metal layer, a second metal layer that is provided in an opening formed in the interlayer insulating film and is in contact with an underlying layer, the second metal layer being connected to the first metal layer, and a first barrier layer that is provided between the second metal layer and the interlayer insulating film and has a different main composition from that of the underlying layer.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: February 14, 2017
    Assignee: MONTEREY RESEARCH, LLC
    Inventor: Takayuki Enda
  • Patent number: 9299577
    Abstract: Methods for eliminating early exposure of a conductive layer in a dual damascene structure and for etching a dielectric barrier layer in the dual damascene structure are provided. In one embodiment, a method for etching a dielectric barrier layer disposed on a substrate includes patterning a substrate having a dielectric bulk insulating layer disposed on a dielectric barrier layer using a hardmask layer disposed on the dielectric bulk insulating layer as an etching mask, exposing a portion of the dielectric barrier layer after removing the dielectric bulk insulating layer uncovered by the dielectric bulk insulating layer, removing the hardmask layer from the substrate, and subsequently etching the dielectric barrier layer exposed by the dielectric bulk insulating layer.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: March 29, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: He Ren, Chia-Ling Kao, Sean Kang, Jeremiah T P Pender, Srinivas D. Nemani, Mehul B. Naik
  • Patent number: 9276001
    Abstract: A semiconductor device comprises a substrate, a word line, an insulation material, and an etch stop material. The substrate comprises a pillar that may comprise an active area. The word line is formed in the substrate. The insulation material is formed on the word line. The etch stop material is formed on the insulating material and around the pillar.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: March 1, 2016
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Guangjun Yang, Russell Benson
  • Publication number: 20150140827
    Abstract: Implementations described herein generally relate to semiconductor manufacturing and more particularly to methods for etching a low-k dielectric barrier layer disposed on a substrate using a non-carbon based approach. In one implementation, a method for etching a barrier low-k layer is provided. The method comprises (a) exposing a surface of the low-k barrier layer to a treatment gas mixture to modify at least a portion of the low-k barrier layer and (b) chemically etching the modified portion of the low-k barrier layer by exposing the modified portion to a chemical etching gas mixture, wherein the chemical etching gas mixture includes at least an ammonium gas and a nitrogen trifluoride gas or at least a hydrogen gas and a nitrogen trifluoride gas.
    Type: Application
    Filed: November 14, 2014
    Publication date: May 21, 2015
    Inventors: Chia-Ling KAO, Sean KANG, Jeremiah T. PENDER, Srinivas D. NEMANI, He REN, Mehul NAIK
  • Publication number: 20150132953
    Abstract: Two-step process sequences uniformly etch both tungsten-based and titanium-based structures on a substrate. A sequence of wet etches using peroxide and heated nitric acid uniformly recesses a metal stack that includes W, TiN, and TiAl. W, TiN and TiC are uniformly recessed by a peroxide etch at ˜25 C followed by an acid solution with a very small amount of added peroxide at ˜60 C. TiC is etched without etching trench oxides or other metals in a work-function metal stack by either (1) highly-dilute of ultra-dilute HF at 25-35 C, (2) dilute HCl at 25-60 C, (3) dilute NH4OH at 25-60 C, or (4) solution (2) or (3) with small amounts of peroxide. Other metals in the stack may then be plasma-etched without being blocked by TiC residues.
    Type: Application
    Filed: November 13, 2013
    Publication date: May 14, 2015
    Applicant: Intermolecular Inc.
    Inventors: Gregory Nowling, John Foster
  • Patent number: 9012304
    Abstract: In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: April 21, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gordon M. Grivna, John M. Parsey, Jr.
  • Patent number: 9005462
    Abstract: In a method for manufacturing a silicon carbide semiconductor device, a conductive layer is formed on a silicon carbide layer. The silicon carbide layer and the conductive layer react with each other thus forming an alloy layer formed of a reaction layer in contact with the silicon carbide layer and a silicide layer on the reaction layer. A carbon component is removed from the silicide layer. A portion of the silicide layer is removed using an acid thus exposing at least a portion of the reaction layer. An electrode layer is formed on an upper side of the exposed reaction layer.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: April 14, 2015
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventor: Jun-ichi Ohno
  • Publication number: 20150099363
    Abstract: A semiconductor is fabricated on a silicon (Si) substrate. The semiconductor is III-nitride based. The Si substrate is partially isolated. Etching is directly processed from top on a chip for solving wire-width problem. The Si substrate does not need to be made thin. The chip can be large scaled and be prevented from bowing. Thus, the present invention simplifies producing procedure and reduces production cost. Besides, for a large-scaled chip, the breakdown voltage is enhanced; and, without making the Si substrate thin, the on-state current is remained the same and the heat problem is weakened.
    Type: Application
    Filed: December 2, 2013
    Publication date: April 9, 2015
    Applicant: National Tsing Hua University
    Inventors: Yu-Syuan Lin, Shuo-Hung Hsu, Yi-Wei Lien
  • Patent number: 8999849
    Abstract: A semiconductor is fabricated on a silicon (Si) substrate. The semiconductor is III-nitride based. The Si substrate is partially isolated. Etching is directly processed from top on a chip for solving wire-width problem. The Si substrate does not need to be made thin. The chip can be large scaled and be prevented from bowing. Thus, the present invention simplifies producing procedure and reduces production cost. Besides, for a large-scaled chip, the breakdown voltage is enhanced; and, without making the Si substrate thin, the on-state current is remained the same and the heat problem is weakened.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: April 7, 2015
    Assignee: National Tsing Hua University
    Inventors: Yu-Syuan Lin, Shuo-Hung Hsu, Yi-Wei Lien
  • Patent number: 8993450
    Abstract: Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface; (d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and (e) providing a conductive structure for sealing the via structure. Also provided are sealed via structures, methods of detecting leakage in a sealed device package, sealed device packages, device packages having cooling structures, and methods of bonding a first component to a second component.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: March 31, 2015
    Assignee: Nuvotronics, LLC
    Inventor: David W Sherrer
  • Patent number: 8993357
    Abstract: A method for manufacturing a liquid discharge includes a process of forming a plurality of blind holes extending from a first surface of the silicon substrate toward a second surface which is a surface opposite to the first surface in the silicon substrate and a process of subjecting the silicon substrate in which the plurality of blind holes are formed to anisotropic etching from the first surface to form a liquid supply port in the silicon substrate, in which, in the process of forming the liquid supply port, the silicon in a region sandwiched by the plurality of blind holes when the silicon substrate is seen from the second surface side is left without being removed by the anisotropic etching to use the left silicon as a beam.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: March 31, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Keisuke Kishimoto, Taichi Yonemoto
  • Patent number: 8993426
    Abstract: The invention provides a semiconductor device with a junction termination extension structure on a mesa and a method of fabricating the same. The device comprises: a type-I semiconductor substrate having a first surface and a second surface; a type-I epitaxial layer disposed on the first surface; at least one depression disposed on the type-I epitaxial layer; a mesa-type junction termination extension structure surrounding the at least one depression wherein the mesa-type junction termination extension structure is of type-II; and at least one semiconductor component formed one the depression.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: March 31, 2015
    Inventor: Chii-Wen Jiang
  • Publication number: 20150087156
    Abstract: A method of etching a semiconductor substrate, having the steps of: preparing an etching liquid by mixing a first liquid with a second liquid to be in the range of pH from 8.5 to 14, the first liquid containing a basic compound, the second liquid containing an oxidizing agent; and then applying the etching liquid to a semiconductor substrate on a timely basis for etching a Ti-containing layer in or on the semiconductor substrate.
    Type: Application
    Filed: December 3, 2014
    Publication date: March 26, 2015
    Applicant: FUJIFILM Corporation
    Inventors: Tetsuya KAMIMURA, Tadashi INABA, Naotsugu MURO, Yoshinori NISHIWAKI
  • Publication number: 20150079795
    Abstract: A plurality of substrate processing devices are disposed in a separated manner within a shared ambient environment. A conveyance device is disposed within the shared ambient environment and is defined to move a substrate through and between each of the substrate processing devices in a continuous manner. Some substrate processing devices are defined to perform dry substrate processing operations in which an energized reactive environment is created in exposure to the substrate in an absence of liquid material. Some substrate processing devices are defined to perform wet substrate processing operations in which at least one material in a liquid state is applied to the substrate. In one embodiment, a complementary pair of dry and wet substrate processing devices are disposed in the shared ambient environment in a sequential manner relative to movement of the substrate by the conveyance device.
    Type: Application
    Filed: November 19, 2014
    Publication date: March 19, 2015
    Inventors: David J. Hemker, Lubab L. Sheet, Jeffrey Marks
  • Patent number: 8969203
    Abstract: There is described a method for creating a thermally-isolated microstructure on a slab of mono-crystalline silicon which uses a hybrid dry-then-wet etch technique that when controlled, can produce microstructures without any silicon adhering underneath, microstructures having small masses of silicon adhering underneath, and microstructures that are still attached to the slab of mono-crystalline silicon via a waisted silicon body. When creating the microstructures with a waisted silicon body, the thermal isolation of the microstructure can be designed by controlling the depth of the etching and the size of the waist.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: March 3, 2015
    Assignee: Sensortechnics GmbH
    Inventors: Leslie M. Landsberger, Oleg Grudin, Jens Urban, Uwe Schwarz
  • Patent number: 8962452
    Abstract: In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: February 24, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Gordon M. Grivna
  • Patent number: 8962403
    Abstract: The present invention discloses a manufacturing method for a switch and an array substrate. The method comprises: firstly, forming sequentially a first metal layer, an insulating layer, a semiconductor layer, an ohmic contact layer, a second metal layer, a third metal layer and a photoresist layer on a base substrate; after patterning the photoresist layer, etching the third metal layer and the second metal layer to form the input electrode and the output electrode of the switch; using a stripper comprising at least 30% by weight of amine in order to remove the photoresist layer and the residual second metal layer; and finally, etching the ohmic contact layer. Through the above steps, the present invention can avoid the electrical abnormality of the switch and increase process yield of the array substrate.
    Type: Grant
    Filed: November 23, 2012
    Date of Patent: February 24, 2015
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventors: Yu-Lien Chou, Po-Lin Chen
  • Patent number: 8912073
    Abstract: A method of manufacturing a semiconductor device is disclosed, which can completely remove hard mask residues left along boundaries between a high-voltage device region and STI structures after a dry etch process, by partially reducing a thickness of each of the exposed portion of the respective STI structures adjacent to the high-voltage device region so as to sufficiently expose the residues. As a result, after a portion of an underlying pad oxide corresponding to the high-voltage device region is removed in a subsequent process, the exposed surface of the substrate is uniform with a smooth and clear border. Therefore, no sharp corners will emerge at a border of a gate oxide subsequently grown on the exposed surface of the substrate, and the gate oxide is thus morphologically improved, thereby resulting in an improvement of the reliability of the high-voltage semiconductor device being fabricated.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: December 16, 2014
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Xu Ma, Wei Zhou, Yamin Cao
  • Publication number: 20140357055
    Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.
    Type: Application
    Filed: May 28, 2013
    Publication date: December 4, 2014
    Applicant: Infineon Technologies AG
    Inventors: Anja Gissibl, Hermann Wendt, Thomas Fischer, Bernhard Weidgans, Gudrun Stranzl, Tobias Schmidt, Dietrich Bonart
  • Patent number: 8894868
    Abstract: A method of forming an aperture (e.g., a through via, a blind via, a trench, an alignment feature, etc.) within a substrate includes irradiating a substrate with a laser beam to form a laser-machined feature having a sidewall. The laser-machined feature is then processed to change at least one characteristic (e.g., the sidewall surface roughness, diameter, taper, aspect ratio, cross-sectional profile, etc.) of the laser-machined feature. The laser-machined feature can be processed to form the aperture by performing an isotropic wet-etch process employing an etchant solution containing HNO3, HF and, optionally acetic acid.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: November 25, 2014
    Assignee: Electro Scientific Industries, Inc.
    Inventors: Andy Hooper, Daragh Finn, Tim Webb, Lynn Sheehan, Kenneth Pettigrew, Yu Chong Tai
  • Patent number: 8889562
    Abstract: Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Ying Zhang
  • Patent number: 8883648
    Abstract: A manufacturing method of a semiconductor structure is disclosed. The manufacturing method includes the following steps: providing an underlying layer; forming a tri-layered photoresist on the underlying layer, which comprises forming a bottom photoresist layer on the underlying layer, forming a silicon-containing material layer on the bottom photoresist layer, and forming a patterned photoresist layer on the silicon-containing material layer; performing an atomic layer deposition (ALD) process for forming a thin layer on the tri-layered photoresist; and performing an etching process for forming a via hole, which comprises etching the silicon-containing material layer according to the thin layer on the tri-layered photoresist.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: November 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Da Hsieh, Yu-Tsung Lai, Hsuan-Hsu Chen
  • Publication number: 20140322918
    Abstract: As discussed herein, there is presented an apparatus comprising micro-posts. The apparatus includes a substrate having a planar surface, a plurality of micro-posts located on the planar surface, wherein each micro-post has a base portion on the planar surface and a post portion located on a top surface of the corresponding base portion, and wherein side surfaces of the base portions intersect the planar surface at oblique angles.
    Type: Application
    Filed: July 8, 2014
    Publication date: October 30, 2014
    Inventors: Cristian A. Bolle, Flavio Pardo
  • Publication number: 20140322879
    Abstract: A method of forming a ?-shaped trench is disclosed. The method includes: providing a silicon substrate; and sequentially performing a plasma etching process and a wet etching process on the silicon substrate to form a ?-shaped trench therein. The plasma etching process includes: horizontally etching the silicon substrate using a first plasma etching gas including a nitrogen-containing fluoride; and vertically etching the silicon substrate using a second plasma etching gas including a polymer gas. A method of forming a semiconductor device is also disclosed.
    Type: Application
    Filed: November 21, 2013
    Publication date: October 30, 2014
    Applicant: Shanghai Huali Microelectronics Corproation
    Inventors: Quanbo LI, Fang LI, Yu ZHANG, Jingxun FANG, Shu Koon PANG
  • Patent number: 8871596
    Abstract: A method of forming different structures of a semiconductor device using a single mask and a hybrid photoresist. The method includes: applying a first photoresist layer on a semiconductor substrate; patterning the first photoresist layer using a photomask to form a first patterned photoresist layer; using the first patterned photoresist layer to form a first structure of a semiconductor device; removing the first patterned photoresist layer; applying a second photoresist layer on the semiconductor substrate; patterning the second photoresist layer using the photomask to form a second patterned photoresist layer; using the second patterned photoresist layer to form a second structure of a semiconductor device; removing the second patterned photoresist layer; and wherein either the first or the second photoresist layer is a hybrid photoresist layer comprising a hybrid photoresist.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kuang-Jung Chen, Kangguo Cheng, Bruce B. Doris, Steven J. Holmes, Sen Liu
  • Publication number: 20140315335
    Abstract: A method of processing a substrate includes forming holes in bottom portions of a plurality of recesses formed in a substrate to be arranged in an array direction at a predetermined pitch by performing reactive ion etching on the bottom portions of the plurality of recesses. The forming holes in the bottom portions of the plurality of recesses is a process of preparing a substrate in which a dummy recess serving as a dummy is formed on at least one side of the array direction, in which the plurality of recesses that include the bottom portions in which the holes are formed are arranged, such that a recess is formed on both sides of a recess so that the plurality of recesses are formed at the predetermined pitch in the array direction and performing reactive ion etching on the bottom portions of the plurality of recesses of the prepared substrate.
    Type: Application
    Filed: April 18, 2014
    Publication date: October 23, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Masataka Kato