Abstract: A method for manufacturing a tunnel junction layer using organic vapor phase deposition, the method including: a first process that supplies a first material gas containing a group III element, a second material gas containing a group V element, and a third material gas containing a dopant of a first conductivity type, onto a compound semiconductor layer on which the tunnel junction layer is to be laminated; a second process that stops supplying the first material gas, the second material gas and the third material gas, and supplies a fourth material gas containing a dopant of a second conductivity type opposite to the first conductivity type; and a third process that continues to supply the fourth material gas, and further supplies a fifth material gas containing a group III element and a sixth material gas containing a group V element.

Abstract: Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods. A method for making an SSL device substrate in accordance with one embodiment of the disclosure includes forming multiple crystals carried by a support member, with the crystals having an orientation selected to facilitate formation of gallium nitride. The method can further include forming a volume of gallium nitride carried by the crystals, with the selected orientation of the crystals at least partially controlling a crystal orientation of the gallium nitride, and without bonding the gallium nitride, as a unit, to the support member. In other embodiments, the number of crystals can be increased by a process that includes annealing a region in which the crystals are present, etching the region to remove crystals having an orientation other than the selected orientation, and/or growing the crystals having the selected orientation.

Abstract: In a process of manufacturing a transistor including an oxide semiconductor layer, an amorphous oxide semiconductor layer which includes a region containing excess oxygen as compared to a stoichiometric composition ratio of an oxide semiconductor in a crystalline state is formed over a silicon oxide film, an aluminum oxide film is formed over the amorphous oxide semiconductor layer, and then heat treatment is performed so that at least part of the amorphous oxide semiconductor layer is crystallized and an oxide semiconductor layer which includes a crystal having a c-axis substantially perpendicular to a surface of the oxide semiconductor layer is formed.

Abstract: A process for treating a semiconductor-on-insulator structure that has, in succession, a support substrate, a layer of an oxide or oxynitride of a semiconductor material, and a thin semiconductor layer of the semiconductor material. The process includes providing, on the surface of the thin layer, a mask defining exposed regions of the thin layer; providing a layer of nitride or oxynitride of the semiconductor material on the exposed regions of the thin layer; and applying a heat treatment causing at least some of the oxygen in the oxide or oxynitride layer to diffuse through the exposed regions. The nitride or oxynitride layer is provided at a thickness sufficient to provide a ratio of the rate of oxygen diffusion though the exposed regions to that through the regions covered with the mask that is greater than 2.

Abstract: Embodiments of the disclosure generally provide methods of forming a silicon containing layers in TFT devices. The silicon can be used to form the active channel in a LTPS TFT or be utilized as an element in a gate dielectric layer, a passivation layer or even an etch stop layer. The silicon containing layer is deposited by a vapor deposition process whereby an inert gas, such as argon, is introduced along with the silicon precursor. The inert gas functions to drive out weak, dangling silicon-hydrogen bonds or silicon-silicon bonds so that strong silicon-silicon or silicon-oxygen bonds remain to form a substantially hydrogen free silicon containing layer.

Abstract: A method for manufacturing a semiconductor device includes the steps of forming a P-type region on a surface of a semiconductor substrate, forming at least one Al electrode on the P-type region, forming an interlayer film in contact with the at least one Al electrode, the interlayer film being of a material which is less reactive with Si than is Al, and forming a semi-insulating film on the interlayer film, the semi-insulating film containing Si.

Abstract: A method for forming a polysilicon layer includes forming an amorphous silicon layer over a substrate, performing a first thermal treatment of the amorphous silicon layer by performing an implantation with a gas that includes silicon (Si), and performing a second thermal treatment on the thermally treated layer at a temperature higher than a temperature of the first thermal treatment.

Abstract: It is an object to provide a homogeneous semiconductor film in which variation in the size of crystal grains is reduced. Alternatively, it is an object to provide a homogeneous semiconductor film and to achieve cost reduction. By introducing a glass substrate over which an amorphous semiconductor film is formed into a treatment atmosphere set at more than or equal to a temperature that is needed for crystallization, rapid heating due to heat conduction from the treatment atmosphere is performed so that the amorphous semiconductor film is crystallized. More specifically, for example, after the temperature of the treatment atmosphere is increased in advance to a temperature that is needed for crystallization, the substrate over which the semiconductor film is formed is put into the treatment atmosphere.

Abstract: A manufacturing method of a semiconductor device is provided, comprising: loading a substrate into a processing chamber; forming a first film on the substrate by supplying silicon atom-containing gas, boron atom-containing gas, and germanium atom-containing gas into the processing chamber; forming a second film on the first film by supplying the silicon atom-containing gas and the boron atom-containing gas into the processing chamber; and unloading the substrate from the processing chamber.

Abstract: A method of fabricating an isolation structure and the structure thereof is provided. The method is compatible with the embedded memory process and provides the isolation structure with a poly cap thereon to protect the top corners of the isolation structure, without using an extra photomask.

Abstract: The invention relates to the fabrication of electronic circuits on a thinned semiconductor substrate. To produce a connection pad on the back side of the thinned substrate, the procedure is as follows: an integrated circuit is produced on an unthinned substrate, in which a portion of a polycrystalline silicon layer (18) dedicated for the connection of the pad is provided. The circuit is transferred onto a transfer substrate (30) and then its back side is thinned. A via is opened in the thinned semiconductor layer (12) in order to gain access to the polycrystalline silicon; aluminum (80) is deposited and this layer is etched so as to define a pad which is in contact with the internal interconnects of the integrated circuit by way of the polycrystalline silicon.

Abstract: A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. The methods entail either treating the backside with a wet etch, or alternatively, applying a protective film layer thereon prior to forming an electronic package incorporating the chip or wafer.

Abstract: The invention relates to a method for simultaneous recrystallization and doping of semiconductor layers, in particular for the production of crystalline silicon thin layer solar cells. In this method, in a first step a substrate base layer 1 is produced, in a step subsequent thereto, on the latter an intermediate layer system 2 which has at least one doped partial layer is deposited, in a step subsequent thereto, an absorber layer 3 which is undoped or likewise doped is deposited on the intermediate layer system 2, and in a recrystallization step, the absorber layer 3 is heated, melted, cooled and tempered. In an advantageous method modification, instead of an undoped capping layer, a capping layer system 4 which has at least one partial layer can also be applied on the absorber layer 3.

Abstract: Disclosed is a light emitting device having a plurality of light emitting cells. The light emitting device comprises a thermally conductive substrate, such as a SiC substrate, having a thermal conductivity higher than that of a sapphire substrate. The plurality of light emitting cells are connected in series on the thermally conductive substrate. Meanwhile, a semi-insulating buffer layer is interposed between the thermally conductive substrate and the light emitting cells. For example, the semi-insulating buffer layer may be formed of AlN or semi-insulating GaN. Since the thermally conductive substrate having a thermal conductivity higher than that of a sapphire substrate is employed, heat-dissipating performance can be enhanced as compared with a conventional sapphire substrate, thereby increasing the maximum light output of a light emitting device that is driven under a high voltage AC power source.

Abstract: After cleaning the front and back sides of a silicon wafer with a liquid SC-1 and liquid SC-2, the front and back sides of the silicon wafer are cleaned with an HF solution to be water-repellent surfaces. Following that, an epitaxial layer of silicon is formed on the front side. Consequently, there can be reduced stacking faults after formation of the epitaxial layer and occurrence of cloud on the back side. Alternatively, the front and back sides of a silicon wafer are cleaned with the liquid SC-1 and liquid SC-2, and then the back side of the silicon wafer is cleaned with an HF solution to be a water-repellent surface while the front side is cleaned with purified water to be a hydrophilic surf ace. Following that, an epitaxial layer of silicon is formed on the front side. Consequently, there can be reduced mounds on the front side and occurrence of cloud on the back side.

Abstract: A method for manufacturing an alignment layer is provided, which includes the following steps. First, a substrate is provided. Next, an auxiliary layer is formed on the substrate. Then, an alignment solution is sprayed on the auxiliary layer through an inkjet printing process. The alignment solution includes an alignment material and a first solvent, and the auxiliary layer has the same polarity as the first solvent. Then, by performing a curing process, the alignment solution is cured to form an alignment layer. As mentioned above, the method for manufacturing an alignment layer may be applied to manufacture an alignment layer with preferred smoothness.

Abstract: When high purity silicon is produced through a gas-phase reaction between silicon tetra-chloride and zinc in a reaction furnace, the produce silicon is obtained as block or molten state. after the reaction in which the silicon is not in contact with air and reaction temperature is maintained at melting point of the silicon or less.

Abstract: The present invention relates to a method and apparatus for forming a thin film using the ALD process. Prior to the ALD process where each of a plurality of source gasses is supplied one by one, plural times, a pretreatment process is performed in which the source gasses are simultaneously supplied to shorten an incubation period and improve throughput.

Abstract: This invention relates to an improvement in a deposition process for producing low dielectric films having a dielectric constant of 3, preferably <2.7 and lower. The process comprises the steps: (a) forming a liquid precursor solution comprised of an organosilicon source containing both Si—O and Si—C bonds and solvent; (b) generating a liquid mist of said liquid precursor solution, said mist existing as precursor solution droplets having a number average droplet diameter size of less than 0.5 ?m; (c) preferably electrically charging the liquid mist of said liquid precursor solution droplets; (d) depositing liquid mist of said liquid precursor solution droplets onto a substrate; and, (e) converting the thus deposited liquid mist of said liquid precursor solution droplets to a solid, low dielectric film.

Abstract: An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.

Abstract: A method of manufacturing a semiconductor device includes irradiating a region to be crystallized of a non-monocrystalline semiconductor film with laser beam modulated by an optical modulator to have light intensity distribution having a minimum light intensity line or minimum light intensity spot to crystallize the region, and heating the crystallized region by irradiating light from a flash lamp onto the crystallized region.

Abstract: An integrated circuit and method of fabrication including a non-semiconductor material substrate with a layer of single crystal rare earth deposited on the surface thereof. A layer of single crystal semiconductor material is grown on the layer of single crystal rare earth and an integrated circuit is formed in the layer of single crystal semiconductor material. In a preferred embodiment the single crystal semiconductor material is silicon and the integrated circuit is formed by standard semiconductor industry processes.

Abstract: The present invention relates to control of copper contamination to semiconductor substrates upon operation of a heat treatment apparatus which is a semiconductor manufacturing apparatus and which is constructed with quartz products having been contaminated with copper when machined. The quartz product is placed in a heating atmosphere on the stage where it is not still used for a heat treatment for semiconductor substrates. Baking gases including a hydrogen chloride gas and a gas for enhancing activity of the hydrogen chloride gas, for example, an oxygen gas, are then supplied to the quartz product. Consequently, the copper concentration in the region from the surface to the 30 ?m depth of the quartz product can be controlled below 20 ppb, preferably below 3 ppb. The baking process may be carried out before or after assembling the quartz product into the heat treatment apparatus.

Abstract: An integrated circuit device is manufactured by forming an insulating layer on a substrate. A capping layer is formed on the insulating layer and both the capping layer and the insulating layer are patterned. Insulating spacers are formed on sidewalls of the insulating layer so that the insulating spacers, the capping layer, and the substrate enclose the insulating layer.

Abstract: One or more aspects of the present invention relate to forming a dielectric suitable for use as a gate dielectric in a transistor. The gate dielectric is formed by a nitridation process that adds nitrogen to a semiconductor substrate.

Abstract: Methods and apparatus for preparing a porous low-k dielectric material on a substrate are provided. The methods optionally involve the use of ultraviolet radiation to react with and remove porogen from a porogen containing precursor film leaving a porous dielectric matrix and further exposing the dielectric matrix to ultraviolet radiation to increase the mechanical strength of the dielectric matrix. Some methods involve activating a gas to create reactive gas species that can clean a reaction chamber. One disclosed apparatus includes an array of multiple ultraviolet sources that can be controlled such that different wavelengths of light can be used to irradiate a sample at a time.

Abstract: In forming a high density plasma oxide film, a projection shaped like the mesa, the peaked roof, the cone or the like is formed on an element formation region. This projection gives rise to a problem of producing a polishing scar when the CMD (Chemical Mechanical Polishing) with a ceria slurry is performed. A film having a polishing rate equivalent to the one of the high density plasma oxide film is formed on the high density plasma oxide film to reinforce a projection in the shape of a triangular prism, a cone or such, and, thereafter, the polishing is carried out, using a ceria slurry. In another method, after the first CMP polishing is performed, using a silica slurry containing grains of small particle size which make no aggregation, the second CMP polishing is performed, using a ceria slurry.

Abstract: Methods and apparatuses are disclosed relating to blocking ultraviolet electromagnetic radiation from a semiconductor. Ultraviolet electromagnetic radiation, such as ultraviolet electromagnetic radiation generated by a plasma process, which may otherwise damage a semiconductor can be blocked from one or more layers below an ultraviolet blocking layer.

Abstract: The invention is a method of determining a set temperature profile of a method of controlling respective substrate temperatures of plurality of groups in accordance with respective corresponding set temperature profiles. The invention includes a first heat processing step of controlling respective substrate temperatures of a plurality of groups in accordance with respective predetermined provisional set temperature profiles for first-batch substrates that are classified into the plurality of groups, and of introducing a process gas to conduct a heat process to form films on the substrates; a first film-thickness measuring step of measuring a thickness of the films formed on the substrates; and a first set-temperature-profile amending step of respectively amending the provisional set temperature profiles based on the measured thickness, in such a manner that a thickness of films formed during a heat process is substantially the same between the plurality of groups.

Abstract: Disclosed herein is a method for forming quantum dots, comprising the steps of (a) depositing a metal thin layer onto a substrate, (b) coating a dielectric precursor onto the metal thin layer, and (c) stepwisely heating the resultant substrate; or a method for forming quantum dots, comprising the steps of (a) mixing a dielectric precursor diluted in a solvent and a metal powder and stirring the mixture, (b) coating the mixture onto a substrate, and (c) heating the resultant substrate. The method can easily control the size, density and uniformity of metal oxide quantum dots.

Abstract: A bi-layer silicon electrode and its method of fabrication is described. The electrode of the present invention comprises a lower polysilicon film having a random grain microstructure, and an upper polysilicon film having a columnar grain microstructure.

Abstract: Method for making three-dimensional structures. A template is provided having at least two conductive regions separated by a non-conductive region. The template is disposed in an electrolyte in an electrodeposition cell and a voltage is established between one of the conductive regions and an electrode in the cell. Material is deposited on the one of the conductive regions connected to the voltage and subsequently bridges to the other conductive region with material deposition continuing on both of the at least two regions. The non conductive region may be a gap and the gap dimension is selected to regulate height differences between the at least two conductive regions.

Abstract: An apparatus on a wafer, comprising: a first metal layer of a wall, a second metal layer of the wall, a third metal layer of the wall comprising: one or more base frames, a fourth metal layer of the wall comprising: one or more vertical frame pairs each on top of the one or more base frames and having a pass-thru therein, a fifth metal layer of the wall comprising: one or more top frames each over the pass-thru; and a metal lid.

Abstract: A method for forming a thin film on a gate electrode reduces oxidation of the gate electrode during a re-oxidation process to fix the damage to the gate oxide film caused during the formation of the gate electrode pattern. The gate electrode pattern formed in this manner will have reduced defects after re-oxidation. After a gate oxide film is formed on a substrate, a gate electrode pattern is formed on the gate oxide film through an etching process. A thin film that includes nitride is then continuously formed on the gate oxide film and on the gate electrode by utilizing a deposition rate difference between the thin film on the gate oxide film and on the thin film forming the gate electrode. Because of the thin film formed on the gate electrode, oxidation of the gate electrode is reduced during the re-oxidation of the gate oxide film.

Abstract: Roughly described, a silicon layer transitions from polysilicon at one surface to amorphous silicon at the opposite surface. The transition can be monotonic, and can be either continuous or it can change abruptly from polysilicon to amorphous silicon. If such a layer is formed as the floating gate of a floating gate transistor structure, the larger grain structure adjacent to the tunnel dielectric layer reduces the formation of a tip (protrusion) and thus reduces leakage. On the other hand, the smaller grain structure adjacent to the gate dielectric layer produces a smooth, more uniform gate dielectric layer. The polysilicon-to-amorphous silicon transistor can be fabricated with a temperature profile that favors polysilicon formation at the start of floating gate deposition, and transitions during deposition to a temperature that favors amorphous silicon deposition at the end of floating gate deposition.

Abstract: A method of forming a polycrystalline silicon layer includes: disposing a mask over the amorphous silicon layer, the mask having a plurality of transmissive regions, the plurality of transmissive regions being disposed in a stairstep arrangement spaced apart from each other in a first direction and a second direction substantially perpendicular from the first direction, each transmissive region having a central portion and first and second side portions that are adjacent to opposite ends of the central portion along the first direction, and wherein each of the portions has a length along the first direction and a width along the second direction, and wherein the width of first and second portions decreases away from the central portion along the first direction; irradiating a laser beam onto the amorphous silicon layer a first time through the mask to form a plurality of first irradiated regions corresponding to the plurality of transmissive regions, each first irradiated region having a central portion, and

Abstract: A thin film transistor having a source region and a drain region having a low melting point region composed of a semiconductor with a melting point lower than that of the semiconductor of the channel region is provided. In the thin film transistor, the dopant concentrations of the low melting point region of the source region adjacent to the channel region and the low melting point region of the drain region adjacent to the channel region are precisely controlled. Using the thin film transistor, a high performance thin film transistor array substrate is also provided, as well as a high display speed liquid crystal display device and a high display speed electroluminescent display device having a high aperture ratio or a high pixel resolution.

Abstract: Ultra-thin gate oxides are formed by exposing the upper surface of a substrate to a pulsed laser light beam in an atmosphere containing oxygen. Embodiments include exposing a silicon substrate to a pulsed laser light beam at a radiant fluence of 0.1 to 0.8 joules/cm2 for 1 to 10 nanoseconds to form a gate oxide layer having a thickness of 3 Å to 8 Å, e.g., 3 Å to 5 Å.

Abstract: A process for forming a thin layer of Silicon nanocrystals in an oxide layer is disclosed. The process includes, on a semiconductive substrate, thermally oxidizing a first portion of the substrate into an oxide layer, forming Silicon ions within the layer of oxide, and thermally treating the Silicon ions to become the thin layer of Silicon nanocrystals. In the inventive process the formation of the Silicon ions is by ionic implantation of the Silicon ions into the oxide at an ionization energy of between 0.1 keV and 7 keV, and preferably between 1 and 5 keV. This allows the Silicon atoms to coalesce in a lower temperature than would otherwise be possible. Additionally, more than one layer of nanocrystals can be formed by performing more than one implantation at more than one energy level. Embodiments of the invention can be used to form non-volatile memory devices with a very high quality having a very small size.

Abstract: Disclosed is a method of forming the floating gate in the flash memory device. After the first polysilicon film is deposited on the semiconductor substrate, the trench is formed on the first polysilicon film with the pad nitride film not deposited. The HDP oxide film is then deposited to bury the trench. Next, the HDP oxide film is etched to define a portion where the second polysilicon film will be deposited in advance. The second polysilicon film is then deposited on the entire top surface, thus forming the floating gate. Thus, it is possible to completely remove a moat and an affect on EFH (effective field oxide height), solve a wafer stress by simplified process and a nitride film, and effectively improve the coupling ratio of the flash memory device.

Abstract: A semiconductor device 100 includes a low-k dielectric insulator 104. In the preferred embodiment, a low-k dielectric material 104 is deposited. This material 104 is then cured using a plasma cure step. The cure process causes the density of the top portion 106 of layer 104 to be increased. The higher density portion 106, however, also has a higher dielectric constant. As a result, the dielectric constant of the layer 104 can be reduced by removing this higher density portion 106. This leads to a lower dielectric constant (e.g., less than about 3) of the bulk film.

Abstract: An operating semiconductor layer is formed in such a manner that amorphous silicon layer is formed to be shaped so that it has a wide region and a narrow region and the narrow region is connected to the wide region at a position asymmetric to the wide region, and the amorphous silicon layer is crystallized by scanning a CW laser beam from the wide region toward the narrow region in a state that a polycrystalline silicon layer as a heat-retaining layer encloses the narrow region from a side face through the silicon oxide layer.

Abstract: A laser beam irradiation method that achieves uniform crystallization, even if a film thickness of an a-Si film or the like fluctuates, is provided. The present invention provides a laser beam irradiation method in which a non-single crystal semiconductor film is formed on a substrate having an insulating surface and a laser beam having a wavelength longer than 350 nm is irradiated to the non-single crystal semiconductor film, thus crystallizing the non-single crystal silicon film. The non-single crystal semiconductor film has a film thickness distribution within the surface of the substrate, and a differential coefficient of a laser beam absorptivity with respect to the film thickness of the non-single crystal semiconductor film is positive.

Abstract: There is provided a silica microstructure fabrication method. An etch stop layer is first partially deposited on an etching area of a first silica layer formed on a semiconductor substrate. A second silica layer is deposited on the surfaces of the etch stop layer and the first silica layer. A mask patterned according to the shape of the etching area is formed on the surface of the second silica layer. The second silica layer is removed from the etching area using the mask by dry etching, and the etch stop layer is removed by wet etching. A silica microstructure which is manufactured according to the present method has the second silica layer removed according to a predetermined vertical profile to provide a precise removal of the overcladding layer in a microstructure.

Abstract: An apparatus on a wafer, including; a first metal layer of a wall, a second metal layer of the wall, a third metal layer of the wall including; one or more base frames, a fourth metal layer of the wall including; one or more vertical frame pairs each on top of the one or more base frames and having a pass-thru therein, a fifth metal layer of the wall including; one or more top frames each over the pass-thru; and a metal lid.

Abstract: A high voltage semiconductor device including a semiconductor substrate on which a semi-insulating polycrystalline silicon layer is formed to alleviate electric field concentration in a field region, is disclosed. A thermal oxide layer is formed on the semi-insulating polycrystalline silicon layer to serve as a protective layer. The thermal oxide layer forms a good interface with the semi-insulating polycrystalline silicon layer compared to a wet etched oxide layer or a chemical vapor deposition (CVD) oxide layer, thereby decreasing the amount of leakage current. In addition, compared to a dual semi-insulating polycrystalline silicon layer, the thermal oxide layer exhibits a high surface protection effect and a high resistance against dielectric breakdown. It also allows a great reduction in fabrication time.

Abstract: A method has been provided for forming a polycrystalline silicon (p-Si) film with a small amount of hydrogen. Such a film has been found to have excellent sheet resistance, and it is useful in the fabrication of liquid crystal display (LCD) panels made from thin film transistors (TFTs). The low hydrogen content polycrystalline silicon films are made from introducing a small amount of hydrogen gas, with Ar, during the sputter deposition of an amorphous silicon film. The hydrogen content in the film is regulated by controlling the deposition temperatures and the volume of hydrogen in the gas feed during the sputter deposition. The polycrystalline silicon film results from annealing the low hydrogen content amorphous silicon film thus formed.

Abstract: After a GaN film 12 is formed on a (0001) plane sapphire (Al2O3) substrate 11, islands of the GaN film 12 are formed by wet etching. An upper part of the islands of the GaN film 12 is a single-crystal layer. By performing epitaxial growth over the islands of GaN film 12, a GaN film 15 with little crystal defect is obtained.

Abstract: A window is mounted directly to an upper surface of a micromirror device chip. More particularly, the window is mounted above a micromirror device area on the upper surface of the micromirror device chip by a bead. The window in combination with the bead form a hermetic enclosure about the micromirror device area thus protecting the micromirror device area from moisture and contamination.

Abstract: In connection with wafer planarization, an apparatus for forming a layer of material having a substantially uniform thickness and substantially parallel first and second major surfaces includes a pair of pressing elements and a stop. Each of the pair of pressing elements has a flat pressing surface. The pressing surfaces are opposed to one another and operable to compress a quantity of the material therebetween. The stop is positioned at least partially between the pressing surfaces and has a thickness substantially equal to the desired uniform thickness of the layer. The stop is positioned to establish a spacing between the flat pressing surfaces that is substantially equal to the thickness of the stop and thereby to the desired uniform thickness of the layer when the pressing elements engage the stop.