Catalyst Aided Deposition Patents (Class 438/903)
  • Patent number: 8497144
    Abstract: A method for manufacturing a light emitting chip comprises: providing a substrate with a catalyst layer formed thereon, the catalyst layer being etched to form a number of patterns which are spaced from each other by multiple gaps; forming a buffer layer in the multiple gaps of the patterned catalyst layer, the buffer layer comprising a patterned carbon nano tube structure formed along an extending direction of the substrate, the carbon nano tube structure being comprised of nitride semiconductor; removing the catalyst layer from the substrate; growing a cap layer from the substrate to cover the buffer layer; and growing a light emitting structure from a top of the cap layer, the light emitting structure sequentially comprising a first cladding layer, a light emitting layer, and a second cladding layer.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: July 30, 2013
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Jian-Shihn Tsang
  • Patent number: 8350391
    Abstract: The sheet structure includes a plurality of linear structure bundles including a plurality of linear structures of carbon atoms arranged at a first gap, and arranged at a second gap larger than the first gap, a graphite layer formed in a region between the plurality of linear structure bundles and connected to the plurality of linear structure bundles, and a filling layer filled in the first gap and the second gap and retaining the plurality of linear structure bundles and the graphite layer.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: January 8, 2013
    Assignee: Fujitsu Limited
    Inventors: Daiyu Kondo, Taisuke Iwai, Yoshitaka Yamaguchi, Ikuo Soga
  • Patent number: 8258060
    Abstract: The sheet structure includes a plurality of linear structure bundles including a plurality of linear structures of carbon atoms arranged at a first gap, and arranged at a second gap larger than the first gap, a graphite layer formed in a region between the plurality of linear structure bundles and connected to the plurality of linear structure bundles, and a filling layer filled in the first gap and the second gap and retaining the plurality of linear structure bundles and the graphite layer.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: September 4, 2012
    Assignee: Fujitsu Limited
    Inventors: Daiyu Kondo, Taisuke Iwai, Yoshitaka Yamaguchi, Ikuo Soga
  • Patent number: 8148708
    Abstract: A resistive memory device includes a first conductive line on a substrate, a vertical selection diode comprising a nanowire or a nanotube and being arranged over the first conductive line, a resistive element including a resistive layer arranged over the vertical selection diode; and a second conductive line arranged over the resistive element.
    Type: Grant
    Filed: December 26, 2008
    Date of Patent: April 3, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yun-Taek Hwang, Yu-Jin Lee
  • Patent number: 7994017
    Abstract: A self-aligned, silicon carbide power metal oxide semiconductor field effect transistor includes a trench formed in a first layer, with a base region and then a source region epitaxially regrown within the trench. A window is formed through the source region and into the base region within a middle area of the trench. A source contact is formed within the window in contact with a base and source regions. The gate oxide layer is formed on the source and base regions at a peripheral area of the trench and on a surface of the first layer. A gate electrode is formed on the gate oxide layer above the base region at the peripheral area of the trench, and a drain electrode is formed over a second surface of the first layer.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: August 9, 2011
    Assignee: Cree, Inc.
    Inventors: Christopher Harris, Kent Bertilsson, Andrei Konstantinov
  • Patent number: 7888271
    Abstract: A method for making silicon nano-structure, the method includes the following steps. Firstly, providing a growing substrate and a growing device, the growing device comprising a heating apparatus and a reacting room. Secondly, placing the growing substrate and a quantity of catalyst separately into the reacting room. Thirdly, introducing a silicon-containing gas and hydrogen gas into the reacting room. Lastly, heating the reacting room to a temperature of 500˜1100° C.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: February 15, 2011
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Hai-Lin Sun, Kai-Li Jiang, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 7842539
    Abstract: There are provided a method of manufacturing a zinc oxide semiconductor, and a zinc oxide semiconductor manufactured using the method. A metal catalyst layer is formed on a zinc oxide thin film that has an electrical characteristic of a n-type semiconductor, and a heat treatment is performed thereon so that the zinc oxide thin film is modified into a zinc oxide thin film having an electrical characteristic of a p-type semiconductor. Hydrogen atoms existing in the zinc oxide thin film are removed by a metal catalyst during the heat treatment. Accordingly, the hydrogen atoms existing in the zinc oxide thin film are removed by the metal catalyst and the heat treatment, and the concentration of holes serving as carriers is increased. That is, an n-type zinc oxide thin film is modified into a highly-concentrated p-type zinc oxide semiconductor.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: November 30, 2010
    Assignee: Gwangju Institute of Science and Technology
    Inventors: Seong Ju Park, Min Suk Oh, Dae Kyu Hwang, Min Ki Kwon
  • Patent number: 7601639
    Abstract: The present invention provides, in one aspect, the present invention provides, in one embodiment, a method of conditioning a deposition chamber 100. This method comprises placing an undercoat on the walls of a deposition chamber 100 and depositing a pre-deposition coat over the undercoat with a plasma gas mixture conducted at a high pressure and with high gas flow.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: October 13, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Salvator F. Pavone, Jason J New
  • Patent number: 7582507
    Abstract: A catalyst supporting substrate includes a first region (54) which is formed on a substrate (50); and a second region (55) which is formed covering a part of the first region. The first region (54) includes a catalyst supporting portion (54a) containing a first material. The second region (55) includes a catalyst portion (55) containing a second material which is different from the first material. The first material includes a metal containing at least one of elements selected from the second group to the fourteenth group of the periodic table or a compound thereof. The second material is a catalyst which grows carbon nanotubes in a vapor phase.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: September 1, 2009
    Assignee: NEC Corporation
    Inventor: Hiroo Hongo
  • Patent number: 7521361
    Abstract: A method for manufacturing a wiring substrate by an electroless plating method that precipitates metal without using a plating resist is provided. The method includes the steps of: (a) providing a catalyst layer having a predetermined pattern on a substrate; (b) dipping the substrate in an electroless plating solution to thereby precipitate metal on the catalyst layer to provide a first metal layer; (c) washing a top surface of the substrate with water; and (d) dipping the substrate in an electroless plating solution to thereby precipitate metal on the first metal layer to provide a second metal layer.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: April 21, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Satoshi Kimura, Hidemichi Furihata, Takeshi Kijima
  • Patent number: 7446044
    Abstract: Switches having an in situ grown carbon nanotube as an element thereof, and methods of fabricating such switches. A carbon nanotube is grown in situ in mechanical connection with a conductive substrate, such as a heavily doped silicon wafer or an SOI wafer. The carbon nanotube is electrically connected at one location to a terminal. At another location of the carbon nanotube there is situated a pull electrode that can be used to elecrostatically displace the carbon nanotube so that it selectively makes contact with either the pull electrode or with a contact electrode. Connection to the pull electrode is sufficient to operate the device as a simple switch, while connection to a contact electrode is useful to operate the device in a manner analogous to a relay. In various embodiments, the devices disclosed are useful as at least switches for various signals, multi-state memory, computational devices, and multiplexers.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: November 4, 2008
    Assignee: California Institute of Technology
    Inventors: Anupama B. Kaul, Eric W. Wong, Richard L. Baron, Larry Epp
  • Patent number: 7410911
    Abstract: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmospheres and 25 atmospheres N2O and a temperature range of 600° C. to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: August 12, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Daniel Gealy, Dave Chapek, Scott DeBoer, Husam N. Al-Shareef, Randhir Thakur
  • Patent number: 7282457
    Abstract: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace is disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmosphere to 25 atmosphere N2O and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: October 16, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Daniel Gealy, Dave Chapek, Scott DeBoer, Husam N. Al-Shareef, Randhir Thakur
  • Patent number: 7241690
    Abstract: The present invention provides, in one aspect, a method of conditioning a deposition chamber 100. An undercoat is placed on the walls of a deposition chamber 100 and a pre-deposition coat is deposited over the undercoat with a plasma gas mixture conducted at a high pressure and with high gas flow.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: July 10, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Salvator F. Pavone, Jason J. New
  • Patent number: 7183131
    Abstract: A process for producing a nanoelement arrangement and to a nanoelement arrangement. A first nanoelement is at least partially covered with catalyst material for catalyzing the growth of nanoelements. Furthermore, at least one second nanoelement is grown on the catalyst material. Also, a nanoelement arrangement having a first nanoelement on which at least one predetermined region is covered with catalyst material for catalyzing the growth of nanoelements, and at least one second nanoelement grown on the catalyst material.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: February 27, 2007
    Assignee: Infineon Technologies AG
    Inventors: Eugen Unger, Georg Stefan Dusberg, Andrew Graham, Maik Liebau
  • Patent number: 7044821
    Abstract: Plural first exhaust pipes are disposed as exhaust paths at an upper portion of a heat treatment apparatus. Exhaust gases are discharged from the inside of the heat treatment apparatus to the respective exhaust pipes. Inlets of catalyst units are connected to outlets of the first exhaust pipes, and second exhaust pipes are connected to outlets of the catalyst units. Exhaust gases are discharged from exhaust ports of the second exhaust pipes to the outside (e.g., the atmosphere) of the heat treatment apparatus.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: May 16, 2006
    Assignees: Pioneer Corporation, Pioneer Display Products Corporation
    Inventors: Junji Kogure, Masaaki Nakamura, Mineaki Yokoyama
  • Patent number: 6992000
    Abstract: A nonconductor product is soaked in a solution suspending a semiconducting powder and is subjected to light irradiation in the solution so that polar group is formed on the surface of the nonconductor product, and then electroless plating is performed on the surface on which the polar group is formed. A resin product is subjected to electroless plating after ultraviolet treatment in which ultraviolet rays are irradiated through water or a solution is performed. Further, electroless plating or electroplating with a different or the same kind of metal is performed on the electroless-plated layer formed by electroless plating.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: January 31, 2006
    Assignees: Kanto Kasei Co., Ltd., Kanto Gakuin University Surface Engineering Research Institute, Toyota Jidsoha Kabushiki Kaisha
    Inventors: Hideo Honma, Atsushi Kawahara, Akira Teranishi
  • Patent number: 6955996
    Abstract: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmospheres and 25 atmospheres N2O and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: October 18, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Daniel F Gealy, Dave Chapek, Scott DeBoer, Husam N. Al-Shareef, Randhir Thakur
  • Patent number: 6949478
    Abstract: A method of forming an oxide film having high insularity capability is performed within an ultra clean environment, using charged particles.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: September 27, 2005
    Inventors: Tadahiro Ohmi, Takashi Imaoka, Hisayuki Shimada, Nobuhiro Konishi, Mizuho Morita, Takeo Yamashita, Tadashi Shibata, Hidetoshi Wakamatsu, Jinzo Watanabe, Shintaro Aoyama, Masakazu Nakamura
  • Patent number: 6936906
    Abstract: The present invention generally relates to filling of a feature by depositing a barrier layer, depositing a seed layer over the barrier layer, and depositing a conductive layer over the seed layer. In one embodiment, the seed layer comprises a copper alloy seed layer deposited over the barrier layer. For example, the copper alloy seed layer may comprise copper and a metal, such as aluminum, magnesium, titanium, zirconium, tin, and combinations thereof. In another embodiment, the seed layer comprises a copper allloy seed layer deposited over the barrier layer and a second seed layer deposited over the copper alloy seed layer. The copper alloy seed layer may comprise copper and a metal, such as aluminum, magnesium, titanium, zirconium, tin, and combinations thereof The second seed layer may comprise a metal, such as undoped copper. In still another embodiment, the seed layer comprises a first seed layer and a second seed layer.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: August 30, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Hua Chung, Ling Chen, Jick Yu, Mei Chang
  • Patent number: 6844260
    Abstract: Systems and methods for insitu post atomic layer deposition (ALD) destruction of active species are provided. ALD processes deposit multiple atomic layers on a substrate. Pre-cursor gases typically enter a reactor and react with the substrate resulting in a monolayer of atoms. After the remaining gas is purged from the reactor, a second pre-cursor gas enters the reactor and the process is repeated. The active species of some pre-cursor gases do not readily purge from the reactor, thus increasing purge time and decreasing throughput. A high-temperature surface placed in the reactor downstream from the substrate substantially destroys the active species insitu. Substantially destroying the active species allows the reactor to be readily purged, increasing throughput.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: January 18, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Demetrius Sarigiannis, Shuang Meng, Garo J. Derderian
  • Patent number: 6827790
    Abstract: a method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five (5) atmospheres to twenty-five (25) atmospheres N2O and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, rhodium, nickel, silver, and gold.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: December 7, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Daniel Gealy, Dave Chapek, Scott DeBoer, Husam N. Al-Shareef, Randhir Thakur
  • Patent number: 6780664
    Abstract: Various microscopy probes and methods of fabricating the same are provided. In one aspect, a method of fabricating a microscopy probe is provided that includes providing a member and forming a first film on the member. The first film fosters growth of carbon nanotubes when exposed to a carbon-containing compound. A second film is formed on the first film. The second film has an opening therein that exposes a portion of the first film. A carbon nanotube is formed on the exposed portion of the first film.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: August 24, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Rama R. Goruganthu, Michael R. Bruce, Thomas Chu, Miguel Santana, Jr., Robert Powell
  • Patent number: 6774052
    Abstract: A method of making a permeable base transistor (PBT) is disclosed. According to the method, a semiconductor substrate is provided, a base layer is provided on the substrate, and a semiconductor layer is grown over the base layer. The base layer includes metallic nanotubes, which may be grown or deposited on the semiconductor substrate. The nanotube base layer separates emitter and collector layers of semiconductor material.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: August 10, 2004
    Assignee: Nantero, Inc.
    Inventors: Bernhard Vögeli, Thomas Rueckes, Brent M. Segal
  • Patent number: 6653212
    Abstract: A thin film forming apparatus S having a vacuum chamber 1, a substrate 10, a thermal catalyst 5, and a heating means 5a for heating this thermal catalyst 5, wherein a gas introduction system 3 for feeding the gas is connected in the vacuum chamber 1, the gas is fed from this gas introduction system 3 to the vacuum chamber 1, and thin films are formed on the surface of the substrate 10 by utilizing a thermal decomposition reaction or catalytic reaction by the thermal catalyst 5, the gas introduction system 3 is for introducing a carrier gas containing hydrogen and a material gas for forming the thin film on the substrate 10, and the carrier gas is constantly fed into the vacuum chamber 1 at least during the formation of the thin film.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: November 25, 2003
    Assignee: Sony Corporation
    Inventors: Hideo Yamanaka, Hisayoshi Yamoto
  • Patent number: 6596651
    Abstract: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmospheres and 25 atmospheres N2O and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: July 22, 2003
    Assignee: Micron Technology, Inc.
    Inventors: F. Daniel Gealy, Scott DeBoer, Dave Chapek, Husam N. Al-Shareef, Randhir Thakur
  • Patent number: 6495458
    Abstract: The present invention provides a method for forming a substantially carbon- and oxygen-free conductive layer, wherein the layer can contain a metal and/or a metalloid material. According to the present invention, a substantially carbon- and oxygen-free conductive layer is formed in an oxidizing atmosphere in the presence of an organometallic catalyst using, for example, a chemical vapor deposition process. Such layers are particularly advantageous for use in memory devices, such as dynamic random access memory (DRAM) devices.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: December 17, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Patent number: 6451694
    Abstract: In a process for mitigating and/or eliminating the abnormal growth of underlying polysilicon in dichloro silane-based CVD polycide WSix films, a first technique conducts the deposition of the underlying polysilicon layer at a temperature that substantially avoids crystallization of the underlying polysilicon. A second approach reduces the exposure (for example time period and or concentration) of the mono-silane SiH4 post flush, so as to avoid infusion of silicon into the underlying polysilicon layer, and resulting abnormal growth. In this manner, abnormal effects, such as stress fractures formed in subsequent layers, can be eliminated.
    Type: Grant
    Filed: April 4, 2001
    Date of Patent: September 17, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeon-Sig Lim, Jin-Ho Jeon, Jong-Seung Yi, Chul-Hwan Choi
  • Patent number: 6423649
    Abstract: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmospheres and 25 atmospheres N2O and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.
    Type: Grant
    Filed: July 20, 2001
    Date of Patent: July 23, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Daniel Gealy, Dave Chapek, Scott DeBoer, Husam N. Al-Shareef, Randhir Thakur
  • Patent number: 6294404
    Abstract: A semiconductor integrated circuit according to the present invention comprises a synchronous SRAM, a signal generation circuit generating a chip selection signal, a clock signal etc. supplied to the synchronous SRAM, a voltage set circuit setting the voltage of a system power supply line and a controller controlling the signal generation circuit and the voltage set circuit. When setting the synchronous SRAM in a power down mode, the chip selection signal is set in a nonselective state and the power supply voltage of the system power supply line is stepped down to a standby potential. Thus, the synchronous SRAM enters a standby state having extremely low power consumption.
    Type: Grant
    Filed: May 10, 2000
    Date of Patent: September 25, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hirotoshi Sato
  • Patent number: 6291364
    Abstract: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmosphere to 25 atmosphere N2O and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: September 18, 2001
    Assignee: Micron Technology, Inc.
    Inventors: F. Daniel Gealy, Dave Chapek, Scott DeBoer, Husam N. Al-Shareef, Randhir Thakur
  • Patent number: 6126989
    Abstract: A method for depositing copper on a titanium-containing surface of a substrate is provided. The method includes forming a patterned catalyst material on the substrate, such that the titanium-containing surface is exposed in selected regions. The catalyst material has an oxidation half-reaction potential having a magnitude that is greater than a magnitude of a reduction half-reaction potential of titanium dioxide. Copper is then deposited from an electroless solution onto the exposed regions of the titanium-containing surface.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: October 3, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Karl Robinson, Ted Taylor
  • Patent number: 5792705
    Abstract: A planarization process, featuring removal of spin on glass, used to fill narrow spaces between metal lines, has been developed. A dual dielectric, of underlying silicon oxide, and overlying silicon nitride, are initially used to passivate the metal lines, followed by the spin on glass fill. A RIE etchback of the spin on glass proceeds to a point in which the silicon nitride, on the metal line, is exposed. The exposed silicon nitride is then removed leaving a silicon oxide passivated metal line, and seamless insulator filled spaces. The ability of not exposing the passivating silicon oxide to RIE echback process, allows seamless fills to result.
    Type: Grant
    Filed: September 2, 1997
    Date of Patent: August 11, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Kun Wang, Yuan-Chang Huang, Iman Hsu