Abstract: Methods of exposing conductive vias of semiconductor devices may comprise conformally forming a barrier material over conductive vias extending from a backside surface of a substrate. A self-planarizing isolation material may be formed over the barrier material. An exposed surface of the self-planarizing isolation material may be substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of protruding material of the conductive vias may be removed to expose the conductive vias. Removal of the self-planarizing isolation material, the barrier material, and the conductive vias may be stopped after exposing at least one laterally extending portion of the barrier material.

Abstract: A semiconductor device and method where a side wall insulating layer, extending perpendicular from a top surface of a semiconductor substrate, is prevented from contacting the semiconductor substrate by a barrier layer formed at an interface between the semiconductor substrate and the insulating layer.

Abstract: The invention includes embodiments of a method for designing a flip chip and the resulting structure. The starting point is a flip chip with a semiconductor substrate, one or more wiring levels, and a plurality of I/O contact pads (last metal pads/bond pads) for receiving and sending electrical current. There is also a plurality of C4 bumps for connecting the I/O contact pads to another substrate. Then it is determined which of the C4s of the plurality of C4 bumps have a level of susceptibility to electromigration damage that meets or exceeds a threshold level of susceptibility, and in response, plating a conductive structure with a high electrical current carrying capacity (such as a copper pillar, copper pedestal, or partial copper pedestal) onto the corresponding I/O contact pads and adding a solder ball to a top portion of the conductive structure. The resulting structure is a flip chip wherein only a select few C4 bumps use enhanced C4s (such as copper pedestals) reducing the chance of defects.

Abstract: A semiconductor contact structure and method provide contact structures that extend through a dielectric material and provide contact to multiple different subjacent materials including a silicide material and a non-silicide material such as doped silicon. The contact structures includes a lower composite layer formed using a multi-step ionized metal plasma (IMP) deposition operation. A lower IMP film is formed at a high AC bias power followed by the formation of an upper IMP film at a lower AC bias power. The composite layer may be formed of titanium. A further layer is formed as a liner over the composite layer and the liner layer may advantageously be formed using CVD and may be TiN. A conductive plug material such as tungsten or copper fills the contact openings.

Abstract: Plug contacts may be formed with barrier layers having thicknesses of less than 50 ? in some embodiments. In one embodiment, the barrier layer may be formed by the chemical vapor deposition of diborane, forming a boron layer between a metallic contact and the surrounding dielectric and between a metallic contact and the substrate and/or substrate contact. This boron layer may be substantially pure boron and boron silicide.

Abstract: Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier precursor under conditions to cause at least one alloying element in the barrier precursor to form a dielectric barrier between the wire and the ILD. The dielectric barrier is therefore a self-forming, self-aligned barrier. Thermal processing is done under conditions to cause the at least one alloying element to migrate from a zone of higher concentration thereof to a zone of lower concentration thereof to further form the dielectric barrier. Various apparatus are made by the process.

Abstract: After a ferroelectric capacitor is formed, an Al wiring (conductive pad) connected to the ferroelectric capacitor is formed. Then, a silicon oxide film and a silicon nitride film are formed around the Al wiring. Thereafter, as a penetration inhibiting film which inhibits penetration of moisture into the silicon oxide film, an Al2O3 film is formed.

Abstract: Embodiments in accordance with the present invention relate to structures and methods allowing stress-induced electromigration to be tested in multiple interconnect metallization layers. An embodiment of a testing structure in accordance with the present invention comprises at least two segments of a different metal layer through via structures. Each segment includes nodes configured to receive force and sense voltages. Selective application of force and sense voltages to these nodes allows rapid and precise detection of stress-induced immigration in each of the metal layers.

Abstract: The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.

Abstract: To arrange diffusion-inhibitory films 5a, 5b, and 5c for inhibiting the diffusion of a wiring material absent in a region on or above a light receiving unit 2, the diffusion-inhibitory films 5a, 5b, and 5c formed on a region above the light receiving unit 2 are selectively removed. Alternatively, the diffusion-inhibitory films are arranged only on top surfaces of wirings 4a, 4b, and 4c, and only a passivation film 12 and interlayer insulating films 3a, 3b, and 3c are arranged in the region on or above the light receiving unit 2. Thus, with less interface between different insulation films and less reflection of incident light in an incident region, the incident light 13 highly efficiently passes through these insulating films and comes into the light receiving unit 2. The light receiving unit 2 can thereby receive a sufficient quantity of the incident light 13.

Abstract: Provided is a method for forming a composite barrier layer with superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer generally form boundaries with dielectric materials and crystalline layers generally form boundaries with conductive materials such as interconnect materials.

Abstract: The invention generally relates to semiconductor devices, and more particularly to structures and methods for enhancing electromigration (EM) performance in interconnects. A method includes forming an interconnect, forming a cap on the interconnect, and forming a plurality of holes in the cap to improve electromigration performance of the interconnect.

Abstract: A semiconductor device includes a pattern layer formed on and/or over a semiconductor substrate, a fluorine-diffusion barrier layer containing a silicon-doped silicon oxide formed on and/or over the pattern layer, and an interlayer dielectric layer containing fluorine formed on and/or over the fluorine-diffusion barrier layer.

Abstract: A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.

Abstract: A method of monitoring and testing electro-migration and time dependent dielectric breakdown includes forming an addressable wiring test array, which includes a plurality or horizontally disposed metal wiring and a plurality of segmented, vertically disposed probing wiring, performing a single row continuity/resistance check to determine which row of said metal wiring is open, performing a full serpentine continuity/resistance check, and determining a position of short defects.

Abstract: The present invention relates generally to grids for gating a stream of charged particles and methods for manufacturing the same. In one embodiment, the present invention relates to a Bradbury-Nielson gate having transmission line grid elements. In one embodiment is a feed structure for a gating grid where a drive source is coupled to a feeding transmission line with the same geometry as the chopper and continues with the same geometry to a termination transmission line. Also included is a method for fabricating a gate for charged particles which includes micromachining at least two gate elements from at least one wafer, wherein each gate element includes at least one grid element; metalizing the grid elements; and assembling the gate elements such that the grid elements of the gate elements are interleaved, thereby forming a Bradbury Nielson gate.

Abstract: A semiconductor device includes: a p-type MIS transistor having a first gate electrode including silicon doped with p-type impurities; an n-type MIS transistor having a second gate electrode including silicon doped with n-type impurities; and a shared line which connects the p-type MIS transistor and the n-type MIS transistor and serves as a path of a power supply current or a ground current, the shared line including silicided silicon. The first gate electrode and the second gate electrode have silicided top portions, respectively, to establish electrical connection therebetween and the shared line has a line width larger than the line widths of the first gate electrode and the second gate electrode.

Abstract: A semiconductor device, in which a semiconductor integrated circuit having a multi-level interconnection structure is formed, according to an embodiment of the present invention, comprises a copper wiring and an insulating layer formed on a top surface of the copper wiring, wherein the copper wiring includes an additive for improving adhesion between the copper wiring and the insulating layer, and a profile of the additive has a gradient in which a concentration is gradually reduced as it goes from the top surface of the copper wiring toward the inside thereof, and has the highest concentration on the top surface of the copper wiring.

Abstract: There is provided a solution to the problem of the poor adhesion in the pad portion while inhibiting the dishing in the pad portion. An SiON film, which covers insulating areas and has an opening above Cu pad areas, is formed, and a barrier metal film is formed in the opening of the SiON film. Such constitution provides the structure, in which the upper portion of the interfaces between the Cu pad areas and the insulating areas are covered by the SiON film.

Abstract: In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

Abstract: A semiconductor device includes a cross diffusion barrier layer sandwiched between a gate layer and an electrode layer. The gate layer has a first gate portion of doped polysilicon of first conductivity type adjacent to a second gate portion doped polysilicon of second conductivity type. The cross diffusion barrier layer includes a combination of silicon and nitrogen. The cross diffusion barrier layer adequately prevents cross diffusion between the first and second gate portions while causing no substantial increase in the resistance of the gate layer.

Abstract: Electromigration and stress migration of Cu interconnects are significantly reduced by forming a composite capping layer comprising a layer of tantalum nitride on the upper surface of the inlaid Cu and a layer of ?-Ta on the titanium nitride layer. Embodiments include forming a recess in an upper surface of an upper surface of Cu inlaid in a dielectric layer, depositing a layer of titanium nitride of a thickness of 20 ? to 100 ? and then depositing a layer of ?-Ta at a thickness of 200 ? to 500 ?.

Abstract: A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

Abstract: A thin film transistor and a method of manufacturing the same includes forming a copper alloy line on substrate, an oxidation film formed on the upper surface of the copper alloy line. The copper alloy line includes a concentration y of magnesium, and the copper alloy line has a thickness t. the concentration y of magnesium in copper alloy line is related to the thickness is as follows: y ? 94 t .

Abstract: A method of manufacturing a semiconductor device including forming an insulator layer on an integrated circuit, forming a barrier layer having a first titanium film and a titanium nitride film on the insulator layer, heat-treating the barrier layer to release nitrogen gas from the titanium nitride film, forming a second titanium film on the barrier layer, and forming an aluminum film used as a wired metal on the second titanium film.

Abstract: A method for manufacturing a semiconductor device comprises: (a) forming a dummy gate provided with a sidewall spacer at its side wall and an anti-silicidation film thereon on a semiconductor substrate, as well as forming a source/drain region on the surface of the semiconductor substrate; (b) forming a metal film on the whole surface of the obtained semiconductor substrate, the resultant being subject to a silicide reaction to form a silicide layer only on the source/drain region; (c) forming an interlayer dielectric film on the obtained substrate, the surface of the interlayer dielectric film being removed until the anti-silicidation film is exposed; (d) removing the anti-silicidation film and the dummy gate to form a trench in the interlayer dielectric film; and (e) laminating a gate insulating film and gate electrode material film in the trench, the gate insulating film and gate electrode material film being removed until the surface of the interlayer dielectric film is exposed to form a gate electro

Abstract: A thin film transistor and a method of manufacturing the same includes forming a copper alloy line on substrate, an oxidation film formed on the upper surface of the copper alloy line. The copper alloy line includes a concentration y of magnesium, and the copper alloy line has a thickness t. the concentration y of magnesium in copper alloy line is related to the thickness is as follows: y ≤ 94 t .

Abstract: A semiconductor device includes a first insulating film comprising an opening, a capacitor formed at a selected position in the opening, a second insulating film formed at least in the opening, and a third insulating film formed on the second insulating film.

Abstract: A method of making a semiconductor device is described. That method comprises forming a conductive layer that contacts a via, wherein the conductive layer includes a sufficient amount of a dopant, which will diffuse in the direction that is opposite to the direction in which electrons will flow through the conductive layer, to reduce the electromigration of the material that comprises the bulk of the conductive layer without significantly increasing the conductive layer's resistance.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A first channel dielectric layer over the semiconductor has a first opening lined by a first barrier layer and filled by a first conductor core. A via dielectric layer having a via opening which is open to the first conductor core is formed over the first channel dielectric layer. A second channel dielectric layer with a second opening which is open to the via is formed over the via dielectric layer. A second conductor core fills the via and second channel openings. A second barrier layer lining the via and second channel openings under the second conductor core forms a barrier between the second conductor core and the via and second channel dielectric layers, but does not form a barrier between the first and the second conductor cores.

Abstract: A method and apparatus comprising thinning a substrate sufficiently to allow it to be mechanically compliant with a material deposited on its surface is disclosed. The mechanical compliance allows a reduction in the interlayer stress generated by dissimilarities in the materials.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An barrier layer lines the opening and a seed layer is deposited to line the barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is annealed to form an annealed region, which securely bonds the seed layer to the barrier layer and prevents electromigration along the surface between the seed and barrier layers.

Abstract: A microstructure comprises a conductive layer of aluminum, copper or alloys thereof on a substrate wherein the layer comprises metal grains at least about 0.1 microns and barrier material deposited in the grainboundaries of the surface of the metal is provided along with a method for its fabrication.

Abstract: The invention produces an integrated line/via interconnect structure comprising a high-modulus liner material that provides compression and back pressure, thus enhancing electromigration resistance and aiding heat dissipation.

Abstract: A mark structure (100) consists of a gate oxide film (102) formed on a semiconductor substrate (101), a gate wiring layer (103) formed on the gate oxide film (102), an insulating film (104) formed on the gate wiring layer (103) and a sidewall (105) formed in contact with side surfaces of the insulating film (104), the gate wiring layer (103) and the gate oxide film (102). An opaque bit line layer (113) is formed of a polycide consisting of a doped polysilicon layer (1131) and a tungsten silicide layer (1132), extending from on the interlayer insulating film (107) to on the mark structure (100). With this structure, a semiconductor device which allows measurement of alignment mark and overlay check mark with high precision in a lithography process, has no structure unnecessary for a mark and suppresses creation of extraneous matter in a process of manufacturing a semiconductor device to prevent deterioration in manufacturing process yield and a method of manufacturing the semiconductor device can be provided.

Abstract: The substrate according to the present invention is comprised of a silver/gold/grain element alloy layer, wherein the alloy forms an outside layer of the product. The grain element is selected from a group consisting of selenium, antimony, bismuth, nickel, cobalt, indium and combination thereof. The present invention has a particular application in forming the outside layer of various items, including a lead frame, a ball grid array, a header, a printed circuit board, a reed switch and a connector.

Abstract: Methods for fabricating memory devices having a multi-dot floating gate ensuring a desirable crystallization of a semiconductor film without ruining the flatness of the surface of the polycrystallized silicon layer and a tunnel oxide film, allowing desirable semiconductor dots to be produced, and allowing production of the memory devices having a multi-dot floating gate with ease and at low costs even when a substrate is made of glass or plastic.

Abstract: A method of encapsulating metal lines (130, 132, 134, 136, 138) by implantation of dopants to form surface regions (131, 133, 135, 137, 139) after the metal lines have been fabricated. The surface regions may act as passivation layers and electromigration inhibitors and so forth.

Abstract: A method for forming a damascene interconnection. After forming an insulating layer on a semiconductor substrate, the insulating layer is patterned and etched to form an opening. A barrier layer is formed on an entire surface of a resulting structure where the opening is formed. A seed layer is formed on at least on a sidewall of the opening on which the barrier layer is formed, and on a top surface of the insulating layer, using an ionized physical vapor deposition (PVD) apparatus having a target to which a power for making plasma is applied, and a chuck to which a radio frequency (RF) bias for accelerating ions is applied. When the seed layer is formed using an ionized PVD process, the power and bias are controlled to resputter an initial seed layer formed on a bottom of the opening. The resputtered seed layer is redeposited on the sidewall of the opening, forming a seed layer with a good step coverage characteristic on the sidewall.

Abstract: A semiconductor device having a barrier film comprising an extremely thin film formed of one or more monolayers each comprised of a two-dimensional array of metal atoms. In one exemplary aspect, the barrier film is used for preventing the diffusion of atoms of another material, such as a copper conductor, into a substrate, such as a semiconducting material or an insulating material. In one mode of making the semiconductor device, the barrier film is formed by depositing a precursor, such as a metal halide (e.g., BaF2), onto the substrate material, and then annealing the resulting film on the substrate material to remove all of the constituents of the temporary heteroepitaxial film except for a monolayer of metal atoms left behind as attached to the surface of the substrate. A conductor, such as copper, deposited onto the barrier film is effectively prevented from diffusing into the substrate material even when the barrier film is only one or several monolayers in thickness.

Abstract: An apparatus for improving electromigration reliability and resistance of a single- or dual-damascene via includes an imperfect barrier formed at the bottom of the via, and a stronger barrier formed at all other portions of the via. The imperfect barrier allows for metal atoms, such as copper atoms, to flow therethrough when the electromigration force pushes the metal atoms against the barrier. That way, the metal atoms that are pushed away from the downstream side of the barrier are replaced by metal atoms that flow through the barrier from the upstream side of the barrier. The imperfect barrier may be formed by biasing a wafer, and having the atoms resputter from the bottom of the via and adhere to the sidewalls of the via. The imperfect barrier may also be formed by a two-layered barrier, where a first layer corresponds to a good step coverage, poor barrier, and where the second barrier corresponds to a poor step coverage, good barrier.

Abstract: A method of fabricating a single electron tunneling (SET) device, the method including forming a source electrode and a drain electrode a predetermined distance apart from each other on an insulating substrate, forming a metal layer having a thickness on the order of nanometers between the source and drain electrodes, and forming quantum dots between the source and drain electrodes due to the movement of metal atoms/ions within the metal layer caused by applying a predetermined voltage to the source and drain electrodes. In the manufacture of an SET device, quantum dots can be formed by a simple method instead of an self assembled monolayer (SAM) method or lithographic methods. Thus, SET devices fabricated in this way have no material dependency, and are also applicable to large scale integration (LSI) structures. Also, since quantum dots are obtained by deposition and electromigration, SET devices having the above-described advantages can be mass-produced.

Abstract: A method is provided for forming a conductive interconnect, the method comprising forming a first dielectric layer above a structure layer, forming a first opening in the first dielectric layer, and forming a first conductive structure in the first opening. The method also comprises forming a second dielectric layer above the first dielectric layer and above the first conductive structure, forming a second opening in the second dielectric layer above at least a portion of the first conductive structure, the second opening having a side surface and a bottom surface, and forming at least one barrier metal layer in the second opening on the side surface and on the bottom surface. In addition, the method comprises removing a portion of the at least one barrier metal layer from the bottom surface, and forming a second conductive structure in the second opening, the second conductive structure contacting the at least the portion of the first conductive structure.

Abstract: A multi-level wiring structure having: a first wiring formed on an insulating surface, the first wiring containing refractory metal as a main composition thereof; an inter-level insulating film formed to cover the first wiring and having a contact hole at a predetermined region of the first wiring; a second wiring formed over said inter-level insulating film to be electrically connected to an upper surface of the first wiring at a region of the contact hole, the second wiring containing Al as a main composition thereof; and a barrier layer disposed at an interface where the first and second wirings are electrically connected, the barrier layer being made of a material different from, and substantially not reacting with, both Al and the refractory metal constituting the main composition of the first wiring.

Abstract: A method of enhancing the aluminum interconnect properties in very fine metalization patterns interconnecting integrated circuits that improves the texture and electromigration resistance of aluminum in thin films. Enhanced performance can be obtained by forming a smooth oxide layer in situ, or by surface conditioning a previously formed oxide layer in an appropriate manner to provide the requisite surface smoothness, then by refining the aluminum microstructure by hot deposition or ex-situ heat treatment.

Abstract: 16 A thick-film circuit (10) includes an electrically conductive substrate (12), such as stainless steel, and a first layer of a gold-rich conductor (15) applied directly thereon. The gold layer is fired in a non-oxidizing atmosphere, such as nitrogen, to ensure a solid mechanical and electrical connection between the gold and the substrate. A next layer of a silver composition (20) containing a first proportion of silver to a conductive metal is directly applied to the gold layer (15). Preferably, the composition (20) includes palladium in equal parts with the silver to achieve a secure mechanical and electrical contact with the gold layer with a minimum resistivity. A silver-rich layer (23) is then applied directly onto the intermediate layer. This silver-rich layer (23) is a composition of silver and the conductive metal in a second proportion greater than the first proportion. In one embodiment, this second proportion is three parts silver to one part palladium by weight.

Abstract: A semiconductor device comprising a semiconductor substrate including an electronic element, interlayer dielectric (silicon oxide layer and BPSG layer) formed on the semiconductor substrate, a contact hole formed in the interlayer dielectric, a barrier layer formed on the interlayer dielectric and contact hole, and a wiring layer formed on the barrier layer. In the barrier layer, metal oxide (titanium oxide) are scattered in an island-like configuration. The barrier layer is formed by depositing a layer that is used to form the barrier layer and then introducing oxygen into the layer. The step is achieved by depositing a layer for the barrier layer, exposing the layer in oxygen plasma under reduced pressure, and subjecting the layer to the thermal processing, or, alternatively by depositing a layer for the barrier layer and subjecting the layer to thermal processing in an atmosphere of oxygen. The semiconductor device of the present invention has a barrier layer with excellent barrier properties.

Abstract: A process for producing a semiconductor device having an interlayer insulating film of low dielectric constant and interconnects of low resistance and operable at a high speed, which comprises:a step of heat-treating a semiconductor substrate having a lower interconnect,a step of depositing, on the heat-treated semiconductor substrate, an insulating film having a dielectric constant of 3.5 or less,a step of making holes in the insulating film, anda step of growing a metal only in the holes by selective chemical vapor deposition.

Abstract: An interconnect structure and method for an integrated circuit chip for resisting electromigration is described incorporating patterned interconnect layers of Al or Al--Cu and interlayer contact regions or studs of Al.sub.2 Cu between patterned interconnect layers. The invention overcomes the problem of electromigration at high current density in the interconnect structure by providing a continuous path for Cu and/or Al atoms to move in the interconnect structure.

Abstract: An automated apparatus detects electromigration violations in an integrated circuit design. Starting from the lowest hierarchy of the design so far completed, the parasitic (resistance and capacitance) component values extracted from a layout file are propagated up. Then, at the top-most level, lumping algorithms are employed to calculate the parasitic values for all of the top-most level nets. These values are then passed back down to the lower levels and then at each level, the layout is checked using previously computed parasitic values and EM limits. A peak current, AC-average current and AC-rms current are calculated for every layout, and then compared with the process EM rules for violations, in which the optimum line width and number of vias are specified for each interconnection.