Ternary Or Quaternary Semiconductor Comprised Of Elements From Three Different Groups (e.g., I-iii-v, Etc.) Patents (Class 438/930)
  • Patent number: 8404512
    Abstract: The present invention provides methods for forming a doped Group IBIIIAVIA absorber layer for a solar cell. The method includes forming precursor layers that include a dopant rich layer and then annealing the precursor layers. The annealing process results in dopants diffusing through the layers to an exterior surface. The annealing process is periodically halted to remove dopants from the exposed surface.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: March 26, 2013
    Assignee: SoloPower, Inc.
    Inventors: Serdar Aksu, Mustafa Pinarbasi
  • Patent number: 8241943
    Abstract: A method of sodium doping in fabricating CIGS/CIS based thin film solar cells includes providing a shaped substrate member. The method includes forming a barrier layer over the surface region followed by a first electrode layer, and then a sodium bearing layer. A precursor layer of copper, indium, and/or gallium materials having an atomic ratio of copper/group III species no greater than 1.0 is deposited over the sodium bearing layer. The method further includes transferring the shaped substrate member to a second chamber and subjecting it to a thermal treatment process within an environment comprising gas-phase selenium species, followed by an environment comprising gas-phase sulfur species with the selenium species being substantially removed to form an absorber layer.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: August 14, 2012
    Assignee: Stion Corporation
    Inventors: Robert D. Wieting, Steven Aragon, Chester A. Farris, III
  • Patent number: 8129615
    Abstract: The highly mismatched alloy Zn1-yMnyOxTe1-x, 0?y<1 and 0<x<1 and other Group II-IV-Oxygen implanted alloys have been synthesized using the combination of oxygen ion implantation and pulsed laser melting. Incorporation of small quantities of isovalent oxygen leads to the formation of a narrow, oxygen-derived band of extended states located within the band gap of the Zn1-yMnyTe host. With multiple band gaps that fall within the solar energy spectrum, Zn1-yMnyOxTe1-x is a material perfectly satisfying the conditions for single-junction photovoltaics with the potential for power conversion efficiencies surpassing 50%.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: March 6, 2012
    Assignee: The Regents of the University of California
    Inventors: Wladyslaw Walukiewicz, Kin Man Yu, Junqiao Wu
  • Patent number: 8044379
    Abstract: A method of producing silicon nanowires includes providing a substrate in the form of a doped material; formulating an etching solution; and applying an appropriate current density for an appropriate length of time. Related structures and devices composed at least in part from silicon nanowires are also described.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: October 25, 2011
    Assignees: Hitachi Chemical Co., Ltd., Hitachi Chemical Research Center, Inc.
    Inventor: Yongxian Wu
  • Patent number: 7968909
    Abstract: Reconditioned donor substrates that include a remainder substrate from a donor substrate wherein the remainder substrate has a detachment surface where a transfer layer was detached and an opposite surface; and an additional layer deposited upon the opposite surface of the remainder substrate to increase its thickness and to form the reconditioned substrate. The reconditioned substrate is recycled as a donor substrate for fabricating compound material wafers and is typically made from gallium nitride donor substrates.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: June 28, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventor: Frederic Dupont
  • Patent number: 7892938
    Abstract: III-nitride materials are used to form isolation structures in high voltage ICs to isolate low voltage and high voltage functions on a monolithic power IC. Critical performance parameters are improved using III-nitride materials, due to the improved breakdown performance and thermal performance available in III-nitride semiconductor materials. An isolation structure may include a dielectric layer that is epitaxially grown using a III-nitride material to provide a simplified manufacturing process. The process permits the use of planar manufacturing technology to avoid additional manufacturing costs. High voltage power ICs have improved performance in a smaller package in comparison to corresponding silicon structures.
    Type: Grant
    Filed: August 22, 2006
    Date of Patent: February 22, 2011
    Assignee: International Rectifier Corporation
    Inventors: Robert Beach, Paul Bridger
  • Patent number: 7485583
    Abstract: The invention provides a method for fabricating a superlattice semiconductor structure capable of achieving excellent interfacial properties and uniformity. For the superlattice semiconductor structure according to the invention, a substrate is mounted on a susceptor within a process chamber. First and second source gases are supplied simultaneously to two different areas on the susceptor within the chamber to form first and second source gas areas separate from each other. The susceptor is rotated to revolve the substrate through the first and second source gas areas.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: February 3, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Bum Joon Kim, Young Min Kim, Young Chul Shin
  • Patent number: 7459727
    Abstract: The invention concerns an optoelectronic component comprising a layer stack that includes at least two active zones and a carrier that is applied to the layer stack. The invention further concerns a method of fabricating such an optoelectronic component.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: December 2, 2008
    Assignee: Osram Opto Semiconductor GmbH
    Inventor: Peter Stauss
  • Patent number: 6969670
    Abstract: At the time of selective growth of an active layer on a substrate, crystal is previously grown in an active layer non-growth region, and the active layer is grown in an active layer selective growth region. With this configuration, a source supplied to the non-growth region is incorporated in the deposited crystal from the initial stage of growth, so that the supplied amount of the source to the active layer selective growth region is kept nearly at a constant value over the entire period of growth of the active layer, to eliminate degradation of characteristics of the device due to a variation in growth rate of the active layer. In particular, the selective growth method is effective in fabrication of a semiconductor light emitting device including a cladding layer, a guide layer, and an active layer, each of which is formed by selective growth, wherein the active layer has multiple quantum wells.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: November 29, 2005
    Assignee: Sony Corporation
    Inventors: Goshi Biwa, Hiroyuki Okuyama
  • Patent number: 6900069
    Abstract: A method of fabricating a surface-emission type light-emitting device which emits light in a direction perpendicular to a semiconductor substrate, includes the following steps (a) to (e). (a) A step of forming a column-shaped section by etching at least a part of a multilayer film. (b) A step of forming a first resin layer so as to cover the column-shaped section. (c) A step of forming a second resin layer by changing the solubility of the first resin layer in a liquid. (d) A step of immersing, for a specific period of time, at least the column-shaped section and the second resin layer in a liquid in which the second resin layer dissolves, thereby removing the second resin layer at least in the area formed over the column-shaped section. (e) A step of forming an insulating layer by curing the second resin layer.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: May 31, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Tsuyoshi Kaneko, Takayuki Kondo
  • Patent number: 6764888
    Abstract: A method of producing nitride based heterostructure devices by using a quaternary layer comprised of AlInGaN. The quaternary layer may be used in conjunction with a ternary layer in varying thicknesses and compositions that independently adjust polarization charges and band offsets for device structure optimization by using strain compensation profiles. The profiles can be adjusted by altering profiles of molar fractions of In and Al.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: July 20, 2004
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Muhammad Asif Khan, Remigijus Gaska, Michael Shur, Jinwei Yang
  • Publication number: 20040115854
    Abstract: A method of using ammonia to form a GaAs alloy with nitrogen atoms is described. The method includes the operation of introducing ammonia with an agent to assist in the breakdown of the ammonia into a reaction chamber with the GaAs film. Agents that are described include radiation as well as compounds that include aluminum.
    Type: Application
    Filed: December 12, 2002
    Publication date: June 17, 2004
    Applicant: Xerox Corporation.
    Inventors: Michael A. Kneissl, David W. Treat
  • Publication number: 20040115938
    Abstract: The object of the invention is to provide a method of monitoring the chalcogenation process and, in doing so, to enable this process to be controlled and to determine its terminal point.
    Type: Application
    Filed: October 8, 2003
    Publication date: June 17, 2004
    Inventors: Roland Scheer, Christian Pietzker
  • Patent number: 6734033
    Abstract: A light emitting diode is disclosed. The diode includes a silicon carbide substrate having a first conductivity type, a first gallium nitride layer above the SiC substrate having the same conductivity type as the substrate, a superlattice on the GaN layer formed of a plurality of repeating sets of alternating layers selected from among GaN, InGaN, and AlInGaN, a second GaN layer on the superlattice having the same conductivity type as the first GaN layer, a multiple quantum well on the second GaN layer, a third GaN layer on the multiple quantum well, a contact structure on the third GaN layer having the opposite conductivity type from the substrate and the first GaN layer, an ohmic contact to the SiC substrate, and an ohmic contact to the contact structure.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: May 11, 2004
    Assignee: Cree, Inc.
    Inventors: David Todd Emerson, Amber Christine Abare, Michael John Bergmann
  • Patent number: 6667187
    Abstract: A semiconductor laser of present invention is constructed by an aluminium oxide (Al2O3) film on an end surface opposed to a beam emission surface of the semiconductor laser, a silicon nitride (SiNx, or Si3N4) film on the aluminium oxide film, and a silicon oxide (SiO2) film on the silicon nitride film. These films are made successively by a method of Electron Cyclotron Resonance (ECR) sputtering.
    Type: Grant
    Filed: January 25, 2002
    Date of Patent: December 23, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Genei, Makoto Okada
  • Patent number: 6617235
    Abstract: The present invention provides for a method of manufacturing a Group III-V compound semiconductor, which grows a nitrogen-contained Group III-V compound semiconductor of the p-type conductivity, without performing any particular post-processing after growing the compound semiconductor, and which prevents a deterioration in the yield of manufacturing light emitting elements due to post-processing. A first embodiment is directed to a method of manufacturing a Group III-V compound semiconductor which contains p-type impurities and which is expressed by a general formula InxGayAlzN (0≧x≧1,0≧z≧1, x+y+z=1), by thermal decomposition vapor phase method using metalorganics, the method being characterized in that carrier gas is inert gas in which the concentration of hydrogen is 0.5 % or smaller by volume.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: September 9, 2003
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Yasushi Iyechika, Yoshinobu Ono, Tomoyuki Takada
  • Patent number: 6566162
    Abstract: A method of producing a semiconductor film of Cu(MIII)(MVI)2 wherein MIII represents In1-xGax where x is between 0 and 1 and MVI represents SeyS1-y where y is between 0.5 and 1, including the steps of: (a) depositing on a substrate a precursor Cu(MIII)(MVI)2 film having a molar ratio of Cu:MIII of less than 1.0:1.0 but not less than 1.0:1.4 and (b) annealing the precursor film at a temperature of 400-500° C. in an oxygen-containing atmosphere to form a buffer layer of indium oxide and/or gallium oxide and a Cu(In1-xGax)(SeyS1-y)2 film interposed between the substrate and the buffer layer. The buffer layer may be removed by etching with an acid.
    Type: Grant
    Filed: March 14, 2002
    Date of Patent: May 20, 2003
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Akimasa Yamada, Shigeru Niki, Paul Fons, Kakuya Iwata
  • Patent number: 6541297
    Abstract: The method for fabricating a semiconductor device of this invention includes the step of: forming a first compound semiconductor layer by crystal growth on a surface of a semiconductor substrate which includes a plurality of crystal planes having different orientations exposed due to a concave portion and/or a convex portion formed on the semiconductor substrate, the first compound semiconductor layer containing nitrogen and a V group element other than nitrogen.
    Type: Grant
    Filed: April 28, 1999
    Date of Patent: April 1, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Koji Takahashi
  • Patent number: 6518086
    Abstract: A two-stage method of producing thin-films of group IB-IIIA-VIA on a substrate for semiconductor device applications includes a first stage of depositing an amorphous group IB-IIIA-VIA precursor onto an unheated substrate, wherein the precursor contains all of the group IB and group IIIA constituents of the semiconductor thin-film to be produced in the stoichiometric amounts desired for the final product, and a second stage which involves subjecting the precursor to a short thermal treatment at 420° C.-550° C. in a vacuum or under an inert atmosphere to produce a single-phase, group IB-III-VIA film. Preferably the precursor also comprises the group VIA element in the stoichiometric amount desired for the final semiconductor thin-film. The group IB-IIIA-VIA semiconductor films may be, for example, Cu(In,Ga)(Se,S)2 mixed-metal chalcogenides. The resultant supported group IB-IIIA-VIA semiconductor film is suitable for use in photovoltaic applications.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: February 11, 2003
    Assignee: Midwest Research Institute
    Inventors: Markus E. Beck, Rommel Noufi
  • Patent number: 6506618
    Abstract: An undoped GaAs layer is formed on a GaAs substrate. Thallium is adhered to the undoped GaAs layer to a thickness of at least one atomic layer. After adhesion of thallium, GaInNAs is epitaxially grown on the undoped GaAs layer by chemical vapor deposition.
    Type: Grant
    Filed: May 20, 2002
    Date of Patent: January 14, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hirotaka Kizuki, Yasutomo Kajikawa
  • Patent number: 6482672
    Abstract: A method for growing InxGa1−xAs epitaxial layer on a lattice mismatched InP substrate calls for depositing by organo-metallic vapor phase epitaxy, or other epitaxial layer growth technique, a plurality of discreet layers of InAsyP1−y over an InP substrate. These layers provide a buffer. Each succeeding buffer layer has a distinct composition which produces less than a critical amount of lattice mismatch relative to the preceding layer. An InxGa1−xAs epitaxial layer is grown over the buffer wherein 0.53≦x≦0.76. A resulting InGaAs structure comprises an InP substrate with at least one InAsP buffer layer sandwiched between the substrate and the InGaAs epitaxial layer. The buffer layer has a critical lattice mismatch of less than 1.3% relative to the substrate. Additional buffer layers will likewise have a lattice mismatch of no more than 1.3% relative to the preceding layer.
    Type: Grant
    Filed: November 5, 1998
    Date of Patent: November 19, 2002
    Assignee: Essential Research, Inc.
    Inventors: Richard W. Hoffman, David M. Wilt
  • Publication number: 20020160627
    Abstract: Method for treating and/or coating a surface of an object, especially for coating a surface of a substrate such as a semiconductor component or solar cell, in which the surface is supplied with a gas that contains particles that will interact and/or react with the surface, forming a coating thereon. The surface of the object is oriented at an angle &agr; from the vertical, and the gas is directed toward the surface such that it flows along the object by force of convection, starting from the base area of the surface of the object.
    Type: Application
    Filed: April 2, 2002
    Publication date: October 31, 2002
    Inventors: Thomas Kunz, Hilmar Von Campe
  • Patent number: 6429103
    Abstract: A method of fabricating an Emode HIGFET semiconductor device, and the device, is disclosed including epitaxially growing by metal-organic chemical vapor deposition an epitaxial buffer. The buffer includes a layer of short-lifetime gallium arsenide on a gallium arsenide substrate and a layer of aluminum gallium arsenide on the layer of short-lifetime gallium arsenide. The short-lifetime gallium arsenide is grown at a temperature below approximately 550° C. so as to have a lifetime less than approximately 500 picoseconds. A stack of compound semiconductor layers is then epitaxially grown on the layer of aluminum gallium arsenide of the buffer and an Emode field effect transistor is formed in the stack.
    Type: Grant
    Filed: April 13, 2000
    Date of Patent: August 6, 2002
    Assignee: Motorola, Inc.
    Inventors: Eric Shanks Johnson, Nyles Wynn Cody
  • Patent number: 6348703
    Abstract: The present invention provides an epitaxial wafer comprising, on a p-type GaAs single-crystal substrate, a first p-type layer; a p-type cladding layer; a p-type active layer; and an n-type cladding layer, wherein the n-type cladding layer has a carrier concentration of 1×1017 to 1×1018 cm−3; a sulfur concentration of 3×1016 atoms/cm3 or less; and a thickness of 20-50 &mgr;m. The maximum silicon concentration in the portion of the p-type cladding layer within 2 &mgr;m of the interface between the p-type cladding layer and the first p-type layer is less than 1×1018 atoms/cm3; the concentration of carbon, sulfur, or oxygen in the first p-type layer is less than 1×1017 atoms/cm3; the p-type cladding layer has a thickness of 50-80 &mgr;m; the first p-type layer has a carrier concentration of 3×1017 to 1×1018 cm−3; and the n-type cladding layer contains germanium at a concentration of 3×1018 cm−3 or less.
    Type: Grant
    Filed: April 27, 2000
    Date of Patent: February 19, 2002
    Assignee: Showa Denko Kabushiki Kaisha
    Inventors: Atsushi Yoshinaga, Junichi Yamamoto
  • Patent number: 6303485
    Abstract: The present invention proposes a method of producing a gallium nitride-based III-V Group compound semiconductor device. First, beryllium ions are diffused into the p-type layer of gallium nitride to increase hole mobility. Contacts are then added in subsequent procedures, thereby forming contacts having low-impedance ohmic contact layers.
    Type: Grant
    Filed: June 21, 2000
    Date of Patent: October 16, 2001
    Assignee: Arima Optoelectronics Corp.
    Inventors: Ying Che Sung, Weng Ming Liu
  • Patent number: 6258617
    Abstract: A gallium-nitride-based blue light emitting element that is manufacturable through a small number of processes and a method of manufacturing the same are disclosed. A first gallium-nitride-based semiconductor layer containing impurities of a first conductivity type, a gallium-nitridebased semiconductor active layer that is substantially intrinsic, and a second gallium-nitride-based semiconductor layer containing impurities of a second conductivity type that is opposite to the first conductivity type are formed according to a thermal CVD method and are left in an inert gas to cool by themselves.
    Type: Grant
    Filed: April 15, 1997
    Date of Patent: July 10, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Nitta, Hidetoshi Fujimoto, Masayuki Ishikawa
  • Patent number: 6235615
    Abstract: Generation of low work function, stable compound thin films by laser ablation. Compound thin films with low work function can be synthesized by simultaneously laser ablating silicon, for example, and thermal evaporating an alkali metal into an oxygen environment. For example, the compound thin film may be composed of Si/Cs/O. The work functions of the thin films can be varied by changing the silicon/alkali metal/oxygen ratio. Low work functions of the compound thin films deposited on silicon substrates were confirmed by ultraviolet photoelectron spectroscopy (UPS). The compound thin films are stable up to 500° C. as measured by x-ray photoelectron spectroscopy (XPS). Tests have established that for certain chemical compositions and annealing temperatures of the compound thin films, negative electron affinity (NEA) was detected. The low work function, stable compound thin films can be utilized in solar cells, field emission flat panel displays, electron guns, and cold cathode electron guns.
    Type: Grant
    Filed: February 15, 2000
    Date of Patent: May 22, 2001
    Assignee: The Regents of the University of California
    Inventors: Long N. Dinh, William McLean, II, Mehdi Balooch, Edward J. Fehring, Jr., Marcus A. Schildbach
  • Patent number: 6069020
    Abstract: In a method of manufacturing a semiconductor light-emitting device composed of a II-VI compound semiconductor in which at least more than one kind of elements of Zn, Be, Mg, Cd or Hg are used as a II-group element and at least more than one kind of elements of Se, S, Te are used as a VI-group element and which includes first conductivity type and second conductivity type cladding layers and an active layer, a supply ratio VI/II ratio of VI-group element and II-group element required when the active layer is epitaxially deposited is selected to be greater than 1.1 and the active layer is deposited epitaxially. Thus, there may be obtained a highly-reliable semiconductor light-emitting device whose life time is made longer.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: May 30, 2000
    Assignee: Sony Corporation
    Inventors: Eisaku Kato, Hiroyasu Noguchi, Masaharu Nagai
  • Patent number: 6046068
    Abstract: A method, suitable for forming metal contacts on a semiconductor substrate at positions for defining radiation detector cells, includes the steps of forming one or more layers of material on a surface of the substrate with openings to the substrate surface at the contact positions; forming a layer of metal over the layer(s) of material and the openings; and removing metal overlying the layer(s) of material to separate individual contacts. Optionally, a passivation layer to be left between individual contacts on the substrate surface may be applied. Etchants used for removing unwanted gold (or other contact matter) are preferably prevented from coming into contact with the surface of the substrate, thereby avoiding degradation of the resistive properties of the substrate.
    Type: Grant
    Filed: November 26, 1996
    Date of Patent: April 4, 2000
    Assignee: Simage Oy
    Inventors: Risto O. Orava, Jouni I. Pyyhtia, Tom G. Schulman, Miltiadis E. Sarakinos, Konstantinos E. Spartiotis, Panu Y. Jalas
  • Patent number: 5998304
    Abstract: A liquid phase deposition method involves the use of a supersaturated hydrofluosilicic acid aqueous solution for growing a silicon dioxide film at low temperature (30.degree. C.-50.degree. C.) on a III-V semiconductor, such as a gallium arsenide substrate. The silicon dioxide film may be used in a bipolar transistor or as a field oxide of MOS (metal oxide semiconductor). The III-V semiconductor substrate is chemically treated with an alkaline aqueous solution such as ammonium hydroxide so that the surface of the III-V semiconductor substrate is modified to facilitate the growth of the silicon dioxide film by liquid phase deposition. The growth rate of the silicon dioxide film is as fast as 1265 .ANG./hr. The silicon dioxide film has a refractive index ranging between 1.372 and 1.41.
    Type: Grant
    Filed: September 2, 1997
    Date of Patent: December 7, 1999
    Assignee: National Science Council
    Inventors: Mau-Phon Houng, Yeong-Her Wang, Chien-Jung Huang
  • Patent number: 5935324
    Abstract: An apparatus for forming I-III-VI.sub.2 thin-film layers has a reaction chamber made of a carbon material in which a precursor for forming a I-III-VI.sub.2 thin-film layer and a vapor source of an element of group VI of the periodic table are placed. The precursor and vapor source are heated under vacuum to form the I-III-VI.sub.2 thin-film layer. The reaction chamber is divided into a reaction compartment A having the precursor placed therein and a reaction compartment B having the vapor element of group IV placed therein. A communication channel C is provided between the reaction compartments A and B, and a heating unit controlled by a temperature control unit is provided exterior to each of the reaction compartments A and B.
    Type: Grant
    Filed: April 28, 1997
    Date of Patent: August 10, 1999
    Assignee: Yazaki Corporation
    Inventors: Shinnichi Nakagawa, Kenji Sato, Masami Nakamura, Kazuhiro Toyoda, Takeshi Kamiya, Kazue Suzuki, Hiroki Ishihara, Takeshi Ikeya, Masaharu Ishida
  • Patent number: 5930656
    Abstract: A substrate for forming a compound semiconductor device is placed in a reaction chamber. An MOCVD method or a GS-MBE method is used to grow compound semiconductor layers on the substrate. The grown layers include, for example, a GaN buffer layer, an n-GaN layer, an InGaN active layer, a p-AlGaN layer, and a p.sup.+ -GaN contact layer. After the growth of the layers, the substrate is kept in the reaction chamber, and a passivation film of, for example, SiNx, SiO2, or SiON is formed on top of the grown layers according to a CVD or GS-MBE method. Since the top of the grown layers is not exposed to air outside the reaction chamber, no oxidization or contamination occurs on the top of the grown layers. The compound semiconductor device is manufactured through simpler processes compared with a prior art that needs separate apparatuses for growing and forming the layers and passivation film.
    Type: Grant
    Filed: October 17, 1997
    Date of Patent: July 27, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chisato Furukawa, Masayuki Ishikawa, Hideto Sugawara, Kenji Isomoto
  • Patent number: 5780322
    Abstract: A method for growing a II-VI compound semiconductor layer containing Cd, such as Zn.sub.1-x Cd.sub.x Se, by a molecular beam epitaxy method is disclosed. During the growth, the ratio of the intensity of molecular beams of a group VI element to the intensity of molecular beams of a group II element in terms of intensities of molecular beams actually irradiated onto a substrate, namely, the substantial VI/II ratio, is controlled preferably in the range from 0.7 to 1.3, to increase the Cd incorporating efficiency into the grown layer sufficiently high.
    Type: Grant
    Filed: September 27, 1996
    Date of Patent: July 14, 1998
    Assignee: Sony Corporation
    Inventors: Koshi Tamamura, Hironori Tsukamoto, Masao Ikeda
  • Patent number: RE43725
    Abstract: A light emitting diode is disclosed. The diode includes a silicon carbide substrate having a first conductivity type, a first gallium nitride layer above the SiC substrate having the same conductivity type as the substrate, a superlattice on the GaN layer formed of a plurality of repeating sets of alternating layers selected from among GaN, InGaN, and AlInGaN, a second GaN layer on the superlattice having the same conductivity type as the first GaN layer, a multiple quantum well on the second GaN layer, a third GaN layer on the multiple quantum well, a contact structure on the third GaN layer having the opposite conductivity type from the substrate and the first GaN layer, an ohmic contact to the SiC substrate, and an ohmic contact to the contact structure.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: October 9, 2012
    Assignee: Cree, Inc.
    Inventors: David Todd Emerson, Amber Christine Abare, Michael John Bergmann