Abstract: A vapor phase epitaxy method of growing a III-V layer with a doping profile that changes from a p-doping to an n-doping on a surface of a substrate or a preceding layer from the vapor phase from an epitaxial gas flow, at least one first precursor for an element of main group III, and at least one second precursor for an element of main group V. When a first growth height is reached, a first initial doping level is set by means of a ratio of a first mass flow of the first precursor to a second mass flow of the second precursor in the epitaxial gas flow, and subsequently, by stepwise or continuously changing the ratio of the first mass flow to the second mass flow and by stepwise or continuously increasing a mass flow of a third precursor for an n-type dopant in the epitaxial gas flow.

Abstract: A vapor phase epitaxy method of growing a III-V layer with a doping that changes from a first conductivity type to a second conductivity type on a surface of a substrate or a preceding layer in a reaction chamber from the vapor phase from an epitaxial gas flow comprising a carrier gas, at least one first precursor for an element from main group III, and at least one second precursor for an element from main group V, wherein when a first growth height is reached, a first initial doping level of the first conductivity type is set by means of a ratio of a first mass flow of the first precursor to a second mass flow of the second precursor in the epitaxial gas flow, the first initial doping level is then reduced to a second initial doping level of the first or low second conductivity type.

Abstract: A method of performing HVPE heteroepitaxy comprises exposing a substrate to a carrier gas, a first precursor gas, a Group II/III element, and ternary-forming gasses (V/VI group precursor), to form a heteroepitaxial growth of a binary, ternary, and/or quaternary compound on the substrate; wherein the carrier gas is H2, wherein the first precursor gas is HCl, the Group II/III element comprises at least one of Zn, Cd, Hg, Al, Ga, and In; and wherein the ternary-forming gasses comprise at least two or more of AsH3 (arsine), PH3 (phosphine), H2Se (hydrogen selenide), H2Te (hydrogen telluride), SbH3 (hydrogen antimonide, or antimony tri-hydride, or stibine), H2S (hydrogen sulfide), NH3 (ammonia), and HF (hydrogen fluoride); flowing the carrier gas over the Group II/III element; exposing the substrate to the ternary-forming gasses in a predetermined ratio of first ternary-forming gas to second ternary-forming gas (1tf:2tf ratio); and changing the 1tf:2tf ratio over time.

Abstract: A method of performing heteroepitaxy comprises exposing a substrate to a carrier gas, a first precursor gas, a Group II/III element, and a second precursor gas, to form a heteroepitaxial growth of one of GaAs, AlAs, InAs, GaP, InP, ZnSe, GaSe, CdSe, InSe, ZnTe, CdTe, GaTe, HgTe, GaSb, InSb, AlSb, CdS, GaN, and AlN on the substrate; wherein the substrate comprises one of GaAs, AlAs, InAs, GaP, InP, ZnSe, GaSe, CdSe, InSe, ZnTe, CdTe, GaTe, HgTe, GaSb, InSb, AlSb, CdS, GaN, and AlN; wherein the carrier gas is H2, wherein the first precursor is HCl, the Group II/III element comprises at least one of Zn, Cd, Hg, Al, Ga, and In; and wherein the second precursor is one of AsH3 (arsine), PH3 (phosphine), H2Se (hydrogen selenide), H2Te (hydrogen telluride), SbH3 (hydrogen antimonide), H2S (hydrogen sulfide), and NH3 (ammonia). The process may be an HVPE (hydride vapor phase epitaxy) process.

Abstract: Methods, devices, and systems associated with oxide based memory can include a method of forming a resistive switching region of a memory cell. Forming a resistive switching region of a memory cell can include forming a metal oxide material on an electrode and forming a metal material on the metal oxide material, wherein the metal material formation causes a reaction that results in a graded metal oxide portion of the memory cell.

Abstract: A semiconductor device includes a silicon substrate, an aluminum nitride layer which is arranged on the silicon substrate and has a region where silicon is doped thereof as an impurity, a buffer layer which is arranged on the aluminum nitride layer and has a structure where a plurality of nitride semiconductor films are laminated, and a semiconductor functional layer which is arranged on the buffer layer and made of nitride semiconductor.

Abstract: A semiconductor device includes a semiconductor layer stack formed on a substrate, a first ohmic electrode and a second ohmic electrode which are formed on the semiconductor layer stack, and are spaced from each other, a first control layer formed between the first ohmic electrode and the second ohmic electrode, and a first gate electrode formed on the first control layer. The first control layer includes a lower layer, an intermediate layer which is formed on the lower layer, and has lower impurity concentration than the lower layer, and an upper layer which is formed on the intermediate layer, and has higher impurity concentration than the intermediate layer.

Abstract: The present invention provides a light-emitting element having less increase in driving voltage with the accumulation of light-emission time, and provides a light-emitting element having less increase in resistance value with the increase in film thickness. A light-emitting element includes a first layer, a second layer and a third layer between a first electrode and a second electrode. The first layer is provided to be closer to the first electrode than the second layer, and the third layer is provided to be closer to the second electrode than the second layer. The first layer is a layer including an aromatic amine compound and a substance showing an electron accepting property to the aromatic amine compound. The second layer includes a substance of which an electron transporting property is stronger than a hole transporting property, and a substance showing an electron donating property to the aforementioned substance.

Abstract: A light-emitting diode includes a substrate, a compound semiconductor layer including a p-n junction-type light-emitting part formed on the substrate, an electric conductor disposed on the compound semiconductor layer and formed of an electrically conductive material optically transparent to the light emitted from the light-emitting part and a high resistance layer possessing higher resistance than the electric conductor and provided in the middle between the compound semiconductor layer and the electric conductor. In the configuration of a light-emitting diode lamp, the electric conductor and the electrode disposed on the semiconductor layer on the side opposite to the electric conductor across the light-emitting layer are made to assume an equal electric potential by means of wire bonding. The light-emitting diode abounds in luminance and excels in electrostatic breakdown voltage.

Abstract: A semiconductor device capable of avoiding generation of a barrier in a conduction band while maintaining high withstanding voltage and enabling high speed transistor operation at high current in a double hetero bipolar transistor, as well as a manufacturing method thereof, wherein a portion of the base and the collector is formed of a material with a forbidden band width narrower than that of a semiconductor substrate, a region where the forbidden band increases stepwise and continuously from the emitter side to the collector side is disposed in the inside of the base and the forbidden band width at the base-collector interface is designed so as to be larger than the minimum forbidden band width in the base, whereby the forbidden band width at the base layer edge on the collector side can be made closer to the forbidden band width of the semiconductor substrate than usual while sufficiently maintaining the hetero effect near the emitter-base thereby capable of decreasing the height of the energy barrier gene

Abstract: A novel method for synthesizing device-quality alloys and ordered phases in a Si—Ge—Sn system uses a UHV-CVD process and reactions of SnD4 with SiH3GeH3. Using the method, single-phase SixSnyGe1-x-y semiconductors (x?0.25, y?0.11) are grown on Si via Ge1-xSnx buffer layers The Ge1-xSnx buffer layers facilitate heteroepitaxial growth of the SixSnyGe1-x-y films and act as compliant templates that can conform structurally and absorb the differential strain imposed by the more rigid Si and Si—Ge—Sn materials. The SiH3GeH3 species was prepared using a new and high yield method that provided high purity semiconductor grade material.

Abstract: Disclosed is a light-emitting device (100) has a light-emitting layer portion (24) which is composed of a group III-V compound semiconductor and a transparent thick-film semiconductor layer (90) with a thickness of not less than 40 ?m which is formed on at least one major surface side of the light-emitting layer portion (24) and composed of a group III-V compound semiconductor having a band gap energy larger than the photon energy equivalent of the peak wavelength of emission flux from the light-emitting layer portion (24). The transparent thick-film semiconductor layer (90) has a lateral surface portion (90S) which is a chemically etched surface. The dopant concentration of the transparent thick-film semiconductor layer (90) is not less than 5×1016/cm3 and not more than 2×1018/cm3. The light-emitting device can have a transparent thick-film semiconductor layer while being significantly improved in light taking-out efficiency from the lateral surface portion.

Abstract: A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1-x), where the proportion x of a second semiconductor material can be set freely. Furthermore, a gate insulation layer and a gate layer are formed on the strained semiconductor layer. To define an undoped channel region, drain/source regions are formed laterally with respect to the gate layer at least in the strained semiconductor layer. The possibility of freely setting the Ge proportion x enables a threshold voltage to be set as desired, whereby modern logic semiconductor components can be realized.

Abstract: Techniques and devices are described to use spatially-varying curvature information of a layered structure to determine stresses at each location with non-local contributions from other locations of the structure. For example, a local contribution to stresses at a selected location on a layered structure formed on a substrate is determined from curvature changes at the selected location and a non-local contribution to the stresses at the selected location is also determined from curvature changes at all locations across the layered structure. Next, the local contribution and the non-local contribution are combined to determine the total stresses at the selected location. Techniques and devices for determining a misfit strain between a film and a substrate on which the film is deposited are also described.

Abstract: A resistance change memory device including: a semiconductor substrate; cell arrays stacked above the substrate, bit lines word lines; a read/write circuit formed on the semiconductor substrate; first and second vertical wirings disposed to connect the bit lines to the read/write circuit; and third vertical wirings disposed to connect the word lines to the read/write circuit, wherein the memory cell includes a variable resistance element for storing as information a resistance value, which has a recording layer formed of a first composite compound expressed by AxMyOz (where “A” and “M” are cation elements different from each other; “O” oxygen; and 0.5?x?1.5, 0.5?y?2.5 and 1.5?z?4.5) and a second composite compound containing at least one transition element and a cavity site for housing a cation ion.

Abstract: The present invention is a novel field effect transistor having a channel region formed from a narrow bandgap semiconductor film formed on an insulating substrate. A gate dielectric layer is formed on the narrow bandgap semiconductor film. A gate electrode is then formed on the gate dielectric. A pair of source/drain regions formed from a wide bandgap semiconductor film or a metal is formed on opposite sides of the gate electrode and adjacent to the low bandgap semiconductor film.

Abstract: A SiGe spacer layer 151, a graded SiGe base layer 152 including boron, and an Si-cap layer 153 are sequentially grown through epitaxial growth over a collector layer 102 on an Si substrate. A second deposited oxide film 112 having a base opening portion 118 and a P+ polysilicon layer 115 that will be made into an emitter connecting electrode filling the base opening portion are formed on the Si-cap layer 153, and an emitter diffusion layer 153a is formed by diffusing phosphorus into the Si-cap layer 153. When the Si-cap layer 153 is grown, by allowing the Si-cap layer 153 to include boron only at the upper part thereof by in-situ doping, the width of a depletion layer 154 is narrowed and a recombination current is reduced, thereby making it possible to improve the linearity of the current characteristics.

Abstract: Provide is a 3-5 group compound semiconductor having a concentration of a p-type dopant of 1×1017 cm− or more and 1×1021 cm−3 or less, which can be laminated to control the carrier concentration of an InGaAlN-type mixed crystal in a low range with high reproducibility. Also provided is a 3-5 group compound semiconductor in which the carrier concentration of an InGaAlN-type mixed crystal is controlled in a low range with high reproducibility, and a light emitting device having high light emitting efficiency.

Abstract: The light emitting diode includes an intermediate layer made of non-single crystalline material between single crystalline layers. By the intermediate layer, the boundary characteristic between the single crystalline layers may be improved and the defect caused by the lattice mismatch can be decreased, so that the brightness and forward voltage characteristics can be improved.

Abstract: Several methods for producing an active region for a long wavelength light emitting device are disclosed. In one embodiment, the method comprises placing a substrate in an organometallic vapor phase epitaxy (OMVPE) reactor, the substrate for supporting growth of an indium gallium arsenide nitride (InGaAsN) film, supplying to the reactor a group-III-V precursor mixture comprising arsine, dimethylhydrazine, alkyl-gallium, alkyl-indium and a carrier gas, where the arsine and the dimethylhydrazine are the group-V precursor materials and where the percentage of dimethylhydrazine substantially exceeds the percentage of arsine, and pressurizing the reactor to a pressure at which a concentration of nitrogen commensurate with light emission at a wavelength longer than 1.2 um is extracted from the dimethylhydrazine and deposited on the substrate.

Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

Abstract: There is a method for forming a multilayer electronic device. The method has the following steps: a) depositing a thin molecular layer on an electrically conductive substrate and b) depositing metal atoms or ions on the thin molecular layer at an angle of about 60 degrees or less with respect to the plane of the exposed surface of the thin molecular layer.

Abstract: A method produces structures for semiconductor components, particularly BH laser diodes, in which a mask material is applied to a sample in a masking step. The etch rate in an etching step depends upon the composition and/or nature of the mask material. The etch rate is selected in such a way so that the mask is at least partly dissolved during the etching step. It is therefore possible to easily remove the mask from the semiconductor material and apply additional layers in situ during the fabrication of semiconductor components.

Abstract: A substrate processing apparatus for forming a boron doped silicon-germanium film on one or more substrates in a reaction furnace of a low pressure CVD apparatus uses a mixture gas of GeH4 and SiH4 as a reaction gas, and BCl3 as a doping gas. The substrate processing apparatus includes a plurality of gas outlets for supplying GeH4 at different locations in the reaction tube and a doping gas line for supplying BCl3 at least at an upstream side of gas flow in the reaction tube.

Abstract: A semiconductor layer is co-doped with two dopants. The first dopant is to generate charge carriers in the semiconductor material, and the second dopant is to promote atomic disorder within the material. When the semiconductor material is annealed, the second dopant becomes mobile and moves through the lattice so as to promote atomic disorder. This eliminates unwanted effects such as, for example, a reduction in the forbidden bandgap that can otherwise arise as a result of atomic ordering. The amount of diffusion of the second dopant during the annealing can be increased by making the initial concentration of the second dopant non-uniform over the volume of the semiconductor material.

Abstract: The field effect device consisting of a substrate, a conducting backplane formed in the substrate, a source and a drain disposed above the conductive backplane, a gate insultatively disposed above the substrate between the source and drain, and a backgate contact electrically coupled to the conducting backplane.

Abstract: A method for growing InxGa1−xAs epitaxial layer on a lattice mismatched InP substrate calls for depositing by organo-metallic vapor phase epitaxy, or other epitaxial layer growth technique, a plurality of discreet layers of InAsyP1−y over an InP substrate. These layers provide a buffer. Each succeeding buffer layer has a distinct composition which produces less than a critical amount of lattice mismatch relative to the preceding layer. An InxGa1−xAs epitaxial layer is grown over the buffer wherein 0.53≦x≦0.76. A resulting InGaAs structure comprises an InP substrate with at least one InAsP buffer layer sandwiched between the substrate and the InGaAs epitaxial layer. The buffer layer has a critical lattice mismatch of less than 1.3% relative to the substrate. Additional buffer layers will likewise have a lattice mismatch of no more than 1.3% relative to the preceding layer.

Abstract: A semiconductor device includes a substrate, a multi-layer structure provided on the substrate, a first-conductive-type etch stop layer of a III nitride provided on the multi-layer structure, and a second-conductive-type first semiconductor layer of a III nitride provided on the etch stop layer. A molar fraction of Al is lower in a composition of the III nitride included in the first semiconductor layer than in a composition of the III nitride included in the etch stop layer.

Abstract: A semiconductor light-emitting device has a light-emitting section comprised of at least a lower clad layer, an active layer and an upper clad layer which are formed on a compound semiconductor substrate and a layer grown on the upper clad layer of the light-emitting section. When growing the current diffusion layer from a crystal interface on the upper clad layer in a lattice mismatching state in which the absolute value of a lattice matching factor &Dgr;a/a is not lower than 0.25% with respect to the upper clad layer at a crystal interface where the crystal composition changes on the upper clad layer of the light-emitting section, the growth rate at least at the start time of growth is made to be 1.0 &mgr;m/h or less.

Abstract: The semiconductor laser device has a lower clad layer, an active layer, an upper clad layer, a forward mesa forming layer, a contact layer and an insulating film, sequentially formed on the semiconductor substrate. The upper clad layer, the forward mesa forming layer, the contact layer and the insulating film form a ridge. The etching speed of the forward mesa forming layer is higher than that of the upper clad layer and lower than that of the contact layer. Because of such etching speeds, the ridge having a forward mesa structure is formed.

Abstract: A semiconductor photodetection device includes a photodetection layer formed of an alternate and repetitive stacking of an optical absorption layer accumulating therein a compressive strain and a stress-compensating layer accumulating therein a compensating tensile strain, wherein the optical absorption layer has a thickness larger than a thickness of the stress-compensating layer.

Abstract: A plurality of different wavelength semiconductor lasers are fabricated on a single semiconductor substrate by establishing a thermal gradient across the substrate during epitaxial growth. The result is a variation in composition which produces a corresponding variation of laser wavelength across the substrate. The thermal gradient is preferably achieved by disposing a patterned layer of material (heat reflecting or heat absorbing) on the back side of the substrate, radiatively heating the backside and growing the active layers on the front side. The backside layer is removed when the substrate is lapped to final thickness.

Abstract: According to one embodiment, a memory device comprises a bit line operable to access a memory cell. The bit line has a first end and a second end. A first equilibration circuit is coupled to the first end of the bit line, and a second equilibration circuit is coupled to the second end of the bit line. The first and second equilibration circuits cooperate to pre-charge the bit line. According to another embodiment, an embedded-process memory device comprises a p-well and a deep n-well formed into a substrate. A retrograde well is formed into the deep n-well. An equilibration circuit for pre-charging a bit line is formed into the retrograde well.

Abstract: A photoelectric conversion device includes a plurality of photoelectric conversion units and a signal output unit. The signal output unit has at least one storage device for storing electrical signals generated by the photoelectric conversion device. A scanning device scans the electrical signals generated by the electric conversion units, and a reading device reads out electrical signals generated by the photoelectric conversion units. Each of the photoelectric conversion units includes a light absorption layer and a multiplication layer. The multiplication layer includes at least one step-back structure which multiplies carriers produced by absorption of light, and in which a forbidden band width changes continuously from a minimum to a maximum width.

Abstract: A high gain, high frequency transistor is formed having a combination of a moderately doped retrograde emitter and a collector which is formed by self-aligned implantation through an emitter opening window. This combination allows continued base width scaling and ensures high current capability yet limits the electric field at the emitter-base junction, particularly near the base contacts, in order to reduce leakage and capacitance and to enhance breakdown voltage. Cut-off frequencies on the order of 100 GHz can thus be obtained in the performance of a transistor with a 30 nm base width in a SiGe device.

Abstract: A process and structure for an improved collector-up bipolar transistor. The base is formed after the emitter is implanted to eliminate base damage during oxygen implantation typical in prior art collector-up bipolar transistors. In a preferred embodiment, an emitter layer of GaAlAs is implanted with oxygen in the extrinsic emitter region to damage the material and make it insulative. The base is epitaxially grown at low temperature to insure the emitter material remains damaged and insulative.

Abstract: The present invention broadly concerns layered structures of substantially-crystalline materials and processes for making such structures. More particularly, the invention concerns epitaxial growth of a substantially-crystalline layer of a first material on a substantially-crystalline second material different from the first material utilizing an approximately one monolayer thick monovalent surfactant element.

Abstract: A variable-capacitance device has an n-type diffusion layer which has an impurity concentration profile such that a region where the impurity concentration remains substantially constant and a region where the impurity concentration changes abruptly are alternately repeated, and the impurity concentration increases as the deepness from the surface increases. The impurity concentration profile can be achieved by implanting n-type impurity atoms a plurality of times with different energies in an ion implantation process or varying the concentration of n-type impurity atoms such as of phosphorus added upon epitaxial layer growth. The variable-capacitance device, and a semiconductor integrated circuit device composed of a plurality of such variable-capacitance devices can be fabricated on a semiconductor substrate, and are highly stable.